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path: root/drivers/scsi/bfa/bfa_core.c
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Diffstat (limited to 'drivers/scsi/bfa/bfa_core.c')
-rw-r--r--drivers/scsi/bfa/bfa_core.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/scsi/bfa/bfa_core.c b/drivers/scsi/bfa/bfa_core.c
index 73669245c2c..f75c6be7b84 100644
--- a/drivers/scsi/bfa/bfa_core.c
+++ b/drivers/scsi/bfa/bfa_core.c
@@ -113,7 +113,7 @@ bfa_intx(struct bfa_s *bfa)
113 u32 intr, qintr; 113 u32 intr, qintr;
114 int queue; 114 int queue;
115 115
116 intr = bfa_reg_read(bfa->iocfc.bfa_regs.intr_status); 116 intr = readl(bfa->iocfc.bfa_regs.intr_status);
117 if (!intr) 117 if (!intr)
118 return BFA_FALSE; 118 return BFA_FALSE;
119 119
@@ -121,7 +121,7 @@ bfa_intx(struct bfa_s *bfa)
121 * RME completion queue interrupt 121 * RME completion queue interrupt
122 */ 122 */
123 qintr = intr & __HFN_INT_RME_MASK; 123 qintr = intr & __HFN_INT_RME_MASK;
124 bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, qintr); 124 writel(qintr, bfa->iocfc.bfa_regs.intr_status);
125 125
126 for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) { 126 for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) {
127 if (intr & (__HFN_INT_RME_Q0 << queue)) 127 if (intr & (__HFN_INT_RME_Q0 << queue))
@@ -135,7 +135,7 @@ bfa_intx(struct bfa_s *bfa)
135 * CPE completion queue interrupt 135 * CPE completion queue interrupt
136 */ 136 */
137 qintr = intr & __HFN_INT_CPE_MASK; 137 qintr = intr & __HFN_INT_CPE_MASK;
138 bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, qintr); 138 writel(qintr, bfa->iocfc.bfa_regs.intr_status);
139 139
140 for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) { 140 for (queue = 0; queue < BFI_IOC_MAX_CQS_ASIC; queue++) {
141 if (intr & (__HFN_INT_CPE_Q0 << queue)) 141 if (intr & (__HFN_INT_CPE_Q0 << queue))
@@ -153,13 +153,13 @@ bfa_intx(struct bfa_s *bfa)
153void 153void
154bfa_intx_enable(struct bfa_s *bfa) 154bfa_intx_enable(struct bfa_s *bfa)
155{ 155{
156 bfa_reg_write(bfa->iocfc.bfa_regs.intr_mask, bfa->iocfc.intr_mask); 156 writel(bfa->iocfc.intr_mask, bfa->iocfc.bfa_regs.intr_mask);
157} 157}
158 158
159void 159void
160bfa_intx_disable(struct bfa_s *bfa) 160bfa_intx_disable(struct bfa_s *bfa)
161{ 161{
162 bfa_reg_write(bfa->iocfc.bfa_regs.intr_mask, -1L); 162 writel(-1L, bfa->iocfc.bfa_regs.intr_mask);
163} 163}
164 164
165void 165void
@@ -188,8 +188,8 @@ bfa_isr_enable(struct bfa_s *bfa)
188 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | 188 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 |
189 __HFN_INT_MBOX_LPU1); 189 __HFN_INT_MBOX_LPU1);
190 190
191 bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, intr_unmask); 191 writel(intr_unmask, bfa->iocfc.bfa_regs.intr_status);
192 bfa_reg_write(bfa->iocfc.bfa_regs.intr_mask, ~intr_unmask); 192 writel(~intr_unmask, bfa->iocfc.bfa_regs.intr_mask);
193 bfa->iocfc.intr_mask = ~intr_unmask; 193 bfa->iocfc.intr_mask = ~intr_unmask;
194 bfa_isr_mode_set(bfa, bfa->msix.nvecs != 0); 194 bfa_isr_mode_set(bfa, bfa->msix.nvecs != 0);
195} 195}
@@ -198,7 +198,7 @@ void
198bfa_isr_disable(struct bfa_s *bfa) 198bfa_isr_disable(struct bfa_s *bfa)
199{ 199{
200 bfa_isr_mode_set(bfa, BFA_FALSE); 200 bfa_isr_mode_set(bfa, BFA_FALSE);
201 bfa_reg_write(bfa->iocfc.bfa_regs.intr_mask, -1L); 201 writel(-1L, bfa->iocfc.bfa_regs.intr_mask);
202 bfa_msix_uninstall(bfa); 202 bfa_msix_uninstall(bfa);
203} 203}
204 204
@@ -263,7 +263,7 @@ bfa_msix_rspq(struct bfa_s *bfa, int qid)
263 * update CI 263 * update CI
264 */ 264 */
265 bfa_rspq_ci(bfa, qid) = pi; 265 bfa_rspq_ci(bfa, qid) = pi;
266 bfa_reg_write(bfa->iocfc.bfa_regs.rme_q_ci[qid], pi); 266 writel(pi, bfa->iocfc.bfa_regs.rme_q_ci[qid]);
267 mmiowb(); 267 mmiowb();
268 268
269 /** 269 /**
@@ -279,7 +279,7 @@ bfa_msix_lpu_err(struct bfa_s *bfa, int vec)
279{ 279{
280 u32 intr, curr_value; 280 u32 intr, curr_value;
281 281
282 intr = bfa_reg_read(bfa->iocfc.bfa_regs.intr_status); 282 intr = readl(bfa->iocfc.bfa_regs.intr_status);
283 283
284 if (intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1)) 284 if (intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1))
285 bfa_msix_lpu(bfa); 285 bfa_msix_lpu(bfa);
@@ -294,9 +294,9 @@ bfa_msix_lpu_err(struct bfa_s *bfa, int vec)
294 * Register needs to be cleared as well so Interrupt 294 * Register needs to be cleared as well so Interrupt
295 * Status Register will be cleared. 295 * Status Register will be cleared.
296 */ 296 */
297 curr_value = bfa_reg_read(bfa->ioc.ioc_regs.ll_halt); 297 curr_value = readl(bfa->ioc.ioc_regs.ll_halt);
298 curr_value &= ~__FW_INIT_HALT_P; 298 curr_value &= ~__FW_INIT_HALT_P;
299 bfa_reg_write(bfa->ioc.ioc_regs.ll_halt, curr_value); 299 writel(curr_value, bfa->ioc.ioc_regs.ll_halt);
300 } 300 }
301 301
302 if (intr & __HFN_INT_ERR_PSS) { 302 if (intr & __HFN_INT_ERR_PSS) {
@@ -305,14 +305,14 @@ bfa_msix_lpu_err(struct bfa_s *bfa, int vec)
305 * interrups are shared so driver's interrupt handler is 305 * interrups are shared so driver's interrupt handler is
306 * still called eventhough it is already masked out. 306 * still called eventhough it is already masked out.
307 */ 307 */
308 curr_value = bfa_reg_read( 308 curr_value = readl(
309 bfa->ioc.ioc_regs.pss_err_status_reg); 309 bfa->ioc.ioc_regs.pss_err_status_reg);
310 curr_value &= __PSS_ERR_STATUS_SET; 310 curr_value &= __PSS_ERR_STATUS_SET;
311 bfa_reg_write(bfa->ioc.ioc_regs.pss_err_status_reg, 311 writel(curr_value,
312 curr_value); 312 bfa->ioc.ioc_regs.pss_err_status_reg);
313 } 313 }
314 314
315 bfa_reg_write(bfa->iocfc.bfa_regs.intr_status, intr); 315 writel(intr, bfa->iocfc.bfa_regs.intr_status);
316 bfa_msix_errint(bfa, intr); 316 bfa_msix_errint(bfa, intr);
317 } 317 }
318} 318}