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1/*
2 * 53c710 driver. Modified from Drew Eckhardts driver
3 * for 53c810 by Richard Hirst [richard@sleepie.demon.co.uk]
4 *
5 * I have left the code for the 53c8xx family in here, because it didn't
6 * seem worth removing it. The possibility of IO_MAPPED chips rather
7 * than MEMORY_MAPPED remains, in case someone wants to add support for
8 * 53c710 chips on Intel PCs (some older machines have them on the
9 * motherboard).
10 *
11 * NOTE THERE MAY BE PROBLEMS WITH CASTS IN read8 AND Co.
12 */
13
14/*
15 * NCR 53c{7,8}0x0 driver, header file
16 *
17 * Sponsored by
18 * iX Multiuser Multitasking Magazine
19 * Hannover, Germany
20 * hm@ix.de
21 *
22 * Copyright 1993, 1994, 1995 Drew Eckhardt
23 * Visionary Computing
24 * (Unix and Linux consulting and custom programming)
25 * drew@PoohSticks.ORG
26 * +1 (303) 786-7975
27 *
28 * TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
29 *
30 * PRE-ALPHA
31 *
32 * For more information, please consult
33 *
34 * NCR 53C700/53C700-66
35 * SCSI I/O Processor
36 * Data Manual
37 *
38 * NCR 53C810
39 * PCI-SCSI I/O Processor
40 * Data Manual
41 *
42 * NCR Microelectronics
43 * 1635 Aeroplaza Drive
44 * Colorado Springs, CO 80916
45 * +1 (719) 578-3400
46 *
47 * Toll free literature number
48 * +1 (800) 334-5454
49 *
50 */
51
52#ifndef NCR53c710_H
53#define NCR53c710_H
54
55#ifndef HOSTS_C
56
57/* SCSI control 0 rw, default = 0xc0 */
58#define SCNTL0_REG 0x00
59#define SCNTL0_ARB1 0x80 /* 0 0 = simple arbitration */
60#define SCNTL0_ARB2 0x40 /* 1 1 = full arbitration */
61#define SCNTL0_STRT 0x20 /* Start Sequence */
62#define SCNTL0_WATN 0x10 /* Select with ATN */
63#define SCNTL0_EPC 0x08 /* Enable parity checking */
64/* Bit 2 is reserved on 800 series chips */
65#define SCNTL0_EPG_700 0x04 /* Enable parity generation */
66#define SCNTL0_AAP 0x02 /* ATN/ on parity error */
67#define SCNTL0_TRG 0x01 /* Target mode */
68
69/* SCSI control 1 rw, default = 0x00 */
70
71#define SCNTL1_REG 0x01
72#define SCNTL1_EXC 0x80 /* Extra Clock Cycle of Data setup */
73#define SCNTL1_ADB 0x40 /* contents of SODL on bus */
74#define SCNTL1_ESR_700 0x20 /* Enable SIOP response to selection
75 and reselection */
76#define SCNTL1_DHP_800 0x20 /* Disable halt on parity error or ATN
77 target mode only */
78#define SCNTL1_CON 0x10 /* Connected */
79#define SCNTL1_RST 0x08 /* SCSI RST/ */
80#define SCNTL1_AESP 0x04 /* Force bad parity */
81#define SCNTL1_SND_700 0x02 /* Start SCSI send */
82#define SCNTL1_IARB_800 0x02 /* Immediate Arbitration, start
83 arbitration immediately after
84 busfree is detected */
85#define SCNTL1_RCV_700 0x01 /* Start SCSI receive */
86#define SCNTL1_SST_800 0x01 /* Start SCSI transfer */
87
88/* SCSI control 2 rw, */
89
90#define SCNTL2_REG_800 0x02
91#define SCNTL2_800_SDU 0x80 /* SCSI disconnect unexpected */
92
93/* SCSI control 3 rw */
94
95#define SCNTL3_REG_800 0x03
96#define SCNTL3_800_SCF_SHIFT 4
97#define SCNTL3_800_SCF_MASK 0x70
98#define SCNTL3_800_SCF2 0x40 /* Synchronous divisor */
99#define SCNTL3_800_SCF1 0x20 /* 0x00 = SCLK/3 */
100#define SCNTL3_800_SCF0 0x10 /* 0x10 = SCLK/1 */
101 /* 0x20 = SCLK/1.5
102 0x30 = SCLK/2
103 0x40 = SCLK/3 */
104
105#define SCNTL3_800_CCF_SHIFT 0
106#define SCNTL3_800_CCF_MASK 0x07
107#define SCNTL3_800_CCF2 0x04 /* 0x00 50.01 to 66 */
108#define SCNTL3_800_CCF1 0x02 /* 0x01 16.67 to 25 */
109#define SCNTL3_800_CCF0 0x01 /* 0x02 25.01 - 37.5
110 0x03 37.51 - 50
111 0x04 50.01 - 66 */
112
113/*
114 * SCSI destination ID rw - the appropriate bit is set for the selected
115 * target ID. This is written by the SCSI SCRIPTS processor.
116 * default = 0x00
117 */
118#define SDID_REG_700 0x02
119#define SDID_REG_800 0x06
120
121#define GP_REG_800 0x07 /* General purpose IO */
122#define GP_800_IO1 0x02
123#define GP_800_IO2 0x01
124
125/* SCSI interrupt enable rw, default = 0x00 */
126#define SIEN_REG_700 0x03
127#define SIEN0_REG_800 0x40
128#define SIEN_MA 0x80 /* Phase mismatch (ini) or ATN (tgt) */
129#define SIEN_FC 0x40 /* Function complete */
130#define SIEN_700_STO 0x20 /* Selection or reselection timeout */
131#define SIEN_800_SEL 0x20 /* Selected */
132#define SIEN_700_SEL 0x10 /* Selected or reselected */
133#define SIEN_800_RESEL 0x10 /* Reselected */
134#define SIEN_SGE 0x08 /* SCSI gross error */
135#define SIEN_UDC 0x04 /* Unexpected disconnect */
136#define SIEN_RST 0x02 /* SCSI RST/ received */
137#define SIEN_PAR 0x01 /* Parity error */
138
139/*
140 * SCSI chip ID rw
141 * NCR53c700 :
142 * When arbitrating, the highest bit is used, when reselection or selection
143 * occurs, the chip responds to all IDs for which a bit is set.
144 * default = 0x00
145 * NCR53c810 :
146 * Uses bit mapping
147 */
148#define SCID_REG 0x04
149/* Bit 7 is reserved on 800 series chips */
150#define SCID_800_RRE 0x40 /* Enable response to reselection */
151#define SCID_800_SRE 0x20 /* Enable response to selection */
152/* Bits four and three are reserved on 800 series chips */
153#define SCID_800_ENC_MASK 0x07 /* Encoded SCSI ID */
154
155/* SCSI transfer rw, default = 0x00 */
156#define SXFER_REG 0x05
157#define SXFER_DHP 0x80 /* Disable halt on parity */
158
159#define SXFER_TP2 0x40 /* Transfer period msb */
160#define SXFER_TP1 0x20
161#define SXFER_TP0 0x10 /* lsb */
162#define SXFER_TP_MASK 0x70
163/* FIXME : SXFER_TP_SHIFT == 5 is right for '8xx chips */
164#define SXFER_TP_SHIFT 5
165#define SXFER_TP_4 0x00 /* Divisors */
166#define SXFER_TP_5 0x10<<1
167#define SXFER_TP_6 0x20<<1
168#define SXFER_TP_7 0x30<<1
169#define SXFER_TP_8 0x40<<1
170#define SXFER_TP_9 0x50<<1
171#define SXFER_TP_10 0x60<<1
172#define SXFER_TP_11 0x70<<1
173
174#define SXFER_MO3 0x08 /* Max offset msb */
175#define SXFER_MO2 0x04
176#define SXFER_MO1 0x02
177#define SXFER_MO0 0x01 /* lsb */
178#define SXFER_MO_MASK 0x0f
179#define SXFER_MO_SHIFT 0
180
181/*
182 * SCSI output data latch rw
183 * The contents of this register are driven onto the SCSI bus when
184 * the Assert Data Bus bit of the SCNTL1 register is set and
185 * the CD, IO, and MSG bits of the SOCL register match the SCSI phase
186 */
187#define SODL_REG_700 0x06
188#define SODL_REG_800 0x54
189
190
191/*
192 * SCSI output control latch rw, default = 0
193 * Note that when the chip is being manually programmed as an initiator,
194 * the MSG, CD, and IO bits must be set correctly for the phase the target
195 * is driving the bus in. Otherwise no data transfer will occur due to
196 * phase mismatch.
197 */
198
199#define SOCL_REG 0x07
200#define SOCL_REQ 0x80 /* REQ */
201#define SOCL_ACK 0x40 /* ACK */
202#define SOCL_BSY 0x20 /* BSY */
203#define SOCL_SEL 0x10 /* SEL */
204#define SOCL_ATN 0x08 /* ATN */
205#define SOCL_MSG 0x04 /* MSG */
206#define SOCL_CD 0x02 /* C/D */
207#define SOCL_IO 0x01 /* I/O */
208
209/*
210 * SCSI first byte received latch ro
211 * This register contains the first byte received during a block MOVE
212 * SCSI SCRIPTS instruction, including
213 *
214 * Initiator mode Target mode
215 * Message in Command
216 * Status Message out
217 * Data in Data out
218 *
219 * It also contains the selecting or reselecting device's ID and our
220 * ID.
221 *
222 * Note that this is the register the various IF conditionals can
223 * operate on.
224 */
225#define SFBR_REG 0x08
226
227/*
228 * SCSI input data latch ro
229 * In initiator mode, data is latched into this register on the rising
230 * edge of REQ/. In target mode, data is latched on the rising edge of
231 * ACK/
232 */
233#define SIDL_REG_700 0x09
234#define SIDL_REG_800 0x50
235
236/*
237 * SCSI bus data lines ro
238 * This register reflects the instantaneous status of the SCSI data
239 * lines. Note that SCNTL0 must be set to disable parity checking,
240 * otherwise reading this register will latch new parity.
241 */
242#define SBDL_REG_700 0x0a
243#define SBDL_REG_800 0x58
244
245#define SSID_REG_800 0x0a
246#define SSID_800_VAL 0x80 /* Exactly two bits asserted at sel */
247#define SSID_800_ENCID_MASK 0x07 /* Device which performed operation */
248
249
250/*
251 * SCSI bus control lines rw,
252 * instantaneous readout of control lines
253 */
254#define SBCL_REG 0x0b
255#define SBCL_REQ 0x80 /* REQ ro */
256#define SBCL_ACK 0x40 /* ACK ro */
257#define SBCL_BSY 0x20 /* BSY ro */
258#define SBCL_SEL 0x10 /* SEL ro */
259#define SBCL_ATN 0x08 /* ATN ro */
260#define SBCL_MSG 0x04 /* MSG ro */
261#define SBCL_CD 0x02 /* C/D ro */
262#define SBCL_IO 0x01 /* I/O ro */
263#define SBCL_PHASE_CMDOUT SBCL_CD
264#define SBCL_PHASE_DATAIN SBCL_IO
265#define SBCL_PHASE_DATAOUT 0
266#define SBCL_PHASE_MSGIN (SBCL_CD|SBCL_IO|SBCL_MSG)
267#define SBCL_PHASE_MSGOUT (SBCL_CD|SBCL_MSG)
268#define SBCL_PHASE_STATIN (SBCL_CD|SBCL_IO)
269#define SBCL_PHASE_MASK (SBCL_CD|SBCL_IO|SBCL_MSG)
270/*
271 * Synchronous SCSI Clock Control bits
272 * 0 - set by DCNTL
273 * 1 - SCLK / 1.0
274 * 2 - SCLK / 1.5
275 * 3 - SCLK / 2.0
276 */
277#define SBCL_SSCF1 0x02 /* wo, -66 only */
278#define SBCL_SSCF0 0x01 /* wo, -66 only */
279#define SBCL_SSCF_MASK 0x03
280
281/*
282 * XXX note : when reading the DSTAT and STAT registers to clear interrupts,
283 * insure that 10 clocks elapse between the two
284 */
285/* DMA status ro */
286#define DSTAT_REG 0x0c
287#define DSTAT_DFE 0x80 /* DMA FIFO empty */
288#define DSTAT_800_MDPE 0x40 /* Master Data Parity Error */
289#define DSTAT_800_BF 0x20 /* Bus Fault */
290#define DSTAT_ABRT 0x10 /* Aborted - set on error */
291#define DSTAT_SSI 0x08 /* SCRIPTS single step interrupt */
292#define DSTAT_SIR 0x04 /* SCRIPTS interrupt received -
293 set when INT instruction is
294 executed */
295#define DSTAT_WTD 0x02 /* Watchdog timeout detected */
296#define DSTAT_OPC 0x01 /* Illegal instruction */
297#define DSTAT_800_IID 0x01 /* Same thing, different name */
298
299
300/* NCR53c800 moves this stuff into SIST0 */
301#define SSTAT0_REG 0x0d /* SCSI status 0 ro */
302#define SIST0_REG_800 0x42
303#define SSTAT0_MA 0x80 /* ini : phase mismatch,
304 * tgt : ATN/ asserted
305 */
306#define SSTAT0_CMP 0x40 /* function complete */
307#define SSTAT0_700_STO 0x20 /* Selection or reselection timeout */
308#define SIST0_800_SEL 0x20 /* Selected */
309#define SSTAT0_700_SEL 0x10 /* Selected or reselected */
310#define SIST0_800_RSL 0x10 /* Reselected */
311#define SSTAT0_SGE 0x08 /* SCSI gross error */
312#define SSTAT0_UDC 0x04 /* Unexpected disconnect */
313#define SSTAT0_RST 0x02 /* SCSI RST/ received */
314#define SSTAT0_PAR 0x01 /* Parity error */
315
316/* And uses SSTAT0 for what was SSTAT1 */
317
318#define SSTAT1_REG 0x0e /* SCSI status 1 ro */
319#define SSTAT1_ILF 0x80 /* SIDL full */
320#define SSTAT1_ORF 0x40 /* SODR full */
321#define SSTAT1_OLF 0x20 /* SODL full */
322#define SSTAT1_AIP 0x10 /* Arbitration in progress */
323#define SSTAT1_LOA 0x08 /* Lost arbitration */
324#define SSTAT1_WOA 0x04 /* Won arbitration */
325#define SSTAT1_RST 0x02 /* Instant readout of RST/ */
326#define SSTAT1_SDP 0x01 /* Instant readout of SDP/ */
327
328#define SSTAT2_REG 0x0f /* SCSI status 2 ro */
329#define SSTAT2_FF3 0x80 /* number of bytes in synchronous */
330#define SSTAT2_FF2 0x40 /* data FIFO */
331#define SSTAT2_FF1 0x20
332#define SSTAT2_FF0 0x10
333#define SSTAT2_FF_MASK 0xf0
334#define SSTAT2_FF_SHIFT 4
335
336/*
337 * Latched signals, latched on the leading edge of REQ/ for initiators,
338 * ACK/ for targets.
339 */
340#define SSTAT2_SDP 0x08 /* SDP */
341#define SSTAT2_MSG 0x04 /* MSG */
342#define SSTAT2_CD 0x02 /* C/D */
343#define SSTAT2_IO 0x01 /* I/O */
344#define SSTAT2_PHASE_CMDOUT SSTAT2_CD
345#define SSTAT2_PHASE_DATAIN SSTAT2_IO
346#define SSTAT2_PHASE_DATAOUT 0
347#define SSTAT2_PHASE_MSGIN (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
348#define SSTAT2_PHASE_MSGOUT (SSTAT2_CD|SSTAT2_MSG)
349#define SSTAT2_PHASE_STATIN (SSTAT2_CD|SSTAT2_IO)
350#define SSTAT2_PHASE_MASK (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
351
352
353/* NCR53c700-66 only */
354#define SCRATCHA_REG_00 0x10 /* through 0x13 Scratch A rw */
355/* NCR53c710 and higher */
356#define DSA_REG 0x10 /* DATA structure address */
357
358#define CTEST0_REG_700 0x14 /* Chip test 0 ro */
359#define CTEST0_REG_800 0x18 /* Chip test 0 rw, general purpose */
360/* 0x80 - 0x04 are reserved */
361#define CTEST0_700_RTRG 0x02 /* Real target mode */
362#define CTEST0_700_DDIR 0x01 /* Data direction, 1 =
363 * SCSI bus to host, 0 =
364 * host to SCSI.
365 */
366
367#define CTEST1_REG_700 0x15 /* Chip test 1 ro */
368#define CTEST1_REG_800 0x19 /* Chip test 1 ro */
369#define CTEST1_FMT3 0x80 /* Identify which byte lanes are empty */
370#define CTEST1_FMT2 0x40 /* in the DMA FIFO */
371#define CTEST1_FMT1 0x20
372#define CTEST1_FMT0 0x10
373
374#define CTEST1_FFL3 0x08 /* Identify which bytes lanes are full */
375#define CTEST1_FFL2 0x04 /* in the DMA FIFO */
376#define CTEST1_FFL1 0x02
377#define CTEST1_FFL0 0x01
378
379#define CTEST2_REG_700 0x16 /* Chip test 2 ro */
380#define CTEST2_REG_800 0x1a /* Chip test 2 ro */
381
382#define CTEST2_800_DDIR 0x80 /* 1 = SCSI->host */
383#define CTEST2_800_SIGP 0x40 /* A copy of SIGP in ISTAT.
384 Reading this register clears */
385#define CTEST2_800_CIO 0x20 /* Configured as IO */.
386#define CTEST2_800_CM 0x10 /* Configured as memory */
387
388/* 0x80 - 0x40 are reserved on 700 series chips */
389#define CTEST2_700_SOFF 0x20 /* SCSI Offset Compare,
390 * As an initiator, this bit is
391 * one when the synchronous offset
392 * is zero, as a target this bit
393 * is one when the synchronous
394 * offset is at the maximum
395 * defined in SXFER
396 */
397#define CTEST2_700_SFP 0x10 /* SCSI FIFO parity bit,
398 * reading CTEST3 unloads a byte
399 * from the FIFO and sets this
400 */
401#define CTEST2_700_DFP 0x08 /* DMA FIFO parity bit,
402 * reading CTEST6 unloads a byte
403 * from the FIFO and sets this
404 */
405#define CTEST2_TEOP 0x04 /* SCSI true end of process,
406 * indicates a totally finished
407 * transfer
408 */
409#define CTEST2_DREQ 0x02 /* Data request signal */
410/* 0x01 is reserved on 700 series chips */
411#define CTEST2_800_DACK 0x01
412
413/*
414 * Chip test 3 ro
415 * Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
416 * check SSTAT2 FIFO full bits to determine size. Note that a GROSS
417 * error results if a read is attempted on this register. Also note
418 * that 16 and 32 bit reads of this register will cause corruption.
419 */
420#define CTEST3_REG_700 0x17
421/* Chip test 3 rw */
422#define CTEST3_REG_800 0x1b
423#define CTEST3_800_V3 0x80 /* Chip revision */
424#define CTEST3_800_V2 0x40
425#define CTEST3_800_V1 0x20
426#define CTEST3_800_V0 0x10
427#define CTEST3_800_FLF 0x08 /* Flush DMA FIFO */
428#define CTEST3_800_CLF 0x04 /* Clear DMA FIFO */
429#define CTEST3_800_FM 0x02 /* Fetch mode pin */
430/* bit 0 is reserved on 800 series chips */
431
432#define CTEST4_REG_700 0x18 /* Chip test 4 rw */
433#define CTEST4_REG_800 0x21 /* Chip test 4 rw */
434/* 0x80 is reserved on 700 series chips */
435#define CTEST4_800_BDIS 0x80 /* Burst mode disable */
436#define CTEST4_ZMOD 0x40 /* High impedance mode */
437#define CTEST4_SZM 0x20 /* SCSI bus high impedance */
438#define CTEST4_700_SLBE 0x10 /* SCSI loopback enabled */
439#define CTEST4_800_SRTM 0x10 /* Shadow Register Test Mode */
440#define CTEST4_700_SFWR 0x08 /* SCSI FIFO write enable,
441 * redirects writes from SODL
442 * to the SCSI FIFO.
443 */
444#define CTEST4_800_MPEE 0x08 /* Enable parity checking
445 during master cycles on PCI
446 bus */
447
448/*
449 * These bits send the contents of the CTEST6 register to the appropriate
450 * byte lane of the 32 bit DMA FIFO. Normal operation is zero, otherwise
451 * the high bit means the low two bits select the byte lane.
452 */
453#define CTEST4_FBL2 0x04
454#define CTEST4_FBL1 0x02
455#define CTEST4_FBL0 0x01
456#define CTEST4_FBL_MASK 0x07
457#define CTEST4_FBL_0 0x04 /* Select DMA FIFO byte lane 0 */
458#define CTEST4_FBL_1 0x05 /* Select DMA FIFO byte lane 1 */
459#define CTEST4_FBL_2 0x06 /* Select DMA FIFO byte lane 2 */
460#define CTEST4_FBL_3 0x07 /* Select DMA FIFO byte lane 3 */
461#define CTEST4_800_SAVE (CTEST4_800_BDIS)
462
463
464#define CTEST5_REG_700 0x19 /* Chip test 5 rw */
465#define CTEST5_REG_800 0x22 /* Chip test 5 rw */
466/*
467 * Clock Address Incrementor. When set, it increments the
468 * DNAD register to the next bus size boundary. It automatically
469 * resets itself when the operation is complete.
470 */
471#define CTEST5_ADCK 0x80
472/*
473 * Clock Byte Counter. When set, it decrements the DBC register to
474 * the next bus size boundary.
475 */
476#define CTEST5_BBCK 0x40
477/*
478 * Reset SCSI Offset. Setting this bit to 1 clears the current offset
479 * pointer in the SCSI synchronous offset counter (SSTAT). This bit
480 * is set to 1 if a SCSI Gross Error Condition occurs. The offset should
481 * be cleared when a synchronous transfer fails. When written, it is
482 * automatically cleared after the SCSI synchronous offset counter is
483 * reset.
484 */
485/* Bit 5 is reserved on 800 series chips */
486#define CTEST5_700_ROFF 0x20
487/*
488 * Master Control for Set or Reset pulses. When 1, causes the low
489 * four bits of register to set when set, 0 causes the low bits to
490 * clear when set.
491 */
492#define CTEST5_MASR 0x10
493#define CTEST5_DDIR 0x08 /* DMA direction */
494/*
495 * Bits 2-0 are reserved on 800 series chips
496 */
497#define CTEST5_700_EOP 0x04 /* End of process */
498#define CTEST5_700_DREQ 0x02 /* Data request */
499#define CTEST5_700_DACK 0x01 /* Data acknowledge */
500
501/*
502 * Chip test 6 rw - writing to this register writes to the byte
503 * lane in the DMA FIFO as determined by the FBL bits in the CTEST4
504 * register.
505 */
506#define CTEST6_REG_700 0x1a
507#define CTEST6_REG_800 0x23
508
509#define CTEST7_REG 0x1b /* Chip test 7 rw */
510/* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */
511#define CTEST7_10_CDIS 0x80 /* Cache burst disable */
512#define CTEST7_10_SC1 0x40 /* Snoop control bits */
513#define CTEST7_10_SC0 0x20
514#define CTEST7_10_SC_MASK 0x60
515/* 0x20 is reserved on the NCR53c700 */
516#define CTEST7_0060_FM 0x20 /* Fetch mode */
517#define CTEST7_STD 0x10 /* Selection timeout disable */
518#define CTEST7_DFP 0x08 /* DMA FIFO parity bit for CTEST6 */
519#define CTEST7_EVP 0x04 /* 1 = host bus even parity, 0 = odd */
520#define CTEST7_10_TT1 0x02 /* Transfer type */
521#define CTEST7_00_DC 0x02 /* Set to drive DC low during instruction
522 fetch */
523#define CTEST7_DIFF 0x01 /* Differential mode */
524
525#define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
526
527
528#define TEMP_REG 0x1c /* through 0x1f Temporary stack rw */
529
530#define DFIFO_REG 0x20 /* DMA FIFO rw */
531/*
532 * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
533 * moved into the CTEST8 register.
534 */
535#define DFIFO_00_FLF 0x80 /* Flush DMA FIFO to memory */
536#define DFIFO_00_CLF 0x40 /* Clear DMA and SCSI FIFOs */
537#define DFIFO_BO6 0x40
538#define DFIFO_BO5 0x20
539#define DFIFO_BO4 0x10
540#define DFIFO_BO3 0x08
541#define DFIFO_BO2 0x04
542#define DFIFO_BO1 0x02
543#define DFIFO_BO0 0x01
544#define DFIFO_10_BO_MASK 0x7f /* 7 bit counter */
545#define DFIFO_00_BO_MASK 0x3f /* 6 bit counter */
546
547/*
548 * Interrupt status rw
549 * Note that this is the only register which can be read while SCSI
550 * SCRIPTS are being executed.
551 */
552#define ISTAT_REG_700 0x21
553#define ISTAT_REG_800 0x14
554#define ISTAT_ABRT 0x80 /* Software abort, write
555 *1 to abort, wait for interrupt. */
556/* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */
557#define ISTAT_10_SRST 0x40 /* software reset */
558#define ISTAT_10_SIGP 0x20 /* signal script */
559/* 0x10 is reserved on NCR53c700 series chips */
560#define ISTAT_800_SEM 0x10 /* semaphore */
561#define ISTAT_CON 0x08 /* 1 when connected */
562#define ISTAT_800_INTF 0x04 /* Interrupt on the fly */
563#define ISTAT_700_PRE 0x04 /* Pointer register empty.
564 * Set to 1 when DSPS and DSP
565 * registers are empty in pipeline
566 * mode, always set otherwise.
567 */
568#define ISTAT_SIP 0x02 /* SCSI interrupt pending from
569 * SCSI portion of SIOP see
570 * SSTAT0
571 */
572#define ISTAT_DIP 0x01 /* DMA interrupt pending
573 * see DSTAT
574 */
575
576/* NCR53c700-66 and NCR53c710 only */
577#define CTEST8_REG 0x22 /* Chip test 8 rw */
578#define CTEST8_0066_EAS 0x80 /* Enable alternate SCSI clock,
579 * ie read from SCLK/ rather than CLK/
580 */
581#define CTEST8_0066_EFM 0x40 /* Enable fetch and master outputs */
582#define CTEST8_0066_GRP 0x20 /* Generate Receive Parity for
583 * pass through. This insures that
584 * bad parity won't reach the host
585 * bus.
586 */
587#define CTEST8_0066_TE 0x10 /* TolerANT enable. Enable
588 * active negation, should only
589 * be used for slow SCSI
590 * non-differential.
591 */
592#define CTEST8_0066_HSC 0x08 /* Halt SCSI clock */
593#define CTEST8_0066_SRA 0x04 /* Shorten REQ/ACK filtering,
594 * must be set for fast SCSI-II
595 * speeds.
596 */
597#define CTEST8_0066_DAS 0x02 /* Disable automatic target/initiator
598 * switching.
599 */
600#define CTEST8_0066_LDE 0x01 /* Last disconnect enable.
601 * The status of pending
602 * disconnect is maintained by
603 * the core, eliminating
604 * the possibility of missing a
605 * selection or reselection
606 * while waiting to fetch a
607 * WAIT DISCONNECT opcode.
608 */
609
610#define CTEST8_10_V3 0x80 /* Chip revision */
611#define CTEST8_10_V2 0x40
612#define CTEST8_10_V1 0x20
613#define CTEST8_10_V0 0x10
614#define CTEST8_10_V_MASK 0xf0
615#define CTEST8_10_FLF 0x08 /* Flush FIFOs */
616#define CTEST8_10_CLF 0x04 /* Clear FIFOs */
617#define CTEST8_10_FM 0x02 /* Fetch pin mode */
618#define CTEST8_10_SM 0x01 /* Snoop pin mode */
619
620
621/*
622 * The CTEST9 register may be used to differentiate between a
623 * NCR53c700 and a NCR53c710.
624 *
625 * Write 0xff to this register.
626 * Read it.
627 * If the contents are 0xff, it is a NCR53c700
628 * If the contents are 0x00, it is a NCR53c700-66 first revision
629 * If the contents are some other value, it is some other NCR53c700-66
630 */
631#define CTEST9_REG_00 0x23 /* Chip test 9 ro */
632#define LCRC_REG_10 0x23
633
634/*
635 * 0x24 through 0x27 are the DMA byte counter register. Instructions
636 * write their high 8 bits into the DCMD register, the low 24 bits into
637 * the DBC register.
638 *
639 * Function is dependent on the command type being executed.
640 */
641
642
643#define DBC_REG 0x24
644/*
645 * For Block Move Instructions, DBC is a 24 bit quantity representing
646 * the number of bytes to transfer.
647 * For Transfer Control Instructions, DBC is bit fielded as follows :
648 */
649/* Bits 20 - 23 should be clear */
650#define DBC_TCI_TRUE (1 << 19) /* Jump when true */
651#define DBC_TCI_COMPARE_DATA (1 << 18) /* Compare data */
652#define DBC_TCI_COMPARE_PHASE (1 << 17) /* Compare phase with DCMD field */
653#define DBC_TCI_WAIT_FOR_VALID (1 << 16) /* Wait for REQ */
654/* Bits 8 - 15 are reserved on some implementations ? */
655#define DBC_TCI_MASK_MASK 0xff00 /* Mask for data compare */
656#define DBC_TCI_MASK_SHIFT 8
657#define DBC_TCI_DATA_MASK 0xff /* Data to be compared */
658#define DBC_TCI_DATA_SHIFT 0
659
660#define DBC_RWRI_IMMEDIATE_MASK 0xff00 /* Immediate data */
661#define DBC_RWRI_IMMEDIATE_SHIFT 8 /* Amount to shift */
662#define DBC_RWRI_ADDRESS_MASK 0x3f0000 /* Register address */
663#define DBC_RWRI_ADDRESS_SHIFT 16
664
665
666/*
667 * DMA command r/w
668 */
669#define DCMD_REG 0x27
670#define DCMD_TYPE_MASK 0xc0 /* Masks off type */
671#define DCMD_TYPE_BMI 0x00 /* Indicates a Block Move instruction */
672#define DCMD_BMI_IO 0x01 /* I/O, CD, and MSG bits selecting */
673#define DCMD_BMI_CD 0x02 /* the phase for the block MOVE */
674#define DCMD_BMI_MSG 0x04 /* instruction */
675
676#define DCMD_BMI_OP_MASK 0x18 /* mask for opcode */
677#define DCMD_BMI_OP_MOVE_T 0x00 /* MOVE */
678#define DCMD_BMI_OP_MOVE_I 0x08 /* MOVE Initiator */
679
680#define DCMD_BMI_INDIRECT 0x20 /* Indirect addressing */
681
682#define DCMD_TYPE_TCI 0x80 /* Indicates a Transfer Control
683 instruction */
684#define DCMD_TCI_IO 0x01 /* I/O, CD, and MSG bits selecting */
685#define DCMD_TCI_CD 0x02 /* the phase for the block MOVE */
686#define DCMD_TCI_MSG 0x04 /* instruction */
687#define DCMD_TCI_OP_MASK 0x38 /* mask for opcode */
688#define DCMD_TCI_OP_JUMP 0x00 /* JUMP */
689#define DCMD_TCI_OP_CALL 0x08 /* CALL */
690#define DCMD_TCI_OP_RETURN 0x10 /* RETURN */
691#define DCMD_TCI_OP_INT 0x18 /* INT */
692
693#define DCMD_TYPE_RWRI 0x40 /* Indicates I/O or register Read/Write
694 instruction */
695#define DCMD_RWRI_OPC_MASK 0x38 /* Opcode mask */
696#define DCMD_RWRI_OPC_WRITE 0x28 /* Write SFBR to register */
697#define DCMD_RWRI_OPC_READ 0x30 /* Read register to SFBR */
698#define DCMD_RWRI_OPC_MODIFY 0x38 /* Modify in place */
699
700#define DCMD_RWRI_OP_MASK 0x07
701#define DCMD_RWRI_OP_MOVE 0x00
702#define DCMD_RWRI_OP_SHL 0x01
703#define DCMD_RWRI_OP_OR 0x02
704#define DCMD_RWRI_OP_XOR 0x03
705#define DCMD_RWRI_OP_AND 0x04
706#define DCMD_RWRI_OP_SHR 0x05
707#define DCMD_RWRI_OP_ADD 0x06
708#define DCMD_RWRI_OP_ADDC 0x07
709
710#define DCMD_TYPE_MMI 0xc0 /* Indicates a Memory Move instruction
711 (three words) */
712
713
714#define DNAD_REG 0x28 /* through 0x2b DMA next address for
715 data */
716#define DSP_REG 0x2c /* through 0x2f DMA SCRIPTS pointer rw */
717#define DSPS_REG 0x30 /* through 0x33 DMA SCRIPTS pointer
718 save rw */
719#define DMODE_REG_00 0x34 /* DMA mode rw */
720#define DMODE_00_BL1 0x80 /* Burst length bits */
721#define DMODE_00_BL0 0x40
722#define DMODE_BL_MASK 0xc0
723/* Burst lengths (800) */
724#define DMODE_BL_2 0x00 /* 2 transfer */
725#define DMODE_BL_4 0x40 /* 4 transfers */
726#define DMODE_BL_8 0x80 /* 8 transfers */
727#define DMODE_BL_16 0xc0 /* 16 transfers */
728
729#define DMODE_10_BL_1 0x00 /* 1 transfer */
730#define DMODE_10_BL_2 0x40 /* 2 transfers */
731#define DMODE_10_BL_4 0x80 /* 4 transfers */
732#define DMODE_10_BL_8 0xc0 /* 8 transfers */
733#define DMODE_10_FC2 0x20 /* Driven to FC2 pin */
734#define DMODE_10_FC1 0x10 /* Driven to FC1 pin */
735#define DMODE_710_PD 0x08 /* Program/data on FC0 pin */
736#define DMODE_710_UO 0x02 /* User prog. output */
737
738#define DMODE_700_BW16 0x20 /* Host buswidth = 16 */
739#define DMODE_700_286 0x10 /* 286 mode */
740#define DMODE_700_IOM 0x08 /* Transfer to IO port */
741#define DMODE_700_FAM 0x04 /* Fixed address mode */
742#define DMODE_700_PIPE 0x02 /* Pipeline mode disables
743 * automatic fetch / exec
744 */
745#define DMODE_MAN 0x01 /* Manual start mode,
746 * requires a 1 to be written
747 * to the start DMA bit in the DCNTL
748 * register to run scripts
749 */
750
751#define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )
752
753/* NCR53c800 series only */
754#define SCRATCHA_REG_800 0x34 /* through 0x37 Scratch A rw */
755/* NCR53c710 only */
756#define SCRATCHB_REG_10 0x34 /* through 0x37 scratch B rw */
757
758#define DMODE_REG_10 0x38 /* DMA mode rw, NCR53c710 and newer */
759#define DMODE_800_SIOM 0x20 /* Source IO = 1 */
760#define DMODE_800_DIOM 0x10 /* Destination IO = 1 */
761#define DMODE_800_ERL 0x08 /* Enable Read Line */
762
763/* 35-38 are reserved on 700 and 700-66 series chips */
764#define DIEN_REG 0x39 /* DMA interrupt enable rw */
765/* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
766#define DIEN_800_MDPE 0x40 /* Master data parity error */
767#define DIEN_800_BF 0x20 /* BUS fault */
768#define DIEN_700_BF 0x20 /* BUS fault */
769#define DIEN_ABRT 0x10 /* Enable aborted interrupt */
770#define DIEN_SSI 0x08 /* Enable single step interrupt */
771#define DIEN_SIR 0x04 /* Enable SCRIPTS INT command
772 * interrupt
773 */
774/* 0x02 is reserved on 800 series chips */
775#define DIEN_700_WTD 0x02 /* Enable watchdog timeout interrupt */
776#define DIEN_700_OPC 0x01 /* Enable illegal instruction
777 * interrupt
778 */
779#define DIEN_800_IID 0x01 /* Same meaning, different name */
780
781/*
782 * DMA watchdog timer rw
783 * set in 16 CLK input periods.
784 */
785#define DWT_REG 0x3a
786
787/* DMA control rw */
788#define DCNTL_REG 0x3b
789#define DCNTL_700_CF1 0x80 /* Clock divisor bits */
790#define DCNTL_700_CF0 0x40
791#define DCNTL_700_CF_MASK 0xc0
792/* Clock divisors Divisor SCLK range (MHZ) */
793#define DCNTL_700_CF_2 0x00 /* 2.0 37.51-50.00 */
794#define DCNTL_700_CF_1_5 0x40 /* 1.5 25.01-37.50 */
795#define DCNTL_700_CF_1 0x80 /* 1.0 16.67-25.00 */
796#define DCNTL_700_CF_3 0xc0 /* 3.0 50.01-66.67 (53c700-66) */
797
798#define DCNTL_700_S16 0x20 /* Load scripts 16 bits at a time */
799#define DCNTL_SSM 0x10 /* Single step mode */
800#define DCNTL_700_LLM 0x08 /* Low level mode, can only be set
801 * after selection */
802#define DCNTL_800_IRQM 0x08 /* Totem pole IRQ pin */
803#define DCNTL_STD 0x04 /* Start DMA / SCRIPTS */
804/* 0x02 is reserved */
805#define DCNTL_00_RST 0x01 /* Software reset, resets everything
806 * but 286 mode bit in DMODE. On the
807 * NCR53c710, this bit moved to CTEST8
808 */
809#define DCNTL_10_COM 0x01 /* 700 software compatibility mode */
810#define DCNTL_10_EA 0x20 /* Enable Ack - needed for MVME16x */
811
812#define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)
813
814
815/* NCR53c700-66 only */
816#define SCRATCHB_REG_00 0x3c /* through 0x3f scratch b rw */
817#define SCRATCHB_REG_800 0x5c /* through 0x5f scratch b rw */
818/* NCR53c710 only */
819#define ADDER_REG_10 0x3c /* Adder, NCR53c710 only */
820
821#define SIEN1_REG_800 0x41
822#define SIEN1_800_STO 0x04 /* selection/reselection timeout */
823#define SIEN1_800_GEN 0x02 /* general purpose timer */
824#define SIEN1_800_HTH 0x01 /* handshake to handshake */
825
826#define SIST1_REG_800 0x43
827#define SIST1_800_STO 0x04 /* selection/reselection timeout */
828#define SIST1_800_GEN 0x02 /* general purpose timer */
829#define SIST1_800_HTH 0x01 /* handshake to handshake */
830
831#define SLPAR_REG_800 0x44 /* Parity */
832
833#define MACNTL_REG_800 0x46 /* Memory access control */
834#define MACNTL_800_TYP3 0x80
835#define MACNTL_800_TYP2 0x40
836#define MACNTL_800_TYP1 0x20
837#define MACNTL_800_TYP0 0x10
838#define MACNTL_800_DWR 0x08
839#define MACNTL_800_DRD 0x04
840#define MACNTL_800_PSCPT 0x02
841#define MACNTL_800_SCPTS 0x01
842
843#define GPCNTL_REG_800 0x47 /* General Purpose Pin Control */
844
845/* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
846#define STIME0_REG_800 0x48 /* SCSI Timer Register 0 */
847#define STIME0_800_HTH_MASK 0xf0 /* Handshake to Handshake timeout */
848#define STIME0_800_HTH_SHIFT 4
849#define STIME0_800_SEL_MASK 0x0f /* Selection timeout */
850#define STIME0_800_SEL_SHIFT 0
851
852#define STIME1_REG_800 0x49
853#define STIME1_800_GEN_MASK 0x0f /* General purpose timer */
854
855#define RESPID_REG_800 0x4a /* Response ID, bit fielded. 8
856 bits on narrow chips, 16 on WIDE */
857
858#define STEST0_REG_800 0x4c
859#define STEST0_800_SLT 0x08 /* Selection response logic test */
860#define STEST0_800_ART 0x04 /* Arbitration priority encoder test */
861#define STEST0_800_SOZ 0x02 /* Synchronous offset zero */
862#define STEST0_800_SOM 0x01 /* Synchronous offset maximum */
863
864#define STEST1_REG_800 0x4d
865#define STEST1_800_SCLK 0x80 /* Disable SCSI clock */
866
867#define STEST2_REG_800 0x4e
868#define STEST2_800_SCE 0x80 /* Enable SOCL/SODL */
869#define STEST2_800_ROF 0x40 /* Reset SCSI sync offset */
870#define STEST2_800_SLB 0x10 /* Enable SCSI loopback mode */
871#define STEST2_800_SZM 0x08 /* SCSI high impedance mode */
872#define STEST2_800_EXT 0x02 /* Extend REQ/ACK filter 30 to 60ns */
873#define STEST2_800_LOW 0x01 /* SCSI low level mode */
874
875#define STEST3_REG_800 0x4f
876#define STEST3_800_TE 0x80 /* Enable active negation */
877#define STEST3_800_STR 0x40 /* SCSI FIFO test read */
878#define STEST3_800_HSC 0x20 /* Halt SCSI clock */
879#define STEST3_800_DSI 0x10 /* Disable single initiator response */
880#define STEST3_800_TTM 0x04 /* Time test mode */
881#define STEST3_800_CSF 0x02 /* Clear SCSI FIFO */
882#define STEST3_800_STW 0x01 /* SCSI FIFO test write */
883
884#define OPTION_PARITY 0x1 /* Enable parity checking */
885#define OPTION_TAGGED_QUEUE 0x2 /* Enable SCSI-II tagged queuing */
886#define OPTION_700 0x8 /* Always run NCR53c700 scripts */
887#define OPTION_INTFLY 0x10 /* Use INTFLY interrupts */
888#define OPTION_DEBUG_INTR 0x20 /* Debug interrupts */
889#define OPTION_DEBUG_INIT_ONLY 0x40 /* Run initialization code and
890 simple test code, return
891 DID_NO_CONNECT if any SCSI
892 commands are attempted. */
893#define OPTION_DEBUG_READ_ONLY 0x80 /* Return DID_ERROR if any
894 SCSI write is attempted */
895#define OPTION_DEBUG_TRACE 0x100 /* Animated trace mode, print
896 each address and instruction
897 executed to debug buffer. */
898#define OPTION_DEBUG_SINGLE 0x200 /* stop after executing one
899 instruction */
900#define OPTION_SYNCHRONOUS 0x400 /* Enable sync SCSI. */
901#define OPTION_MEMORY_MAPPED 0x800 /* NCR registers have valid
902 memory mapping */
903#define OPTION_IO_MAPPED 0x1000 /* NCR registers have valid
904 I/O mapping */
905#define OPTION_DEBUG_PROBE_ONLY 0x2000 /* Probe only, don't even init */
906#define OPTION_DEBUG_TESTS_ONLY 0x4000 /* Probe, init, run selected tests */
907#define OPTION_DEBUG_TEST0 0x08000 /* Run test 0 */
908#define OPTION_DEBUG_TEST1 0x10000 /* Run test 1 */
909#define OPTION_DEBUG_TEST2 0x20000 /* Run test 2 */
910#define OPTION_DEBUG_DUMP 0x40000 /* Dump commands */
911#define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */
912#define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */
913#define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */
914#define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */
915#define OPTION_DEBUG_DSA 0x800000
916#define OPTION_DEBUG_CORRUPTION 0x1000000 /* Detect script corruption */
917#define OPTION_DEBUG_SDTR 0x2000000 /* Debug SDTR problem */
918#define OPTION_DEBUG_MISMATCH 0x4000000 /* Debug phase mismatches */
919#define OPTION_DISCONNECT 0x8000000 /* Allow disconnect */
920#define OPTION_DEBUG_DISCONNECT 0x10000000
921#define OPTION_ALWAYS_SYNCHRONOUS 0x20000000 /* Negotiate sync. transfers
922 on power up */
923#define OPTION_DEBUG_QUEUES 0x80000000
924#define OPTION_DEBUG_ALLOCATION 0x100000000LL
925#define OPTION_DEBUG_SYNCHRONOUS 0x200000000LL /* Sanity check SXFER and
926 SCNTL3 registers */
927#define OPTION_NO_ASYNC 0x400000000LL /* Don't automagically send
928 SDTR for async transfers when
929 we haven't been told to do
930 a synchronous transfer. */
931#define OPTION_NO_PRINT_RACE 0x800000000LL /* Don't print message when
932 the reselect/WAIT DISCONNECT
933 race condition hits */
934#if !defined(PERM_OPTIONS)
935#define PERM_OPTIONS 0
936#endif
937
938/*
939 * Some data which is accessed by the NCR chip must be 4-byte aligned.
940 * For some hosts the default is less than that (eg. 68K uses 2-byte).
941 * Alignment has only been forced where it is important; also if one
942 * 32 bit structure field is aligned then it is assumed that following
943 * 32 bit fields are also aligned. Take care when adding fields
944 * which are other than 32 bit.
945 */
946
947struct NCR53c7x0_synchronous {
948 u32 select_indirect /* Value used for indirect selection */
949 __attribute__ ((aligned (4)));
950 u32 sscf_710; /* Used to set SSCF bits for 710 */
951 u32 script[8]; /* Size ?? Script used when target is
952 reselected */
953 unsigned char synchronous_want[5]; /* Per target desired SDTR */
954/*
955 * Set_synchronous programs these, select_indirect and current settings after
956 * int_debug_should show a match.
957 */
958 unsigned char sxfer_sanity, scntl3_sanity;
959};
960
961#define CMD_FLAG_SDTR 1 /* Initiating synchronous
962 transfer negotiation */
963#define CMD_FLAG_WDTR 2 /* Initiating wide transfer
964 negotiation */
965#define CMD_FLAG_DID_SDTR 4 /* did SDTR */
966#define CMD_FLAG_DID_WDTR 8 /* did WDTR */
967
968struct NCR53c7x0_table_indirect {
969 u32 count;
970 void *address;
971};
972
973enum ncr_event {
974 EVENT_NONE = 0,
975/*
976 * Order is IMPORTANT, since these must correspond to the event interrupts
977 * in 53c7,8xx.scr
978 */
979
980 EVENT_ISSUE_QUEUE = 0x5000000, /* 0 Command was added to issue queue */
981 EVENT_START_QUEUE, /* 1 Command moved to start queue */
982 EVENT_SELECT, /* 2 Command completed selection */
983 EVENT_DISCONNECT, /* 3 Command disconnected */
984 EVENT_RESELECT, /* 4 Command reselected */
985 EVENT_COMPLETE, /* 5 Command completed */
986 EVENT_IDLE, /* 6 */
987 EVENT_SELECT_FAILED, /* 7 */
988 EVENT_BEFORE_SELECT, /* 8 */
989 EVENT_RESELECT_FAILED /* 9 */
990};
991
992struct NCR53c7x0_event {
993 enum ncr_event event; /* What type of event */
994 unsigned char target;
995 unsigned char lun;
996 struct timeval time;
997 u32 *dsa; /* What's in the DSA register now (virt) */
998/*
999 * A few things from that SCSI pid so we know what happened after
1000 * the Scsi_Cmnd structure in question may have disappeared.
1001 */
1002 unsigned long pid; /* The SCSI PID which caused this
1003 event */
1004 unsigned char cmnd[12];
1005};
1006
1007/*
1008 * Things in the NCR53c7x0_cmd structure are split into two parts :
1009 *
1010 * 1. A fixed portion, for things which are not accessed directly by static NCR
1011 * code (ie, are referenced only by the Linux side of the driver,
1012 * or only by dynamically generated code).
1013 *
1014 * 2. The DSA portion, for things which are accessed directly by static NCR
1015 * code.
1016 *
1017 * This is a little ugly, but it
1018 * 1. Avoids conflicts between the NCR code's picture of the structure, and
1019 * Linux code's idea of what it looks like.
1020 *
1021 * 2. Minimizes the pain in the Linux side of the code needed
1022 * to calculate real dsa locations for things, etc.
1023 *
1024 */
1025
1026struct NCR53c7x0_cmd {
1027 void *real; /* Real, unaligned address for
1028 free function */
1029 void (* free)(void *, int); /* Command to deallocate; NULL
1030 for structures allocated with
1031 scsi_register, etc. */
1032 Scsi_Cmnd *cmd; /* Associated Scsi_Cmnd
1033 structure, Scsi_Cmnd points
1034 at NCR53c7x0_cmd using
1035 host_scribble structure */
1036
1037 int size; /* scsi_malloc'd size of this
1038 structure */
1039
1040 int flags; /* CMD_* flags */
1041
1042 unsigned char cmnd[12]; /* CDB, copied from Scsi_Cmnd */
1043 int result; /* Copy to Scsi_Cmnd when done */
1044
1045 struct { /* Private non-cached bounce buffer */
1046 unsigned char buf[256];
1047 u32 addr;
1048 u32 len;
1049 } bounce;
1050
1051/*
1052 * SDTR and WIDE messages are an either/or affair
1053 * in this message, since we will go into message out and send
1054 * _the whole mess_ without dropping out of message out to
1055 * let the target go into message in after sending the first
1056 * message.
1057 */
1058
1059 unsigned char select[11]; /* Select message, includes
1060 IDENTIFY
1061 (optional) QUEUE TAG
1062 (optional) SDTR or WDTR
1063 */
1064
1065
1066 volatile struct NCR53c7x0_cmd *next; /* Linux maintained lists (free,
1067 running, eventually finished */
1068
1069
1070 u32 *data_transfer_start; /* Start of data transfer routines */
1071 u32 *data_transfer_end; /* Address after end of data transfer o
1072 routines */
1073/*
1074 * The following three fields were moved from the DSA proper to here
1075 * since only dynamically generated NCR code refers to them, meaning
1076 * we don't need dsa_* absolutes, and it is simpler to let the
1077 * host code refer to them directly.
1078 */
1079
1080/*
1081 * HARD CODED : residual and saved_residual need to agree with the sizes
1082 * used in NCR53c7,8xx.scr.
1083 *
1084 * FIXME: we want to consider the case where we have odd-length
1085 * scatter/gather buffers and a WIDE transfer, in which case
1086 * we'll need to use the CHAIN MOVE instruction. Ick.
1087 */
1088 u32 residual[6] __attribute__ ((aligned (4)));
1089 /* Residual data transfer which
1090 allows pointer code to work
1091 right.
1092
1093 [0-1] : Conditional call to
1094 appropriate other transfer
1095 routine.
1096 [2-3] : Residual block transfer
1097 instruction.
1098 [4-5] : Jump to instruction
1099 after splice.
1100 */
1101 u32 saved_residual[6]; /* Copy of old residual, so we
1102 can get another partial
1103 transfer and still recover
1104 */
1105
1106 u32 saved_data_pointer; /* Saved data pointer */
1107
1108 u32 dsa_next_addr; /* _Address_ of dsa_next field
1109 in this dsa for RISCy
1110 style constant. */
1111
1112 u32 dsa_addr; /* Address of dsa; RISCy style
1113 constant */
1114
1115 u32 dsa[0]; /* Variable length (depending
1116 on host type, number of scatter /
1117 gather buffers, etc). */
1118};
1119
1120struct NCR53c7x0_break {
1121 u32 *address, old_instruction[2];
1122 struct NCR53c7x0_break *next;
1123 unsigned char old_size; /* Size of old instruction */
1124};
1125
1126/* Indicates that the NCR is not executing code */
1127#define STATE_HALTED 0
1128/*
1129 * Indicates that the NCR is executing the wait for select / reselect
1130 * script. Only used when running NCR53c700 compatible scripts, only
1131 * state during which an ABORT is _not_ considered an error condition.
1132 */
1133#define STATE_WAITING 1
1134/* Indicates that the NCR is executing other code. */
1135#define STATE_RUNNING 2
1136/*
1137 * Indicates that the NCR was being aborted.
1138 */
1139#define STATE_ABORTING 3
1140/* Indicates that the NCR was successfully aborted. */
1141#define STATE_ABORTED 4
1142/* Indicates that the NCR has been disabled due to a fatal error */
1143#define STATE_DISABLED 5
1144
1145/*
1146 * Where knowledge of SCSI SCRIPT(tm) specified values are needed
1147 * in an interrupt handler, an interrupt handler exists for each
1148 * different SCSI script so we don't have name space problems.
1149 *
1150 * Return values of these handlers are as follows :
1151 */
1152#define SPECIFIC_INT_NOTHING 0 /* don't even restart */
1153#define SPECIFIC_INT_RESTART 1 /* restart at the next instruction */
1154#define SPECIFIC_INT_ABORT 2 /* recoverable error, abort cmd */
1155#define SPECIFIC_INT_PANIC 3 /* unrecoverable error, panic */
1156#define SPECIFIC_INT_DONE 4 /* normal command completion */
1157#define SPECIFIC_INT_BREAK 5 /* break point encountered */
1158
1159struct NCR53c7x0_hostdata {
1160 int size; /* Size of entire Scsi_Host
1161 structure */
1162 int board; /* set to board type, useful if
1163 we have host specific things,
1164 ie, a general purpose I/O
1165 bit is being used to enable
1166 termination, etc. */
1167
1168 int chip; /* set to chip type; 700-66 is
1169 700-66, rest are last three
1170 digits of part number */
1171
1172 char valid_ids[8]; /* Valid SCSI ID's for adapter */
1173
1174 u32 *dsp; /* dsp to restart with after
1175 all stacked interrupts are
1176 handled. */
1177
1178 unsigned dsp_changed:1; /* Has dsp changed within this
1179 set of stacked interrupts ? */
1180
1181 unsigned char dstat; /* Most recent value of dstat */
1182 unsigned dstat_valid:1;
1183
1184 unsigned expecting_iid:1; /* Expect IID interrupt */
1185 unsigned expecting_sto:1; /* Expect STO interrupt */
1186
1187 /*
1188 * The code stays cleaner if we use variables with function
1189 * pointers and offsets that are unique for the different
1190 * scripts rather than having a slew of switch(hostdata->chip)
1191 * statements.
1192 *
1193 * It also means that the #defines from the SCSI SCRIPTS(tm)
1194 * don't have to be visible outside of the script-specific
1195 * instructions, preventing name space pollution.
1196 */
1197
1198 void (* init_fixup)(struct Scsi_Host *host);
1199 void (* init_save_regs)(struct Scsi_Host *host);
1200 void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd);
1201 void (* soft_reset)(struct Scsi_Host *host);
1202 int (* run_tests)(struct Scsi_Host *host);
1203
1204 /*
1205 * Called when DSTAT_SIR is set, indicating an interrupt generated
1206 * by the INT instruction, where values are unique for each SCSI
1207 * script. Should return one of the SPEC_* values.
1208 */
1209
1210 int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd);
1211
1212 int dsa_len; /* Size of DSA structure */
1213
1214 /*
1215 * Location of DSA fields for the SCSI SCRIPT corresponding to this
1216 * chip.
1217 */
1218
1219 s32 dsa_start;
1220 s32 dsa_end;
1221 s32 dsa_next;
1222 s32 dsa_prev;
1223 s32 dsa_cmnd;
1224 s32 dsa_select;
1225 s32 dsa_msgout;
1226 s32 dsa_cmdout;
1227 s32 dsa_dataout;
1228 s32 dsa_datain;
1229 s32 dsa_msgin;
1230 s32 dsa_msgout_other;
1231 s32 dsa_write_sync;
1232 s32 dsa_write_resume;
1233 s32 dsa_check_reselect;
1234 s32 dsa_status;
1235 s32 dsa_saved_pointer;
1236 s32 dsa_jump_dest;
1237
1238 /*
1239 * Important entry points that generic fixup code needs
1240 * to know about, fixed up.
1241 */
1242
1243 s32 E_accept_message;
1244 s32 E_command_complete;
1245 s32 E_data_transfer;
1246 s32 E_dsa_code_template;
1247 s32 E_dsa_code_template_end;
1248 s32 E_end_data_transfer;
1249 s32 E_msg_in;
1250 s32 E_initiator_abort;
1251 s32 E_other_transfer;
1252 s32 E_other_in;
1253 s32 E_other_out;
1254 s32 E_target_abort;
1255 s32 E_debug_break;
1256 s32 E_reject_message;
1257 s32 E_respond_message;
1258 s32 E_select;
1259 s32 E_select_msgout;
1260 s32 E_test_0;
1261 s32 E_test_1;
1262 s32 E_test_2;
1263 s32 E_test_3;
1264 s32 E_dsa_zero;
1265 s32 E_cmdout_cmdout;
1266 s32 E_wait_reselect;
1267 s32 E_dsa_code_begin;
1268
1269 long long options; /* Bitfielded set of options enabled */
1270 volatile u32 test_completed; /* Test completed */
1271 int test_running; /* Test currently running */
1272 s32 test_source
1273 __attribute__ ((aligned (4)));
1274 volatile s32 test_dest;
1275
1276 volatile int state; /* state of driver, only used for
1277 OPTION_700 */
1278
1279 unsigned char dmode; /*
1280 * set to the address of the DMODE
1281 * register for this chip.
1282 */
1283 unsigned char istat; /*
1284 * set to the address of the ISTAT
1285 * register for this chip.
1286 */
1287
1288 int scsi_clock; /*
1289 * SCSI clock in HZ. 0 may be used
1290 * for unknown, although this will
1291 * disable synchronous negotiation.
1292 */
1293
1294 volatile int intrs; /* Number of interrupts */
1295 volatile int resets; /* Number of SCSI resets */
1296 unsigned char saved_dmode;
1297 unsigned char saved_ctest4;
1298 unsigned char saved_ctest7;
1299 unsigned char saved_dcntl;
1300 unsigned char saved_scntl3;
1301
1302 unsigned char this_id_mask;
1303
1304 /* Debugger information */
1305 struct NCR53c7x0_break *breakpoints, /* Linked list of all break points */
1306 *breakpoint_current; /* Current breakpoint being stepped
1307 through, NULL if we are running
1308 normally. */
1309#ifdef NCR_DEBUG
1310 int debug_size; /* Size of debug buffer */
1311 volatile int debug_count; /* Current data count */
1312 volatile char *debug_buf; /* Output ring buffer */
1313 volatile char *debug_write; /* Current write pointer */
1314 volatile char *debug_read; /* Current read pointer */
1315#endif /* def NCR_DEBUG */
1316
1317 /* XXX - primitive debugging junk, remove when working ? */
1318 int debug_print_limit; /* Number of commands to print
1319 out exhaustive debugging
1320 information for if
1321 OPTION_DEBUG_DUMP is set */
1322
1323 unsigned char debug_lun_limit[16]; /* If OPTION_DEBUG_TARGET_LIMIT
1324 set, puke if commands are sent
1325 to other target/lun combinations */
1326
1327 int debug_count_limit; /* Number of commands to execute
1328 before puking to limit debugging
1329 output */
1330
1331
1332 volatile unsigned idle:1; /* set to 1 if idle */
1333
1334 /*
1335 * Table of synchronous+wide transfer parameters set on a per-target
1336 * basis.
1337 */
1338
1339 volatile struct NCR53c7x0_synchronous sync[16]
1340 __attribute__ ((aligned (4)));
1341
1342 volatile Scsi_Cmnd *issue_queue
1343 __attribute__ ((aligned (4)));
1344 /* waiting to be issued by
1345 Linux driver */
1346 volatile struct NCR53c7x0_cmd *running_list;
1347 /* commands running, maintained
1348 by Linux driver */
1349
1350 volatile struct NCR53c7x0_cmd *ncrcurrent; /* currently connected
1351 nexus, ONLY valid for
1352 NCR53c700/NCR53c700-66
1353 */
1354
1355 volatile struct NCR53c7x0_cmd *spare; /* pointer to spare,
1356 allocated at probe time,
1357 which we can use for
1358 initialization */
1359 volatile struct NCR53c7x0_cmd *free;
1360 int max_cmd_size; /* Maximum size of NCR53c7x0_cmd
1361 based on number of
1362 scatter/gather segments, etc.
1363 */
1364 volatile int num_cmds; /* Number of commands
1365 allocated */
1366 volatile int extra_allocate;
1367 volatile unsigned char cmd_allocated[16]; /* Have we allocated commands
1368 for this target yet? If not,
1369 do so ASAP */
1370 volatile unsigned char busy[16][8]; /* number of commands
1371 executing on each target
1372 */
1373 /*
1374 * Eventually, I'll switch to a coroutine for calling
1375 * cmd->done(cmd), etc. so that we can overlap interrupt
1376 * processing with this code for maximum performance.
1377 */
1378
1379 volatile struct NCR53c7x0_cmd *finished_queue;
1380
1381 /* Shared variables between SCRIPT and host driver */
1382 volatile u32 *schedule
1383 __attribute__ ((aligned (4))); /* Array of JUMPs to dsa_begin
1384 routines of various DSAs.
1385 When not in use, replace
1386 with jump to next slot */
1387
1388
1389 volatile unsigned char msg_buf[16]; /* buffer for messages
1390 other than the command
1391 complete message */
1392
1393 /* Per-target default synchronous and WIDE messages */
1394 volatile unsigned char synchronous_want[16][5];
1395 volatile unsigned char wide_want[16][4];
1396
1397 /* Bit fielded set of targets we want to speak synchronously with */
1398 volatile u16 initiate_sdtr;
1399 /* Bit fielded set of targets we want to speak wide with */
1400 volatile u16 initiate_wdtr;
1401 /* Bit fielded list of targets we've talked to. */
1402 volatile u16 talked_to;
1403
1404 /* Array of bit-fielded lun lists that we need to request_sense */
1405 volatile unsigned char request_sense[16];
1406
1407 u32 addr_reconnect_dsa_head
1408 __attribute__ ((aligned (4))); /* RISCy style constant,
1409 address of following */
1410 volatile u32 reconnect_dsa_head;
1411 /* Data identifying nexus we are trying to match during reselection */
1412 volatile unsigned char reselected_identify; /* IDENTIFY message */
1413 volatile unsigned char reselected_tag; /* second byte of queue tag
1414 message or 0 */
1415
1416 /* These were static variables before we moved them */
1417
1418 s32 NCR53c7xx_zero
1419 __attribute__ ((aligned (4)));
1420 s32 NCR53c7xx_sink;
1421 u32 NOP_insn;
1422 char NCR53c7xx_msg_reject;
1423 char NCR53c7xx_msg_abort;
1424 char NCR53c7xx_msg_nop;
1425
1426 /*
1427 * Following item introduced by RGH to support NCRc710, which is
1428 * VERY brain-dead when it come to memory moves
1429 */
1430
1431 /* DSA save area used only by the NCR chip */
1432 volatile unsigned long saved2_dsa
1433 __attribute__ ((aligned (4)));
1434
1435 volatile unsigned long emulated_intfly
1436 __attribute__ ((aligned (4)));
1437
1438 volatile int event_size, event_index;
1439 volatile struct NCR53c7x0_event *events;
1440
1441 /* If we need to generate code to kill off the currently connected
1442 command, this is where we do it. Should have a BMI instruction
1443 to source or sink the current data, followed by a JUMP
1444 to abort_connected */
1445
1446 u32 *abort_script;
1447
1448 int script_count; /* Size of script in words */
1449 u32 script[0]; /* Relocated SCSI script */
1450
1451};
1452
1453#define SCSI_IRQ_NONE 255
1454#define DMA_NONE 255
1455#define IRQ_AUTO 254
1456#define DMA_AUTO 254
1457
1458#define BOARD_GENERIC 0
1459
1460#define NCR53c7x0_insn_size(insn) \
1461 (((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2)
1462
1463
1464#define NCR53c7x0_local_declare() \
1465 volatile unsigned char *NCR53c7x0_address_memory; \
1466 unsigned int NCR53c7x0_address_io; \
1467 int NCR53c7x0_memory_mapped
1468
1469#define NCR53c7x0_local_setup(host) \
1470 NCR53c7x0_address_memory = (void *) (host)->base; \
1471 NCR53c7x0_address_io = (unsigned int) (host)->io_port; \
1472 NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *) \
1473 host->hostdata[0])-> options & OPTION_MEMORY_MAPPED
1474
1475#ifdef BIG_ENDIAN
1476/* These could be more efficient, given that we are always memory mapped,
1477 * but they don't give the same problems as the write macros, so leave
1478 * them. */
1479#ifdef __mc68000__
1480#define NCR53c7x0_read8(address) \
1481 ((unsigned int)raw_inb((u32)NCR53c7x0_address_memory + ((u32)(address)^3)) )
1482
1483#define NCR53c7x0_read16(address) \
1484 ((unsigned int)raw_inw((u32)NCR53c7x0_address_memory + ((u32)(address)^2)))
1485#else
1486#define NCR53c7x0_read8(address) \
1487 (NCR53c7x0_memory_mapped ? \
1488 (unsigned int)readb((u32)NCR53c7x0_address_memory + ((u32)(address)^3)) : \
1489 inb(NCR53c7x0_address_io + (address)))
1490
1491#define NCR53c7x0_read16(address) \
1492 (NCR53c7x0_memory_mapped ? \
1493 (unsigned int)readw((u32)NCR53c7x0_address_memory + ((u32)(address)^2)) : \
1494 inw(NCR53c7x0_address_io + (address)))
1495#endif /* mc68000 */
1496#else
1497#define NCR53c7x0_read8(address) \
1498 (NCR53c7x0_memory_mapped ? \
1499 (unsigned int)readb((u32)NCR53c7x0_address_memory + (u32)(address)) : \
1500 inb(NCR53c7x0_address_io + (address)))
1501
1502#define NCR53c7x0_read16(address) \
1503 (NCR53c7x0_memory_mapped ? \
1504 (unsigned int)readw((u32)NCR53c7x0_address_memory + (u32)(address)) : \
1505 inw(NCR53c7x0_address_io + (address)))
1506#endif
1507
1508#ifdef __mc68000__
1509#define NCR53c7x0_read32(address) \
1510 ((unsigned int) raw_inl((u32)NCR53c7x0_address_memory + (u32)(address)))
1511#else
1512#define NCR53c7x0_read32(address) \
1513 (NCR53c7x0_memory_mapped ? \
1514 (unsigned int) readl((u32)NCR53c7x0_address_memory + (u32)(address)) : \
1515 inl(NCR53c7x0_address_io + (address)))
1516#endif /* mc68000*/
1517
1518#ifdef BIG_ENDIAN
1519/* If we are big-endian, then we are not Intel, so probably don't have
1520 * an i/o map as well as a memory map. So, let's assume memory mapped.
1521 * Also, I am having terrible problems trying to persuade the compiler
1522 * not to lay down code which does a read after write for these macros.
1523 * If you remove 'volatile' from writeb() and friends it is ok....
1524 */
1525
1526#define NCR53c7x0_write8(address,value) \
1527 *(volatile unsigned char *) \
1528 ((u32)NCR53c7x0_address_memory + ((u32)(address)^3)) = (value)
1529
1530#define NCR53c7x0_write16(address,value) \
1531 *(volatile unsigned short *) \
1532 ((u32)NCR53c7x0_address_memory + ((u32)(address)^2)) = (value)
1533
1534#define NCR53c7x0_write32(address,value) \
1535 *(volatile unsigned long *) \
1536 ((u32)NCR53c7x0_address_memory + ((u32)(address))) = (value)
1537
1538#else
1539
1540#define NCR53c7x0_write8(address,value) \
1541 (NCR53c7x0_memory_mapped ? \
1542 ({writeb((value), (u32)NCR53c7x0_address_memory + (u32)(address)); mb();}) : \
1543 outb((value), NCR53c7x0_address_io + (address)))
1544
1545#define NCR53c7x0_write16(address,value) \
1546 (NCR53c7x0_memory_mapped ? \
1547 ({writew((value), (u32)NCR53c7x0_address_memory + (u32)(address)); mb();}) : \
1548 outw((value), NCR53c7x0_address_io + (address)))
1549
1550#define NCR53c7x0_write32(address,value) \
1551 (NCR53c7x0_memory_mapped ? \
1552 ({writel((value), (u32)NCR53c7x0_address_memory + (u32)(address)); mb();}) : \
1553 outl((value), NCR53c7x0_address_io + (address)))
1554
1555#endif
1556
1557/* Patch arbitrary 32 bit words in the script */
1558#define patch_abs_32(script, offset, symbol, value) \
1559 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1560 (u32)); ++i) { \
1561 (script)[A_##symbol##_used[i] - (offset)] += (value); \
1562 if (hostdata->options & OPTION_DEBUG_FIXUP) \
1563 printk("scsi%d : %s reference %d at 0x%x in %s is now 0x%x\n",\
1564 host->host_no, #symbol, i, A_##symbol##_used[i] - \
1565 (int)(offset), #script, (script)[A_##symbol##_used[i] - \
1566 (offset)]); \
1567 }
1568
1569/* Patch read/write instruction immediate field */
1570#define patch_abs_rwri_data(script, offset, symbol, value) \
1571 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1572 (u32)); ++i) \
1573 (script)[A_##symbol##_used[i] - (offset)] = \
1574 ((script)[A_##symbol##_used[i] - (offset)] & \
1575 ~DBC_RWRI_IMMEDIATE_MASK) | \
1576 (((value) << DBC_RWRI_IMMEDIATE_SHIFT) & \
1577 DBC_RWRI_IMMEDIATE_MASK)
1578
1579/* Patch transfer control instruction data field */
1580#define patch_abs_tci_data(script, offset, symbol, value) \
1581 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1582 (u32)); ++i) \
1583 (script)[A_##symbol##_used[i] - (offset)] = \
1584 ((script)[A_##symbol##_used[i] - (offset)] & \
1585 ~DBC_TCI_DATA_MASK) | \
1586 (((value) << DBC_TCI_DATA_SHIFT) & \
1587 DBC_TCI_DATA_MASK)
1588
1589/* Patch field in dsa structure (assignment should be +=?) */
1590#define patch_dsa_32(dsa, symbol, word, value) \
1591 { \
1592 (dsa)[(hostdata->##symbol - hostdata->dsa_start) / sizeof(u32) \
1593 + (word)] = (value); \
1594 if (hostdata->options & OPTION_DEBUG_DSA) \
1595 printk("scsi : dsa %s symbol %s(%d) word %d now 0x%x\n", \
1596 #dsa, #symbol, hostdata->##symbol, \
1597 (word), (u32) (value)); \
1598 }
1599
1600/* Paranoid people could use panic() here. */
1601#define FATAL(host) shutdown((host));
1602
1603extern int ncr53c7xx_init(struct scsi_host_template *tpnt, int board, int chip,
1604 unsigned long base, int io_port, int irq, int dma,
1605 long long options, int clock);
1606
1607#endif /* NCR53c710_C */
1608#endif /* NCR53c710_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 16:54:43 -0500