diff options
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/wireless/ath/ath5k/ath5k.h | 8 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/attach.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/phy.c | 1 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath5k/qcu.c | 16 |
4 files changed, 16 insertions, 11 deletions
diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h index 66359dca322..b1429da41a8 100644 --- a/drivers/net/wireless/ath/ath5k/ath5k.h +++ b/drivers/net/wireless/ath/ath5k/ath5k.h | |||
@@ -424,6 +424,12 @@ enum ath5k_ant_mode { | |||
424 | AR5K_ANTMODE_MAX, | 424 | AR5K_ANTMODE_MAX, |
425 | }; | 425 | }; |
426 | 426 | ||
427 | enum ath5k_bw_mode { | ||
428 | AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */ | ||
429 | AR5K_BWMODE_5MHZ = 1, /* Quarter rate */ | ||
430 | AR5K_BWMODE_10MHZ = 2, /* Half rate */ | ||
431 | AR5K_BWMODE_40MHZ = 3 /* Turbo */ | ||
432 | }; | ||
427 | 433 | ||
428 | /****************\ | 434 | /****************\ |
429 | TX DEFINITIONS | 435 | TX DEFINITIONS |
@@ -1026,7 +1032,6 @@ struct ath5k_hw { | |||
1026 | enum ath5k_int ah_imr; | 1032 | enum ath5k_int ah_imr; |
1027 | 1033 | ||
1028 | struct ieee80211_channel *ah_current_channel; | 1034 | struct ieee80211_channel *ah_current_channel; |
1029 | bool ah_turbo; | ||
1030 | bool ah_calibration; | 1035 | bool ah_calibration; |
1031 | bool ah_single_chip; | 1036 | bool ah_single_chip; |
1032 | 1037 | ||
@@ -1044,6 +1049,7 @@ struct ath5k_hw { | |||
1044 | 1049 | ||
1045 | u32 ah_limit_tx_retries; | 1050 | u32 ah_limit_tx_retries; |
1046 | u8 ah_coverage_class; | 1051 | u8 ah_coverage_class; |
1052 | u8 ah_bwmode; | ||
1047 | 1053 | ||
1048 | /* Antenna Control */ | 1054 | /* Antenna Control */ |
1049 | u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; | 1055 | u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; |
diff --git a/drivers/net/wireless/ath/ath5k/attach.c b/drivers/net/wireless/ath/ath5k/attach.c index fbe8aca975d..ed86b9dde1b 100644 --- a/drivers/net/wireless/ath/ath5k/attach.c +++ b/drivers/net/wireless/ath/ath5k/attach.c | |||
@@ -115,7 +115,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc) | |||
115 | * HW information | 115 | * HW information |
116 | */ | 116 | */ |
117 | ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; | 117 | ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; |
118 | ah->ah_turbo = false; | 118 | ah->ah_bwmode = AR5K_BWMODE_DEFAULT; |
119 | ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; | 119 | ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; |
120 | ah->ah_imr = 0; | 120 | ah->ah_imr = 0; |
121 | ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; | 121 | ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; |
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c index 1c41fa83745..02869c7d596 100644 --- a/drivers/net/wireless/ath/ath5k/phy.c +++ b/drivers/net/wireless/ath/ath5k/phy.c | |||
@@ -1235,7 +1235,6 @@ static int ath5k_hw_channel(struct ath5k_hw *ah, | |||
1235 | } | 1235 | } |
1236 | 1236 | ||
1237 | ah->ah_current_channel = channel; | 1237 | ah->ah_current_channel = channel; |
1238 | ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false; | ||
1239 | ath5k_hw_set_clockrate(ah); | 1238 | ath5k_hw_set_clockrate(ah); |
1240 | 1239 | ||
1241 | return 0; | 1240 | return 0; |
diff --git a/drivers/net/wireless/ath/ath5k/qcu.c b/drivers/net/wireless/ath/ath5k/qcu.c index ed62273cdf0..778fb59d89f 100644 --- a/drivers/net/wireless/ath/ath5k/qcu.c +++ b/drivers/net/wireless/ath/ath5k/qcu.c | |||
@@ -246,21 +246,21 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue) | |||
246 | return 0; | 246 | return 0; |
247 | 247 | ||
248 | /* Set Slot time */ | 248 | /* Set Slot time */ |
249 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 249 | ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? |
250 | AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME, | 250 | AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME, |
251 | AR5K_SLOT_TIME); | 251 | AR5K_SLOT_TIME); |
252 | /* Set ACK_CTS timeout */ | 252 | /* Set ACK_CTS timeout */ |
253 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 253 | ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? |
254 | AR5K_INIT_ACK_CTS_TIMEOUT_TURBO : | 254 | AR5K_INIT_ACK_CTS_TIMEOUT_TURBO : |
255 | AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME); | 255 | AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME); |
256 | /* Set Transmit Latency */ | 256 | /* Set Transmit Latency */ |
257 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 257 | ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? |
258 | AR5K_INIT_TRANSMIT_LATENCY_TURBO : | 258 | AR5K_INIT_TRANSMIT_LATENCY_TURBO : |
259 | AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210); | 259 | AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210); |
260 | 260 | ||
261 | /* Set IFS0 */ | 261 | /* Set IFS0 */ |
262 | if (ah->ah_turbo) { | 262 | if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) { |
263 | ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO + | 263 | ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO + |
264 | tq->tqi_aifs * AR5K_INIT_SLOT_TIME_TURBO) << | 264 | tq->tqi_aifs * AR5K_INIT_SLOT_TIME_TURBO) << |
265 | AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO, | 265 | AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO, |
266 | AR5K_IFS0); | 266 | AR5K_IFS0); |
@@ -272,18 +272,18 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue) | |||
272 | } | 272 | } |
273 | 273 | ||
274 | /* Set IFS1 */ | 274 | /* Set IFS1 */ |
275 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 275 | ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? |
276 | AR5K_INIT_PROTO_TIME_CNTRL_TURBO : | 276 | AR5K_INIT_PROTO_TIME_CNTRL_TURBO : |
277 | AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1); | 277 | AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1); |
278 | /* Set AR5K_PHY_SETTLING */ | 278 | /* Set AR5K_PHY_SETTLING */ |
279 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 279 | ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? |
280 | (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) | 280 | (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) |
281 | | 0x38 : | 281 | | 0x38 : |
282 | (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) | 282 | (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) |
283 | | 0x1C, | 283 | | 0x1C, |
284 | AR5K_PHY_SETTLING); | 284 | AR5K_PHY_SETTLING); |
285 | /* Set Frame Control Register */ | 285 | /* Set Frame Control Register */ |
286 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 286 | ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? |
287 | (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE | | 287 | (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE | |
288 | AR5K_PHY_TURBO_SHORT | 0x2020) : | 288 | AR5K_PHY_TURBO_SHORT | 0x2020) : |
289 | (AR5K_PHY_FRAME_CTL_INI | 0x1020), | 289 | (AR5K_PHY_FRAME_CTL_INI | 0x1020), |