diff options
Diffstat (limited to 'drivers/net/wireless/wl12xx/wl1251_ops.c')
-rw-r--r-- | drivers/net/wireless/wl12xx/wl1251_ops.c | 190 |
1 files changed, 95 insertions, 95 deletions
diff --git a/drivers/net/wireless/wl12xx/wl1251_ops.c b/drivers/net/wireless/wl12xx/wl1251_ops.c index cdfd2c21899..96a45f59529 100644 --- a/drivers/net/wireless/wl12xx/wl1251_ops.c +++ b/drivers/net/wireless/wl12xx/wl1251_ops.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * This file is part of wl12xx | 2 | * This file is part of wl1251 |
3 | * | 3 | * |
4 | * Copyright (C) 2008-2009 Nokia Corporation | 4 | * Copyright (C) 2008-2009 Nokia Corporation |
5 | * | 5 | * |
@@ -35,7 +35,7 @@ | |||
35 | #include "wl1251_ps.h" | 35 | #include "wl1251_ps.h" |
36 | #include "wl1251_init.h" | 36 | #include "wl1251_init.h" |
37 | 37 | ||
38 | static struct wl12xx_partition_set wl1251_part_table[PART_TABLE_LEN] = { | 38 | static struct wl1251_partition_set wl1251_part_table[PART_TABLE_LEN] = { |
39 | [PART_DOWN] = { | 39 | [PART_DOWN] = { |
40 | .mem = { | 40 | .mem = { |
41 | .start = 0x00000000, | 41 | .start = 0x00000000, |
@@ -75,31 +75,31 @@ static enum wl12xx_acx_int_reg wl1251_acx_reg_table[ACX_REG_TABLE_LEN] = { | |||
75 | [ACX_REG_ECPU_CONTROL] = (REGISTERS_BASE + 0x0804) | 75 | [ACX_REG_ECPU_CONTROL] = (REGISTERS_BASE + 0x0804) |
76 | }; | 76 | }; |
77 | 77 | ||
78 | static int wl1251_upload_firmware(struct wl12xx *wl) | 78 | static int wl1251_upload_firmware(struct wl1251 *wl) |
79 | { | 79 | { |
80 | struct wl12xx_partition_set *p_table = wl->chip.p_table; | 80 | struct wl1251_partition_set *p_table = wl->chip.p_table; |
81 | int addr, chunk_num, partition_limit; | 81 | int addr, chunk_num, partition_limit; |
82 | size_t fw_data_len; | 82 | size_t fw_data_len; |
83 | u8 *p; | 83 | u8 *p; |
84 | 84 | ||
85 | /* whal_FwCtrl_LoadFwImageSm() */ | 85 | /* whal_FwCtrl_LoadFwImageSm() */ |
86 | 86 | ||
87 | wl12xx_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x", | 87 | wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x", |
88 | wl12xx_reg_read32(wl, CHIP_ID_B)); | 88 | wl1251_reg_read32(wl, CHIP_ID_B)); |
89 | 89 | ||
90 | /* 10.0 check firmware length and set partition */ | 90 | /* 10.0 check firmware length and set partition */ |
91 | fw_data_len = (wl->fw[4] << 24) | (wl->fw[5] << 16) | | 91 | fw_data_len = (wl->fw[4] << 24) | (wl->fw[5] << 16) | |
92 | (wl->fw[6] << 8) | (wl->fw[7]); | 92 | (wl->fw[6] << 8) | (wl->fw[7]); |
93 | 93 | ||
94 | wl12xx_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len, | 94 | wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len, |
95 | CHUNK_SIZE); | 95 | CHUNK_SIZE); |
96 | 96 | ||
97 | if ((fw_data_len % 4) != 0) { | 97 | if ((fw_data_len % 4) != 0) { |
98 | wl12xx_error("firmware length not multiple of four"); | 98 | wl1251_error("firmware length not multiple of four"); |
99 | return -EIO; | 99 | return -EIO; |
100 | } | 100 | } |
101 | 101 | ||
102 | wl12xx_set_partition(wl, | 102 | wl1251_set_partition(wl, |
103 | p_table[PART_DOWN].mem.start, | 103 | p_table[PART_DOWN].mem.start, |
104 | p_table[PART_DOWN].mem.size, | 104 | p_table[PART_DOWN].mem.size, |
105 | p_table[PART_DOWN].reg.start, | 105 | p_table[PART_DOWN].reg.start, |
@@ -118,7 +118,7 @@ static int wl1251_upload_firmware(struct wl12xx *wl) | |||
118 | chunk_num * CHUNK_SIZE; | 118 | chunk_num * CHUNK_SIZE; |
119 | partition_limit = chunk_num * CHUNK_SIZE + | 119 | partition_limit = chunk_num * CHUNK_SIZE + |
120 | p_table[PART_DOWN].mem.size; | 120 | p_table[PART_DOWN].mem.size; |
121 | wl12xx_set_partition(wl, | 121 | wl1251_set_partition(wl, |
122 | addr, | 122 | addr, |
123 | p_table[PART_DOWN].mem.size, | 123 | p_table[PART_DOWN].mem.size, |
124 | p_table[PART_DOWN].reg.start, | 124 | p_table[PART_DOWN].reg.start, |
@@ -128,9 +128,9 @@ static int wl1251_upload_firmware(struct wl12xx *wl) | |||
128 | /* 10.3 upload the chunk */ | 128 | /* 10.3 upload the chunk */ |
129 | addr = p_table[PART_DOWN].mem.start + chunk_num * CHUNK_SIZE; | 129 | addr = p_table[PART_DOWN].mem.start + chunk_num * CHUNK_SIZE; |
130 | p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE; | 130 | p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE; |
131 | wl12xx_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x", | 131 | wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x", |
132 | p, addr); | 132 | p, addr); |
133 | wl12xx_spi_mem_write(wl, addr, p, CHUNK_SIZE); | 133 | wl1251_spi_mem_write(wl, addr, p, CHUNK_SIZE); |
134 | 134 | ||
135 | chunk_num++; | 135 | chunk_num++; |
136 | } | 136 | } |
@@ -138,14 +138,14 @@ static int wl1251_upload_firmware(struct wl12xx *wl) | |||
138 | /* 10.4 upload the last chunk */ | 138 | /* 10.4 upload the last chunk */ |
139 | addr = p_table[PART_DOWN].mem.start + chunk_num * CHUNK_SIZE; | 139 | addr = p_table[PART_DOWN].mem.start + chunk_num * CHUNK_SIZE; |
140 | p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE; | 140 | p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE; |
141 | wl12xx_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x", | 141 | wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x", |
142 | fw_data_len % CHUNK_SIZE, p, addr); | 142 | fw_data_len % CHUNK_SIZE, p, addr); |
143 | wl12xx_spi_mem_write(wl, addr, p, fw_data_len % CHUNK_SIZE); | 143 | wl1251_spi_mem_write(wl, addr, p, fw_data_len % CHUNK_SIZE); |
144 | 144 | ||
145 | return 0; | 145 | return 0; |
146 | } | 146 | } |
147 | 147 | ||
148 | static int wl1251_upload_nvs(struct wl12xx *wl) | 148 | static int wl1251_upload_nvs(struct wl1251 *wl) |
149 | { | 149 | { |
150 | size_t nvs_len, nvs_bytes_written, burst_len; | 150 | size_t nvs_len, nvs_bytes_written, burst_len; |
151 | int nvs_start, i; | 151 | int nvs_start, i; |
@@ -181,10 +181,10 @@ static int wl1251_upload_nvs(struct wl12xx *wl) | |||
181 | val = (nvs_ptr[0] | (nvs_ptr[1] << 8) | 181 | val = (nvs_ptr[0] | (nvs_ptr[1] << 8) |
182 | | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24)); | 182 | | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24)); |
183 | 183 | ||
184 | wl12xx_debug(DEBUG_BOOT, | 184 | wl1251_debug(DEBUG_BOOT, |
185 | "nvs burst write 0x%x: 0x%x", | 185 | "nvs burst write 0x%x: 0x%x", |
186 | dest_addr, val); | 186 | dest_addr, val); |
187 | wl12xx_mem_write32(wl, dest_addr, val); | 187 | wl1251_mem_write32(wl, dest_addr, val); |
188 | 188 | ||
189 | nvs_ptr += 4; | 189 | nvs_ptr += 4; |
190 | dest_addr += 4; | 190 | dest_addr += 4; |
@@ -200,7 +200,7 @@ static int wl1251_upload_nvs(struct wl12xx *wl) | |||
200 | nvs_len = ALIGN(nvs_len, 4); | 200 | nvs_len = ALIGN(nvs_len, 4); |
201 | 201 | ||
202 | /* Now we must set the partition correctly */ | 202 | /* Now we must set the partition correctly */ |
203 | wl12xx_set_partition(wl, nvs_start, | 203 | wl1251_set_partition(wl, nvs_start, |
204 | wl->chip.p_table[PART_DOWN].mem.size, | 204 | wl->chip.p_table[PART_DOWN].mem.size, |
205 | wl->chip.p_table[PART_DOWN].reg.start, | 205 | wl->chip.p_table[PART_DOWN].reg.start, |
206 | wl->chip.p_table[PART_DOWN].reg.size); | 206 | wl->chip.p_table[PART_DOWN].reg.size); |
@@ -213,10 +213,10 @@ static int wl1251_upload_nvs(struct wl12xx *wl) | |||
213 | 213 | ||
214 | val = cpu_to_le32(val); | 214 | val = cpu_to_le32(val); |
215 | 215 | ||
216 | wl12xx_debug(DEBUG_BOOT, | 216 | wl1251_debug(DEBUG_BOOT, |
217 | "nvs write table 0x%x: 0x%x", | 217 | "nvs write table 0x%x: 0x%x", |
218 | nvs_start, val); | 218 | nvs_start, val); |
219 | wl12xx_mem_write32(wl, nvs_start, val); | 219 | wl1251_mem_write32(wl, nvs_start, val); |
220 | 220 | ||
221 | nvs_ptr += 4; | 221 | nvs_ptr += 4; |
222 | nvs_bytes_written += 4; | 222 | nvs_bytes_written += 4; |
@@ -226,12 +226,12 @@ static int wl1251_upload_nvs(struct wl12xx *wl) | |||
226 | return 0; | 226 | return 0; |
227 | } | 227 | } |
228 | 228 | ||
229 | static int wl1251_boot(struct wl12xx *wl) | 229 | static int wl1251_boot(struct wl1251 *wl) |
230 | { | 230 | { |
231 | int ret = 0, minor_minor_e2_ver; | 231 | int ret = 0, minor_minor_e2_ver; |
232 | u32 tmp, boot_data; | 232 | u32 tmp, boot_data; |
233 | 233 | ||
234 | ret = wl12xx_boot_soft_reset(wl); | 234 | ret = wl1251_boot_soft_reset(wl); |
235 | if (ret < 0) | 235 | if (ret < 0) |
236 | goto out; | 236 | goto out; |
237 | 237 | ||
@@ -242,39 +242,39 @@ static int wl1251_boot(struct wl12xx *wl) | |||
242 | 242 | ||
243 | /* write firmware's last address (ie. it's length) to | 243 | /* write firmware's last address (ie. it's length) to |
244 | * ACX_EEPROMLESS_IND_REG */ | 244 | * ACX_EEPROMLESS_IND_REG */ |
245 | wl12xx_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len); | 245 | wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len); |
246 | 246 | ||
247 | /* 6. read the EEPROM parameters */ | 247 | /* 6. read the EEPROM parameters */ |
248 | tmp = wl12xx_reg_read32(wl, SCR_PAD2); | 248 | tmp = wl1251_reg_read32(wl, SCR_PAD2); |
249 | 249 | ||
250 | /* 7. read bootdata */ | 250 | /* 7. read bootdata */ |
251 | wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8; | 251 | wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8; |
252 | wl->boot_attr.major = (tmp & 0x00FF0000) >> 16; | 252 | wl->boot_attr.major = (tmp & 0x00FF0000) >> 16; |
253 | tmp = wl12xx_reg_read32(wl, SCR_PAD3); | 253 | tmp = wl1251_reg_read32(wl, SCR_PAD3); |
254 | 254 | ||
255 | /* 8. check bootdata and call restart sequence */ | 255 | /* 8. check bootdata and call restart sequence */ |
256 | wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16; | 256 | wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16; |
257 | minor_minor_e2_ver = (tmp & 0xFF000000) >> 24; | 257 | minor_minor_e2_ver = (tmp & 0xFF000000) >> 24; |
258 | 258 | ||
259 | wl12xx_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x " | 259 | wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x " |
260 | "minorE2Ver 0x%x minor_minor_e2_ver 0x%x", | 260 | "minorE2Ver 0x%x minor_minor_e2_ver 0x%x", |
261 | wl->boot_attr.radio_type, wl->boot_attr.major, | 261 | wl->boot_attr.radio_type, wl->boot_attr.major, |
262 | wl->boot_attr.minor, minor_minor_e2_ver); | 262 | wl->boot_attr.minor, minor_minor_e2_ver); |
263 | 263 | ||
264 | ret = wl12xx_boot_init_seq(wl); | 264 | ret = wl1251_boot_init_seq(wl); |
265 | if (ret < 0) | 265 | if (ret < 0) |
266 | goto out; | 266 | goto out; |
267 | 267 | ||
268 | /* 9. NVS processing done */ | 268 | /* 9. NVS processing done */ |
269 | boot_data = wl12xx_reg_read32(wl, ACX_REG_ECPU_CONTROL); | 269 | boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL); |
270 | 270 | ||
271 | wl12xx_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data); | 271 | wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data); |
272 | 272 | ||
273 | /* 10. check that ECPU_CONTROL_HALT bits are set in | 273 | /* 10. check that ECPU_CONTROL_HALT bits are set in |
274 | * pWhalBus->uBootData and start uploading firmware | 274 | * pWhalBus->uBootData and start uploading firmware |
275 | */ | 275 | */ |
276 | if ((boot_data & ECPU_CONTROL_HALT) == 0) { | 276 | if ((boot_data & ECPU_CONTROL_HALT) == 0) { |
277 | wl12xx_error("boot failed, ECPU_CONTROL_HALT not set"); | 277 | wl1251_error("boot failed, ECPU_CONTROL_HALT not set"); |
278 | ret = -EIO; | 278 | ret = -EIO; |
279 | goto out; | 279 | goto out; |
280 | } | 280 | } |
@@ -284,7 +284,7 @@ static int wl1251_boot(struct wl12xx *wl) | |||
284 | goto out; | 284 | goto out; |
285 | 285 | ||
286 | /* 10.5 start firmware */ | 286 | /* 10.5 start firmware */ |
287 | ret = wl12xx_boot_run_firmware(wl); | 287 | ret = wl1251_boot_run_firmware(wl); |
288 | if (ret < 0) | 288 | if (ret < 0) |
289 | goto out; | 289 | goto out; |
290 | 290 | ||
@@ -292,12 +292,12 @@ out: | |||
292 | return ret; | 292 | return ret; |
293 | } | 293 | } |
294 | 294 | ||
295 | static int wl1251_mem_cfg(struct wl12xx *wl) | 295 | static int wl1251_mem_cfg(struct wl1251 *wl) |
296 | { | 296 | { |
297 | struct wl1251_acx_config_memory *mem_conf; | 297 | struct wl1251_acx_config_memory *mem_conf; |
298 | int ret, i; | 298 | int ret, i; |
299 | 299 | ||
300 | wl12xx_debug(DEBUG_ACX, "wl1251 mem cfg"); | 300 | wl1251_debug(DEBUG_ACX, "wl1251 mem cfg"); |
301 | 301 | ||
302 | mem_conf = kzalloc(sizeof(*mem_conf), GFP_KERNEL); | 302 | mem_conf = kzalloc(sizeof(*mem_conf), GFP_KERNEL); |
303 | if (!mem_conf) { | 303 | if (!mem_conf) { |
@@ -327,10 +327,10 @@ static int wl1251_mem_cfg(struct wl12xx *wl) | |||
327 | mem_conf->tx_queue_config[i].attributes = i; | 327 | mem_conf->tx_queue_config[i].attributes = i; |
328 | } | 328 | } |
329 | 329 | ||
330 | ret = wl12xx_cmd_configure(wl, ACX_MEM_CFG, mem_conf, | 330 | ret = wl1251_cmd_configure(wl, ACX_MEM_CFG, mem_conf, |
331 | sizeof(*mem_conf)); | 331 | sizeof(*mem_conf)); |
332 | if (ret < 0) { | 332 | if (ret < 0) { |
333 | wl12xx_warning("wl1251 mem config failed: %d", ret); | 333 | wl1251_warning("wl1251 mem config failed: %d", ret); |
334 | goto out; | 334 | goto out; |
335 | } | 335 | } |
336 | 336 | ||
@@ -339,7 +339,7 @@ out: | |||
339 | return ret; | 339 | return ret; |
340 | } | 340 | } |
341 | 341 | ||
342 | static int wl1251_hw_init_mem_config(struct wl12xx *wl) | 342 | static int wl1251_hw_init_mem_config(struct wl1251 *wl) |
343 | { | 343 | { |
344 | int ret; | 344 | int ret; |
345 | 345 | ||
@@ -350,15 +350,15 @@ static int wl1251_hw_init_mem_config(struct wl12xx *wl) | |||
350 | wl->target_mem_map = kzalloc(sizeof(struct wl1251_acx_mem_map), | 350 | wl->target_mem_map = kzalloc(sizeof(struct wl1251_acx_mem_map), |
351 | GFP_KERNEL); | 351 | GFP_KERNEL); |
352 | if (!wl->target_mem_map) { | 352 | if (!wl->target_mem_map) { |
353 | wl12xx_error("couldn't allocate target memory map"); | 353 | wl1251_error("couldn't allocate target memory map"); |
354 | return -ENOMEM; | 354 | return -ENOMEM; |
355 | } | 355 | } |
356 | 356 | ||
357 | /* we now ask for the firmware built memory map */ | 357 | /* we now ask for the firmware built memory map */ |
358 | ret = wl12xx_acx_mem_map(wl, wl->target_mem_map, | 358 | ret = wl1251_acx_mem_map(wl, wl->target_mem_map, |
359 | sizeof(struct wl1251_acx_mem_map)); | 359 | sizeof(struct wl1251_acx_mem_map)); |
360 | if (ret < 0) { | 360 | if (ret < 0) { |
361 | wl12xx_error("couldn't retrieve firmware memory map"); | 361 | wl1251_error("couldn't retrieve firmware memory map"); |
362 | kfree(wl->target_mem_map); | 362 | kfree(wl->target_mem_map); |
363 | wl->target_mem_map = NULL; | 363 | wl->target_mem_map = NULL; |
364 | return ret; | 364 | return ret; |
@@ -367,19 +367,19 @@ static int wl1251_hw_init_mem_config(struct wl12xx *wl) | |||
367 | return 0; | 367 | return 0; |
368 | } | 368 | } |
369 | 369 | ||
370 | static void wl1251_set_ecpu_ctrl(struct wl12xx *wl, u32 flag) | 370 | static void wl1251_set_ecpu_ctrl(struct wl1251 *wl, u32 flag) |
371 | { | 371 | { |
372 | u32 cpu_ctrl; | 372 | u32 cpu_ctrl; |
373 | 373 | ||
374 | /* 10.5.0 run the firmware (I) */ | 374 | /* 10.5.0 run the firmware (I) */ |
375 | cpu_ctrl = wl12xx_reg_read32(wl, ACX_REG_ECPU_CONTROL); | 375 | cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL); |
376 | 376 | ||
377 | /* 10.5.1 run the firmware (II) */ | 377 | /* 10.5.1 run the firmware (II) */ |
378 | cpu_ctrl &= ~flag; | 378 | cpu_ctrl &= ~flag; |
379 | wl12xx_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl); | 379 | wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl); |
380 | } | 380 | } |
381 | 381 | ||
382 | static void wl1251_target_enable_interrupts(struct wl12xx *wl) | 382 | static void wl1251_target_enable_interrupts(struct wl1251 *wl) |
383 | { | 383 | { |
384 | /* Enable target's interrupts */ | 384 | /* Enable target's interrupts */ |
385 | wl->intr_mask = WL1251_ACX_INTR_RX0_DATA | | 385 | wl->intr_mask = WL1251_ACX_INTR_RX0_DATA | |
@@ -388,60 +388,60 @@ static void wl1251_target_enable_interrupts(struct wl12xx *wl) | |||
388 | WL1251_ACX_INTR_EVENT_A | | 388 | WL1251_ACX_INTR_EVENT_A | |
389 | WL1251_ACX_INTR_EVENT_B | | 389 | WL1251_ACX_INTR_EVENT_B | |
390 | WL1251_ACX_INTR_INIT_COMPLETE; | 390 | WL1251_ACX_INTR_INIT_COMPLETE; |
391 | wl12xx_boot_target_enable_interrupts(wl); | 391 | wl1251_boot_target_enable_interrupts(wl); |
392 | } | 392 | } |
393 | 393 | ||
394 | static void wl1251_fw_version(struct wl12xx *wl) | 394 | static void wl1251_fw_version(struct wl1251 *wl) |
395 | { | 395 | { |
396 | wl12xx_acx_fw_version(wl, wl->chip.fw_ver, sizeof(wl->chip.fw_ver)); | 396 | wl1251_acx_fw_version(wl, wl->chip.fw_ver, sizeof(wl->chip.fw_ver)); |
397 | } | 397 | } |
398 | 398 | ||
399 | static void wl1251_irq_work(struct work_struct *work) | 399 | static void wl1251_irq_work(struct work_struct *work) |
400 | { | 400 | { |
401 | u32 intr; | 401 | u32 intr; |
402 | struct wl12xx *wl = | 402 | struct wl1251 *wl = |
403 | container_of(work, struct wl12xx, irq_work); | 403 | container_of(work, struct wl1251, irq_work); |
404 | int ret; | 404 | int ret; |
405 | 405 | ||
406 | mutex_lock(&wl->mutex); | 406 | mutex_lock(&wl->mutex); |
407 | 407 | ||
408 | wl12xx_debug(DEBUG_IRQ, "IRQ work"); | 408 | wl1251_debug(DEBUG_IRQ, "IRQ work"); |
409 | 409 | ||
410 | if (wl->state == WL12XX_STATE_OFF) | 410 | if (wl->state == WL1251_STATE_OFF) |
411 | goto out; | 411 | goto out; |
412 | 412 | ||
413 | ret = wl12xx_ps_elp_wakeup(wl); | 413 | ret = wl1251_ps_elp_wakeup(wl); |
414 | if (ret < 0) | 414 | if (ret < 0) |
415 | goto out; | 415 | goto out; |
416 | 416 | ||
417 | wl12xx_reg_write32(wl, ACX_REG_INTERRUPT_MASK, WL1251_ACX_INTR_ALL); | 417 | wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, WL1251_ACX_INTR_ALL); |
418 | 418 | ||
419 | intr = wl12xx_reg_read32(wl, ACX_REG_INTERRUPT_CLEAR); | 419 | intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_CLEAR); |
420 | wl12xx_debug(DEBUG_IRQ, "intr: 0x%x", intr); | 420 | wl1251_debug(DEBUG_IRQ, "intr: 0x%x", intr); |
421 | 421 | ||
422 | if (wl->data_path) { | 422 | if (wl->data_path) { |
423 | wl->rx_counter = | 423 | wl->rx_counter = |
424 | wl12xx_mem_read32(wl, wl->data_path->rx_control_addr); | 424 | wl1251_mem_read32(wl, wl->data_path->rx_control_addr); |
425 | 425 | ||
426 | /* We handle a frmware bug here */ | 426 | /* We handle a frmware bug here */ |
427 | switch ((wl->rx_counter - wl->rx_handled) & 0xf) { | 427 | switch ((wl->rx_counter - wl->rx_handled) & 0xf) { |
428 | case 0: | 428 | case 0: |
429 | wl12xx_debug(DEBUG_IRQ, "RX: FW and host in sync"); | 429 | wl1251_debug(DEBUG_IRQ, "RX: FW and host in sync"); |
430 | intr &= ~WL1251_ACX_INTR_RX0_DATA; | 430 | intr &= ~WL1251_ACX_INTR_RX0_DATA; |
431 | intr &= ~WL1251_ACX_INTR_RX1_DATA; | 431 | intr &= ~WL1251_ACX_INTR_RX1_DATA; |
432 | break; | 432 | break; |
433 | case 1: | 433 | case 1: |
434 | wl12xx_debug(DEBUG_IRQ, "RX: FW +1"); | 434 | wl1251_debug(DEBUG_IRQ, "RX: FW +1"); |
435 | intr |= WL1251_ACX_INTR_RX0_DATA; | 435 | intr |= WL1251_ACX_INTR_RX0_DATA; |
436 | intr &= ~WL1251_ACX_INTR_RX1_DATA; | 436 | intr &= ~WL1251_ACX_INTR_RX1_DATA; |
437 | break; | 437 | break; |
438 | case 2: | 438 | case 2: |
439 | wl12xx_debug(DEBUG_IRQ, "RX: FW +2"); | 439 | wl1251_debug(DEBUG_IRQ, "RX: FW +2"); |
440 | intr |= WL1251_ACX_INTR_RX0_DATA; | 440 | intr |= WL1251_ACX_INTR_RX0_DATA; |
441 | intr |= WL1251_ACX_INTR_RX1_DATA; | 441 | intr |= WL1251_ACX_INTR_RX1_DATA; |
442 | break; | 442 | break; |
443 | default: | 443 | default: |
444 | wl12xx_warning("RX: FW and host out of sync: %d", | 444 | wl1251_warning("RX: FW and host out of sync: %d", |
445 | wl->rx_counter - wl->rx_handled); | 445 | wl->rx_counter - wl->rx_handled); |
446 | break; | 446 | break; |
447 | } | 447 | } |
@@ -449,49 +449,49 @@ static void wl1251_irq_work(struct work_struct *work) | |||
449 | wl->rx_handled = wl->rx_counter; | 449 | wl->rx_handled = wl->rx_counter; |
450 | 450 | ||
451 | 451 | ||
452 | wl12xx_debug(DEBUG_IRQ, "RX counter: %d", wl->rx_counter); | 452 | wl1251_debug(DEBUG_IRQ, "RX counter: %d", wl->rx_counter); |
453 | } | 453 | } |
454 | 454 | ||
455 | intr &= wl->intr_mask; | 455 | intr &= wl->intr_mask; |
456 | 456 | ||
457 | if (intr == 0) { | 457 | if (intr == 0) { |
458 | wl12xx_debug(DEBUG_IRQ, "INTR is 0"); | 458 | wl1251_debug(DEBUG_IRQ, "INTR is 0"); |
459 | wl12xx_reg_write32(wl, ACX_REG_INTERRUPT_MASK, | 459 | wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, |
460 | ~(wl->intr_mask)); | 460 | ~(wl->intr_mask)); |
461 | 461 | ||
462 | goto out_sleep; | 462 | goto out_sleep; |
463 | } | 463 | } |
464 | 464 | ||
465 | if (intr & WL1251_ACX_INTR_RX0_DATA) { | 465 | if (intr & WL1251_ACX_INTR_RX0_DATA) { |
466 | wl12xx_debug(DEBUG_IRQ, "WL1251_ACX_INTR_RX0_DATA"); | 466 | wl1251_debug(DEBUG_IRQ, "WL1251_ACX_INTR_RX0_DATA"); |
467 | wl12xx_rx(wl); | 467 | wl1251_rx(wl); |
468 | } | 468 | } |
469 | 469 | ||
470 | if (intr & WL1251_ACX_INTR_RX1_DATA) { | 470 | if (intr & WL1251_ACX_INTR_RX1_DATA) { |
471 | wl12xx_debug(DEBUG_IRQ, "WL1251_ACX_INTR_RX1_DATA"); | 471 | wl1251_debug(DEBUG_IRQ, "WL1251_ACX_INTR_RX1_DATA"); |
472 | wl12xx_rx(wl); | 472 | wl1251_rx(wl); |
473 | } | 473 | } |
474 | 474 | ||
475 | if (intr & WL1251_ACX_INTR_TX_RESULT) { | 475 | if (intr & WL1251_ACX_INTR_TX_RESULT) { |
476 | wl12xx_debug(DEBUG_IRQ, "WL1251_ACX_INTR_TX_RESULT"); | 476 | wl1251_debug(DEBUG_IRQ, "WL1251_ACX_INTR_TX_RESULT"); |
477 | wl1251_tx_complete(wl); | 477 | wl1251_tx_complete(wl); |
478 | } | 478 | } |
479 | 479 | ||
480 | if (intr & (WL1251_ACX_INTR_EVENT_A | WL1251_ACX_INTR_EVENT_B)) { | 480 | if (intr & (WL1251_ACX_INTR_EVENT_A | WL1251_ACX_INTR_EVENT_B)) { |
481 | wl12xx_debug(DEBUG_IRQ, "WL1251_ACX_INTR_EVENT (0x%x)", intr); | 481 | wl1251_debug(DEBUG_IRQ, "WL1251_ACX_INTR_EVENT (0x%x)", intr); |
482 | if (intr & WL1251_ACX_INTR_EVENT_A) | 482 | if (intr & WL1251_ACX_INTR_EVENT_A) |
483 | wl12xx_event_handle(wl, 0); | 483 | wl1251_event_handle(wl, 0); |
484 | else | 484 | else |
485 | wl12xx_event_handle(wl, 1); | 485 | wl1251_event_handle(wl, 1); |
486 | } | 486 | } |
487 | 487 | ||
488 | if (intr & WL1251_ACX_INTR_INIT_COMPLETE) | 488 | if (intr & WL1251_ACX_INTR_INIT_COMPLETE) |
489 | wl12xx_debug(DEBUG_IRQ, "WL1251_ACX_INTR_INIT_COMPLETE"); | 489 | wl1251_debug(DEBUG_IRQ, "WL1251_ACX_INTR_INIT_COMPLETE"); |
490 | 490 | ||
491 | wl12xx_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask)); | 491 | wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask)); |
492 | 492 | ||
493 | out_sleep: | 493 | out_sleep: |
494 | wl12xx_ps_elp_sleep(wl); | 494 | wl1251_ps_elp_sleep(wl); |
495 | 495 | ||
496 | out: | 496 | out: |
497 | mutex_unlock(&wl->mutex); | 497 | mutex_unlock(&wl->mutex); |
@@ -529,20 +529,20 @@ static int wl1251_hw_init_txq_fill(u8 qid, | |||
529 | (QOS_TX_LOW_VO_DEF * num_blocks) / 100; | 529 | (QOS_TX_LOW_VO_DEF * num_blocks) / 100; |
530 | break; | 530 | break; |
531 | default: | 531 | default: |
532 | wl12xx_error("Invalid TX queue id: %d", qid); | 532 | wl1251_error("Invalid TX queue id: %d", qid); |
533 | return -EINVAL; | 533 | return -EINVAL; |
534 | } | 534 | } |
535 | 535 | ||
536 | return 0; | 536 | return 0; |
537 | } | 537 | } |
538 | 538 | ||
539 | static int wl1251_hw_init_tx_queue_config(struct wl12xx *wl) | 539 | static int wl1251_hw_init_tx_queue_config(struct wl1251 *wl) |
540 | { | 540 | { |
541 | struct acx_tx_queue_qos_config *config; | 541 | struct acx_tx_queue_qos_config *config; |
542 | struct wl1251_acx_mem_map *wl_mem_map = wl->target_mem_map; | 542 | struct wl1251_acx_mem_map *wl_mem_map = wl->target_mem_map; |
543 | int ret, i; | 543 | int ret, i; |
544 | 544 | ||
545 | wl12xx_debug(DEBUG_ACX, "acx tx queue config"); | 545 | wl1251_debug(DEBUG_ACX, "acx tx queue config"); |
546 | 546 | ||
547 | config = kzalloc(sizeof(*config), GFP_KERNEL); | 547 | config = kzalloc(sizeof(*config), GFP_KERNEL); |
548 | if (!config) { | 548 | if (!config) { |
@@ -556,7 +556,7 @@ static int wl1251_hw_init_tx_queue_config(struct wl12xx *wl) | |||
556 | if (ret < 0) | 556 | if (ret < 0) |
557 | goto out; | 557 | goto out; |
558 | 558 | ||
559 | ret = wl12xx_cmd_configure(wl, ACX_TX_QUEUE_CFG, | 559 | ret = wl1251_cmd_configure(wl, ACX_TX_QUEUE_CFG, |
560 | config, sizeof(*config)); | 560 | config, sizeof(*config)); |
561 | if (ret < 0) | 561 | if (ret < 0) |
562 | goto out; | 562 | goto out; |
@@ -567,7 +567,7 @@ out: | |||
567 | return ret; | 567 | return ret; |
568 | } | 568 | } |
569 | 569 | ||
570 | static int wl1251_hw_init_data_path_config(struct wl12xx *wl) | 570 | static int wl1251_hw_init_data_path_config(struct wl1251 *wl) |
571 | { | 571 | { |
572 | int ret; | 572 | int ret; |
573 | 573 | ||
@@ -575,11 +575,11 @@ static int wl1251_hw_init_data_path_config(struct wl12xx *wl) | |||
575 | wl->data_path = kzalloc(sizeof(struct acx_data_path_params_resp), | 575 | wl->data_path = kzalloc(sizeof(struct acx_data_path_params_resp), |
576 | GFP_KERNEL); | 576 | GFP_KERNEL); |
577 | if (!wl->data_path) { | 577 | if (!wl->data_path) { |
578 | wl12xx_error("Couldnt allocate data path parameters"); | 578 | wl1251_error("Couldnt allocate data path parameters"); |
579 | return -ENOMEM; | 579 | return -ENOMEM; |
580 | } | 580 | } |
581 | 581 | ||
582 | ret = wl12xx_acx_data_path_params(wl, wl->data_path); | 582 | ret = wl1251_acx_data_path_params(wl, wl->data_path); |
583 | if (ret < 0) { | 583 | if (ret < 0) { |
584 | kfree(wl->data_path); | 584 | kfree(wl->data_path); |
585 | wl->data_path = NULL; | 585 | wl->data_path = NULL; |
@@ -589,17 +589,17 @@ static int wl1251_hw_init_data_path_config(struct wl12xx *wl) | |||
589 | return 0; | 589 | return 0; |
590 | } | 590 | } |
591 | 591 | ||
592 | static int wl1251_hw_init(struct wl12xx *wl) | 592 | static int wl1251_hw_init(struct wl1251 *wl) |
593 | { | 593 | { |
594 | struct wl1251_acx_mem_map *wl_mem_map; | 594 | struct wl1251_acx_mem_map *wl_mem_map; |
595 | int ret; | 595 | int ret; |
596 | 596 | ||
597 | ret = wl12xx_hw_init_hwenc_config(wl); | 597 | ret = wl1251_hw_init_hwenc_config(wl); |
598 | if (ret < 0) | 598 | if (ret < 0) |
599 | return ret; | 599 | return ret; |
600 | 600 | ||
601 | /* Template settings */ | 601 | /* Template settings */ |
602 | ret = wl12xx_hw_init_templates_config(wl); | 602 | ret = wl1251_hw_init_templates_config(wl); |
603 | if (ret < 0) | 603 | if (ret < 0) |
604 | return ret; | 604 | return ret; |
605 | 605 | ||
@@ -614,7 +614,7 @@ static int wl1251_hw_init(struct wl12xx *wl) | |||
614 | goto out_free_memmap; | 614 | goto out_free_memmap; |
615 | 615 | ||
616 | /* RX config */ | 616 | /* RX config */ |
617 | ret = wl12xx_hw_init_rx_config(wl, | 617 | ret = wl1251_hw_init_rx_config(wl, |
618 | RX_CFG_PROMISCUOUS | RX_CFG_TSF, | 618 | RX_CFG_PROMISCUOUS | RX_CFG_TSF, |
619 | RX_FILTER_OPTION_DEF); | 619 | RX_FILTER_OPTION_DEF); |
620 | /* RX_CONFIG_OPTION_ANY_DST_ANY_BSS, | 620 | /* RX_CONFIG_OPTION_ANY_DST_ANY_BSS, |
@@ -628,42 +628,42 @@ static int wl1251_hw_init(struct wl12xx *wl) | |||
628 | goto out_free_data_path; | 628 | goto out_free_data_path; |
629 | 629 | ||
630 | /* PHY layer config */ | 630 | /* PHY layer config */ |
631 | ret = wl12xx_hw_init_phy_config(wl); | 631 | ret = wl1251_hw_init_phy_config(wl); |
632 | if (ret < 0) | 632 | if (ret < 0) |
633 | goto out_free_data_path; | 633 | goto out_free_data_path; |
634 | 634 | ||
635 | /* Beacon filtering */ | 635 | /* Beacon filtering */ |
636 | ret = wl12xx_hw_init_beacon_filter(wl); | 636 | ret = wl1251_hw_init_beacon_filter(wl); |
637 | if (ret < 0) | 637 | if (ret < 0) |
638 | goto out_free_data_path; | 638 | goto out_free_data_path; |
639 | 639 | ||
640 | /* Bluetooth WLAN coexistence */ | 640 | /* Bluetooth WLAN coexistence */ |
641 | ret = wl12xx_hw_init_pta(wl); | 641 | ret = wl1251_hw_init_pta(wl); |
642 | if (ret < 0) | 642 | if (ret < 0) |
643 | goto out_free_data_path; | 643 | goto out_free_data_path; |
644 | 644 | ||
645 | /* Energy detection */ | 645 | /* Energy detection */ |
646 | ret = wl12xx_hw_init_energy_detection(wl); | 646 | ret = wl1251_hw_init_energy_detection(wl); |
647 | if (ret < 0) | 647 | if (ret < 0) |
648 | goto out_free_data_path; | 648 | goto out_free_data_path; |
649 | 649 | ||
650 | /* Beacons and boradcast settings */ | 650 | /* Beacons and boradcast settings */ |
651 | ret = wl12xx_hw_init_beacon_broadcast(wl); | 651 | ret = wl1251_hw_init_beacon_broadcast(wl); |
652 | if (ret < 0) | 652 | if (ret < 0) |
653 | goto out_free_data_path; | 653 | goto out_free_data_path; |
654 | 654 | ||
655 | /* Enable data path */ | 655 | /* Enable data path */ |
656 | ret = wl12xx_cmd_data_path(wl, wl->channel, 1); | 656 | ret = wl1251_cmd_data_path(wl, wl->channel, 1); |
657 | if (ret < 0) | 657 | if (ret < 0) |
658 | goto out_free_data_path; | 658 | goto out_free_data_path; |
659 | 659 | ||
660 | /* Default power state */ | 660 | /* Default power state */ |
661 | ret = wl12xx_hw_init_power_auth(wl); | 661 | ret = wl1251_hw_init_power_auth(wl); |
662 | if (ret < 0) | 662 | if (ret < 0) |
663 | goto out_free_data_path; | 663 | goto out_free_data_path; |
664 | 664 | ||
665 | wl_mem_map = wl->target_mem_map; | 665 | wl_mem_map = wl->target_mem_map; |
666 | wl12xx_info("%d tx blocks at 0x%x, %d rx blocks at 0x%x", | 666 | wl1251_info("%d tx blocks at 0x%x, %d rx blocks at 0x%x", |
667 | wl_mem_map->num_tx_mem_blocks, | 667 | wl_mem_map->num_tx_mem_blocks, |
668 | wl->data_path->tx_control_addr, | 668 | wl->data_path->tx_control_addr, |
669 | wl_mem_map->num_rx_mem_blocks, | 669 | wl_mem_map->num_rx_mem_blocks, |
@@ -680,7 +680,7 @@ static int wl1251_hw_init(struct wl12xx *wl) | |||
680 | return ret; | 680 | return ret; |
681 | } | 681 | } |
682 | 682 | ||
683 | static int wl1251_plt_init(struct wl12xx *wl) | 683 | static int wl1251_plt_init(struct wl1251 *wl) |
684 | { | 684 | { |
685 | int ret; | 685 | int ret; |
686 | 686 | ||
@@ -688,14 +688,14 @@ static int wl1251_plt_init(struct wl12xx *wl) | |||
688 | if (ret < 0) | 688 | if (ret < 0) |
689 | return ret; | 689 | return ret; |
690 | 690 | ||
691 | ret = wl12xx_cmd_data_path(wl, wl->channel, 1); | 691 | ret = wl1251_cmd_data_path(wl, wl->channel, 1); |
692 | if (ret < 0) | 692 | if (ret < 0) |
693 | return ret; | 693 | return ret; |
694 | 694 | ||
695 | return 0; | 695 | return 0; |
696 | } | 696 | } |
697 | 697 | ||
698 | void wl1251_setup(struct wl12xx *wl) | 698 | void wl1251_setup(struct wl1251 *wl) |
699 | { | 699 | { |
700 | /* FIXME: Is it better to use strncpy here or is this ok? */ | 700 | /* FIXME: Is it better to use strncpy here or is this ok? */ |
701 | wl->chip.fw_filename = WL1251_FW_NAME; | 701 | wl->chip.fw_filename = WL1251_FW_NAME; |