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path: root/drivers/net/wireless/ath9k/core.h
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Diffstat (limited to 'drivers/net/wireless/ath9k/core.h')
-rw-r--r--drivers/net/wireless/ath9k/core.h206
1 files changed, 99 insertions, 107 deletions
diff --git a/drivers/net/wireless/ath9k/core.h b/drivers/net/wireless/ath9k/core.h
index cf76b36d175..903bd4624c6 100644
--- a/drivers/net/wireless/ath9k/core.h
+++ b/drivers/net/wireless/ath9k/core.h
@@ -568,7 +568,8 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
568int ath_tx_init(struct ath_softc *sc, int nbufs); 568int ath_tx_init(struct ath_softc *sc, int nbufs);
569int ath_tx_cleanup(struct ath_softc *sc); 569int ath_tx_cleanup(struct ath_softc *sc);
570int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype); 570int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
571int ath_txq_update(struct ath_softc *sc, int qnum, struct ath9k_txq_info *q); 571int ath_txq_update(struct ath_softc *sc, int qnum,
572 struct ath9k_tx_queue_info *q);
572int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb); 573int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
573void ath_tx_tasklet(struct ath_softc *sc); 574void ath_tx_tasklet(struct ath_softc *sc);
574u32 ath_txq_depth(struct ath_softc *sc, int qnum); 575u32 ath_txq_depth(struct ath_softc *sc, int qnum);
@@ -922,132 +923,123 @@ struct ath_ht_info {
922}; 923};
923 924
924struct ath_softc { 925struct ath_softc {
925 struct ieee80211_hw *hw; /* mac80211 instance */ 926 struct ieee80211_hw *hw;
926 struct pci_dev *pdev; /* Bus handle */ 927 struct pci_dev *pdev;
927 void __iomem *mem; /* address of the device */ 928 void __iomem *mem;
928 struct tasklet_struct intr_tq; /* General tasklet */ 929 struct tasklet_struct intr_tq;
929 struct tasklet_struct bcon_tasklet; /* Beacon tasklet */ 930 struct tasklet_struct bcon_tasklet;
930 struct ath_config sc_config; /* per-instance load-time 931 struct ath_config sc_config; /* load-time parameters */
931 parameters */ 932 int sc_debug;
932 int sc_debug; /* Debug masks */ 933 struct ath_hal *sc_ah;
933 struct ath_hal *sc_ah; /* HAL Instance */ 934 struct ath_rate_softc *sc_rc; /* tx rate control support */
934 struct ath_rate_softc *sc_rc; /* tx rate control support */ 935 u32 sc_intrstatus;
935 u32 sc_intrstatus; /* HAL_STATUS */ 936 enum ath9k_opmode sc_opmode; /* current operating mode */
936 enum ath9k_opmode sc_opmode; /* current operating mode */ 937
937 938 u8 sc_invalid; /* being detached */
938 /* Properties, Config */ 939 u8 sc_beacons; /* beacons running */
939 u8 sc_invalid; /* being detached */ 940 u8 sc_scanning; /* scanning active */
940 u8 sc_beacons; /* beacons running */ 941 u8 sc_txaggr; /* enable 11n tx aggregation */
941 u8 sc_scanning; /* scanning active */ 942 u8 sc_rxaggr; /* enable 11n rx aggregation */
942 u8 sc_txaggr; /* enable 11n tx aggregation */ 943 u8 sc_update_chainmask; /* change chain mask */
943 u8 sc_rxaggr; /* enable 11n rx aggregation */ 944 u8 sc_full_reset; /* force full reset */
944 u8 sc_update_chainmask; /* change chain mask */ 945 enum wireless_mode sc_curmode; /* current phy mode */
945 u8 sc_full_reset; /* force full reset */ 946 u16 sc_curtxpow;
946 enum wireless_mode sc_curmode; /* current phy mode */ 947 u16 sc_curaid;
947 u16 sc_curtxpow; /* current tx power limit */ 948 u8 sc_curbssid[ETH_ALEN];
948 u16 sc_curaid; /* current association id */ 949 u8 sc_myaddr[ETH_ALEN];
949 u8 sc_curbssid[ETH_ALEN]; 950 enum PROT_MODE sc_protmode;
950 u8 sc_myaddr[ETH_ALEN]; 951 u8 sc_mcastantenna;
951 enum PROT_MODE sc_protmode; /* protection mode */ 952 u8 sc_txantenna; /* data tx antenna (fixed or auto) */
952 u8 sc_mcastantenna;/* Multicast antenna number */ 953 u8 sc_nbcnvaps; /* # of vaps sending beacons */
953 u8 sc_txantenna; /* data tx antenna 954 u16 sc_nvaps; /* # of active virtual ap's */
954 (fixed or auto) */ 955 struct ath_vap *sc_vaps[ATH_BCBUF];
955 u8 sc_nbcnvaps; /* # of vaps sending beacons */ 956 enum ath9k_int sc_imask;
956 u16 sc_nvaps; /* # of active virtual ap's */ 957 u8 sc_bssidmask[ETH_ALEN];
957 struct ath_vap *sc_vaps[ATH_BCBUF]; /* interface id 958 u8 sc_defant; /* current default antenna */
958 to avp map */ 959 u8 sc_rxotherant; /* rx's on non-default antenna */
959 enum ath9k_int sc_imask; /* interrupt mask copy */ 960 u16 sc_cachelsz;
960 u8 sc_bssidmask[ETH_ALEN]; 961 int sc_slotupdate; /* slot to next advance fsm */
961 u8 sc_defant; /* current default antenna */ 962 int sc_slottime;
962 u8 sc_rxotherant; /* rx's on non-default antenna*/ 963 u8 sc_noreset;
963 u16 sc_cachelsz; /* cache line size */ 964 int sc_bslot[ATH_BCBUF];
964 int sc_slotupdate; /* slot to next advance fsm */ 965 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
965 int sc_slottime; /* slot time */ 966 struct list_head node_list;
966 u8 sc_noreset; 967 struct ath_ht_info sc_ht_info;
967 int sc_bslot[ATH_BCBUF];/* beacon xmit slots */ 968 int16_t sc_noise_floor; /* signal noise floor in dBm */
968 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */ 969 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
969 struct list_head node_list; 970 u8 sc_tx_chainmask;
970 struct ath_ht_info sc_ht_info; 971 u8 sc_rx_chainmask;
971 int16_t sc_noise_floor; /* signal noise floor in dBm */ 972 u8 sc_rxchaindetect_ref;
972 enum ath9k_ht_extprotspacing sc_ht_extprotspacing; 973 u8 sc_rxchaindetect_thresh5GHz;
973 u8 sc_tx_chainmask; 974 u8 sc_rxchaindetect_thresh2GHz;
974 u8 sc_rx_chainmask; 975 u8 sc_rxchaindetect_delta5GHz;
975 u8 sc_rxchaindetect_ref; 976 u8 sc_rxchaindetect_delta2GHz;
976 u8 sc_rxchaindetect_thresh5GHz; 977 u32 sc_rtsaggrlimit; /* Chipset specific aggr limit */
977 u8 sc_rxchaindetect_thresh2GHz; 978 u32 sc_flags;
978 u8 sc_rxchaindetect_delta5GHz;
979 u8 sc_rxchaindetect_delta2GHz;
980 u32 sc_rtsaggrlimit; /* Chipset specific
981 aggr limit */
982 u32 sc_flags;
983#ifdef CONFIG_SLOW_ANT_DIV 979#ifdef CONFIG_SLOW_ANT_DIV
984 /* Slow antenna diversity */ 980 struct ath_antdiv sc_antdiv;
985 struct ath_antdiv sc_antdiv;
986#endif 981#endif
987 enum { 982 enum {
988 OK, /* no change needed */ 983 OK, /* no change needed */
989 UPDATE, /* update pending */ 984 UPDATE, /* update pending */
990 COMMIT /* beacon sent, commit change */ 985 COMMIT /* beacon sent, commit change */
991 } sc_updateslot; /* slot time update fsm */ 986 } sc_updateslot; /* slot time update fsm */
992 987
993 /* Crypto */ 988 /* Crypto */
994 u32 sc_keymax; /* size of key cache */ 989 u32 sc_keymax; /* size of key cache */
995 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */ 990 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */
996 u8 sc_splitmic; /* split TKIP MIC keys */ 991 u8 sc_splitmic; /* split TKIP MIC keys */
997 int sc_keytype; /* type of the key being used */ 992 int sc_keytype;
998 993
999 /* RX */ 994 /* RX */
1000 struct list_head sc_rxbuf; /* receive buffer */ 995 struct list_head sc_rxbuf;
1001 struct ath_descdma sc_rxdma; /* RX descriptors */ 996 struct ath_descdma sc_rxdma;
1002 int sc_rxbufsize; /* rx size based on mtu */ 997 int sc_rxbufsize; /* rx size based on mtu */
1003 u32 *sc_rxlink; /* link ptr in last RX desc */ 998 u32 *sc_rxlink; /* link ptr in last RX desc */
1004 u32 sc_rxflush; /* rx flush in progress */ 999 u32 sc_rxflush; /* rx flush in progress */
1005 u64 sc_lastrx; /* tsf of last rx'd frame */ 1000 u64 sc_lastrx; /* tsf of last rx'd frame */
1006 1001
1007 /* TX */ 1002 /* TX */
1008 struct list_head sc_txbuf; /* transmit buffer */ 1003 struct list_head sc_txbuf;
1009 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES]; 1004 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
1010 struct ath_descdma sc_txdma; /* TX descriptors */ 1005 struct ath_descdma sc_txdma;
1011 u32 sc_txqsetup; /* h/w queues setup */ 1006 u32 sc_txqsetup;
1012 u32 sc_txintrperiod;/* tx interrupt batching */ 1007 u32 sc_txintrperiod; /* tx interrupt batching */
1013 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME 1008 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
1014 AC -> h/w qnum */ 1009 u32 sc_ant_tx[8]; /* recent tx frames/antenna */
1015 u32 sc_ant_tx[8]; /* recent tx frames/antenna */
1016 1010
1017 /* Beacon */ 1011 /* Beacon */
1018 struct ath9k_txq_info sc_beacon_qi; /* adhoc only: beacon 1012 struct ath9k_tx_queue_info sc_beacon_qi;
1019 queue parameters */ 1013 struct ath_descdma sc_bdma;
1020 struct ath_descdma sc_bdma; /* beacon descriptors */ 1014 struct ath_txq *sc_cabq;
1021 struct ath_txq *sc_cabq; /* tx q for cab frames */ 1015 struct list_head sc_bbuf;
1022 struct list_head sc_bbuf; /* beacon buffers */ 1016 u32 sc_bhalq;
1023 u32 sc_bhalq; /* HAL q for outgoing beacons */ 1017 u32 sc_bmisscount;
1024 u32 sc_bmisscount; /* missed beacon transmits */ 1018 u32 ast_be_xmit; /* beacons transmitted */
1025 u32 ast_be_xmit; /* beacons transmitted */
1026 1019
1027 /* Rate */ 1020 /* Rate */
1028 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; 1021 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
1029 const struct ath9k_rate_table *sc_rates[WIRELESS_MODE_MAX]; 1022 const struct ath9k_rate_table *sc_rates[WIRELESS_MODE_MAX];
1030 const struct ath9k_rate_table *sc_currates; /* current rate table */ 1023 const struct ath9k_rate_table *sc_currates;
1031 u8 sc_rixmap[256]; /* IEEE to h/w 1024 u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */
1032 rate table ix */ 1025 u8 sc_minrateix; /* min h/w rate index */
1033 u8 sc_minrateix; /* min h/w rate index */ 1026 u8 sc_protrix; /* protection rate index */
1034 u8 sc_protrix; /* protection rate index */
1035 struct { 1027 struct {
1036 u32 rateKbps; /* transfer rate in kbs */ 1028 u32 rateKbps; /* transfer rate in kbs */
1037 u8 ieeerate; /* IEEE rate */ 1029 u8 ieeerate; /* IEEE rate */
1038 } sc_hwmap[256]; /* h/w rate ix mappings */ 1030 } sc_hwmap[256]; /* h/w rate ix mappings */
1039 1031
1040 /* Channel, Band */ 1032 /* Channel, Band */
1041 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX]; 1033 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
1042 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 1034 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1043 struct ath9k_channel sc_curchan; /* current h/w channel */ 1035 struct ath9k_channel sc_curchan;
1044 1036
1045 /* Locks */ 1037 /* Locks */
1046 spinlock_t sc_rxflushlock; /* lock of RX flush */ 1038 spinlock_t sc_rxflushlock;
1047 spinlock_t sc_rxbuflock; /* rxbuf lock */ 1039 spinlock_t sc_rxbuflock;
1048 spinlock_t sc_txbuflock; /* txbuf lock */ 1040 spinlock_t sc_txbuflock;
1049 spinlock_t sc_resetlock; 1041 spinlock_t sc_resetlock;
1050 spinlock_t node_lock; 1042 spinlock_t node_lock;
1051}; 1043};
1052 1044
1053int ath_init(u16 devid, struct ath_softc *sc); 1045int ath_init(u16 devid, struct ath_softc *sc);