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path: root/drivers/net/wireless/ath/ath9k/hw.c
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-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c498
1 files changed, 1 insertions, 497 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 0db3475487c..3157ddeab31 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc. 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 * 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any 4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 5 * purpose with or without fee is hereby granted, provided that the above
@@ -20,18 +20,12 @@
20#include "hw.h" 20#include "hw.h"
21#include "hw-ops.h" 21#include "hw-ops.h"
22#include "rc.h" 22#include "rc.h"
23#include "ar5008_initvals.h"
24#include "ar9001_initvals.h"
25#include "ar9002_initvals.h" 23#include "ar9002_initvals.h"
26#include "ar9003_initvals.h"
27 24
28#define ATH9K_CLOCK_RATE_CCK 22 25#define ATH9K_CLOCK_RATE_CCK 22
29#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 26#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
30#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 27#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
31 28
32static void ar9002_hw_attach_ops(struct ath_hw *ah);
33static void ar9003_hw_attach_ops(struct ath_hw *ah);
34
35static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 29static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
36 30
37MODULE_AUTHOR("Atheros Communications"); 31MODULE_AUTHOR("Atheros Communications");
@@ -571,296 +565,6 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
571 return 0; 565 return 0;
572} 566}
573 567
574static bool ar9002_hw_macversion_supported(u32 macversion)
575{
576 switch (macversion) {
577 case AR_SREV_VERSION_5416_PCI:
578 case AR_SREV_VERSION_5416_PCIE:
579 case AR_SREV_VERSION_9160:
580 case AR_SREV_VERSION_9100:
581 case AR_SREV_VERSION_9280:
582 case AR_SREV_VERSION_9285:
583 case AR_SREV_VERSION_9287:
584 case AR_SREV_VERSION_9271:
585 return true;
586 default:
587 break;
588 }
589 return false;
590}
591
592static bool ar9003_hw_macversion_supported(u32 macversion)
593{
594 switch (macversion) {
595 case AR_SREV_VERSION_9300:
596 return true;
597 default:
598 break;
599 }
600 return false;
601}
602
603static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
604{
605 if (AR_SREV_9271(ah)) {
606 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
607 ARRAY_SIZE(ar9271Modes_9271), 6);
608 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
609 ARRAY_SIZE(ar9271Common_9271), 2);
610 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
611 ar9271Common_normal_cck_fir_coeff_9271,
612 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
613 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
614 ar9271Common_japan_2484_cck_fir_coeff_9271,
615 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
616 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
617 ar9271Modes_9271_1_0_only,
618 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
619 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
620 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
621 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
622 ar9271Modes_high_power_tx_gain_9271,
623 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
624 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
625 ar9271Modes_normal_power_tx_gain_9271,
626 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
627 return;
628 }
629
630 if (AR_SREV_9287_11_OR_LATER(ah)) {
631 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
632 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
633 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
634 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
635 if (ah->config.pcie_clock_req)
636 INIT_INI_ARRAY(&ah->iniPcieSerdes,
637 ar9287PciePhy_clkreq_off_L1_9287_1_1,
638 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
639 else
640 INIT_INI_ARRAY(&ah->iniPcieSerdes,
641 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
642 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
643 2);
644 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
645 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
646 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
647 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
648 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
649
650 if (ah->config.pcie_clock_req)
651 INIT_INI_ARRAY(&ah->iniPcieSerdes,
652 ar9287PciePhy_clkreq_off_L1_9287_1_0,
653 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
654 else
655 INIT_INI_ARRAY(&ah->iniPcieSerdes,
656 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
657 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
658 2);
659 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
660
661
662 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
663 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
664 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
665 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
666
667 if (ah->config.pcie_clock_req) {
668 INIT_INI_ARRAY(&ah->iniPcieSerdes,
669 ar9285PciePhy_clkreq_off_L1_9285_1_2,
670 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
671 } else {
672 INIT_INI_ARRAY(&ah->iniPcieSerdes,
673 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
674 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
675 2);
676 }
677 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
678 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
679 ARRAY_SIZE(ar9285Modes_9285), 6);
680 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
681 ARRAY_SIZE(ar9285Common_9285), 2);
682
683 if (ah->config.pcie_clock_req) {
684 INIT_INI_ARRAY(&ah->iniPcieSerdes,
685 ar9285PciePhy_clkreq_off_L1_9285,
686 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
687 } else {
688 INIT_INI_ARRAY(&ah->iniPcieSerdes,
689 ar9285PciePhy_clkreq_always_on_L1_9285,
690 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
691 }
692 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
693 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
694 ARRAY_SIZE(ar9280Modes_9280_2), 6);
695 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
696 ARRAY_SIZE(ar9280Common_9280_2), 2);
697
698 if (ah->config.pcie_clock_req) {
699 INIT_INI_ARRAY(&ah->iniPcieSerdes,
700 ar9280PciePhy_clkreq_off_L1_9280,
701 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
702 } else {
703 INIT_INI_ARRAY(&ah->iniPcieSerdes,
704 ar9280PciePhy_clkreq_always_on_L1_9280,
705 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
706 }
707 INIT_INI_ARRAY(&ah->iniModesAdditional,
708 ar9280Modes_fast_clock_9280_2,
709 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
710 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
711 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
712 ARRAY_SIZE(ar9280Modes_9280), 6);
713 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
714 ARRAY_SIZE(ar9280Common_9280), 2);
715 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
716 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
717 ARRAY_SIZE(ar5416Modes_9160), 6);
718 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
719 ARRAY_SIZE(ar5416Common_9160), 2);
720 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
721 ARRAY_SIZE(ar5416Bank0_9160), 2);
722 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
723 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
724 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
725 ARRAY_SIZE(ar5416Bank1_9160), 2);
726 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
727 ARRAY_SIZE(ar5416Bank2_9160), 2);
728 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
729 ARRAY_SIZE(ar5416Bank3_9160), 3);
730 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
731 ARRAY_SIZE(ar5416Bank6_9160), 3);
732 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
733 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
734 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
735 ARRAY_SIZE(ar5416Bank7_9160), 2);
736 if (AR_SREV_9160_11(ah)) {
737 INIT_INI_ARRAY(&ah->iniAddac,
738 ar5416Addac_91601_1,
739 ARRAY_SIZE(ar5416Addac_91601_1), 2);
740 } else {
741 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
742 ARRAY_SIZE(ar5416Addac_9160), 2);
743 }
744 } else if (AR_SREV_9100_OR_LATER(ah)) {
745 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
746 ARRAY_SIZE(ar5416Modes_9100), 6);
747 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
748 ARRAY_SIZE(ar5416Common_9100), 2);
749 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
750 ARRAY_SIZE(ar5416Bank0_9100), 2);
751 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
752 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
753 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
754 ARRAY_SIZE(ar5416Bank1_9100), 2);
755 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
756 ARRAY_SIZE(ar5416Bank2_9100), 2);
757 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
758 ARRAY_SIZE(ar5416Bank3_9100), 3);
759 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
760 ARRAY_SIZE(ar5416Bank6_9100), 3);
761 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
762 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
763 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
764 ARRAY_SIZE(ar5416Bank7_9100), 2);
765 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
766 ARRAY_SIZE(ar5416Addac_9100), 2);
767 } else {
768 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
769 ARRAY_SIZE(ar5416Modes), 6);
770 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
771 ARRAY_SIZE(ar5416Common), 2);
772 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
773 ARRAY_SIZE(ar5416Bank0), 2);
774 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
775 ARRAY_SIZE(ar5416BB_RfGain), 3);
776 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
777 ARRAY_SIZE(ar5416Bank1), 2);
778 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
779 ARRAY_SIZE(ar5416Bank2), 2);
780 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
781 ARRAY_SIZE(ar5416Bank3), 3);
782 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
783 ARRAY_SIZE(ar5416Bank6), 3);
784 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
785 ARRAY_SIZE(ar5416Bank6TPC), 3);
786 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
787 ARRAY_SIZE(ar5416Bank7), 2);
788 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
789 ARRAY_SIZE(ar5416Addac), 2);
790 }
791}
792
793/* AR9003 2.0 - new INI format (pre, core, post arrays per subsystem) */
794static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
795{
796 /* mac */
797 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
798 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
799 ar9300_2p0_mac_core,
800 ARRAY_SIZE(ar9300_2p0_mac_core), 2);
801 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
802 ar9300_2p0_mac_postamble,
803 ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
804
805 /* bb */
806 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
807 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
808 ar9300_2p0_baseband_core,
809 ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
810 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
811 ar9300_2p0_baseband_postamble,
812 ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
813
814 /* radio */
815 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
816 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
817 ar9300_2p0_radio_core,
818 ARRAY_SIZE(ar9300_2p0_radio_core), 2);
819 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
820 ar9300_2p0_radio_postamble,
821 ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
822
823 /* soc */
824 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
825 ar9300_2p0_soc_preamble,
826 ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
827 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
828 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
829 ar9300_2p0_soc_postamble,
830 ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
831
832 /* rx/tx gain */
833 INIT_INI_ARRAY(&ah->iniModesRxGain,
834 ar9300Common_rx_gain_table_2p0,
835 ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
836 INIT_INI_ARRAY(&ah->iniModesTxGain,
837 ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
838 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
839 5);
840
841 /* Load PCIE SERDES settings from INI */
842
843 /* Awake Setting */
844
845 INIT_INI_ARRAY(&ah->iniPcieSerdes,
846 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
847 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
848 2);
849
850 /* Sleep Setting */
851
852 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
853 ar9300PciePhy_clkreq_enable_L1_2p0,
854 ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
855 2);
856
857 /* Fast clock modal settings */
858 INIT_INI_ARRAY(&ah->iniModesAdditional,
859 ar9300Modes_fast_clock_2p0,
860 ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
861 3);
862}
863
864static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 568static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
865{ 569{
866 if (AR_SREV_9287_11_OR_LATER(ah)) 570 if (AR_SREV_9287_11_OR_LATER(ah))
@@ -2179,140 +1883,6 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2179} 1883}
2180EXPORT_SYMBOL(ath9k_hw_setpower); 1884EXPORT_SYMBOL(ath9k_hw_setpower);
2181 1885
2182/*
2183 * Helper for ASPM support.
2184 *
2185 * Disable PLL when in L0s as well as receiver clock when in L1.
2186 * This power saving option must be enabled through the SerDes.
2187 *
2188 * Programming the SerDes must go through the same 288 bit serial shift
2189 * register as the other analog registers. Hence the 9 writes.
2190 */
2191static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
2192 int restore,
2193 int power_off)
2194{
2195 u8 i;
2196 u32 val;
2197
2198 if (ah->is_pciexpress != true)
2199 return;
2200
2201 /* Do not touch SerDes registers */
2202 if (ah->config.pcie_powersave_enable == 2)
2203 return;
2204
2205 /* Nothing to do on restore for 11N */
2206 if (!restore) {
2207 if (AR_SREV_9280_20_OR_LATER(ah)) {
2208 /*
2209 * AR9280 2.0 or later chips use SerDes values from the
2210 * initvals.h initialized depending on chipset during
2211 * __ath9k_hw_init()
2212 */
2213 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2214 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2215 INI_RA(&ah->iniPcieSerdes, i, 1));
2216 }
2217 } else if (AR_SREV_9280(ah) &&
2218 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2219 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2220 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2221
2222 /* RX shut off when elecidle is asserted */
2223 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2224 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2225 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2226
2227 /* Shut off CLKREQ active in L1 */
2228 if (ah->config.pcie_clock_req)
2229 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2230 else
2231 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2232
2233 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2234 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2235 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2236
2237 /* Load the new settings */
2238 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2239
2240 } else {
2241 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2242 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2243
2244 /* RX shut off when elecidle is asserted */
2245 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2246 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2247 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2248
2249 /*
2250 * Ignore ah->ah_config.pcie_clock_req setting for
2251 * pre-AR9280 11n
2252 */
2253 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2254
2255 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2256 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2257 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2258
2259 /* Load the new settings */
2260 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2261 }
2262
2263 udelay(1000);
2264
2265 /* set bit 19 to allow forcing of pcie core into L1 state */
2266 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2267
2268 /* Several PCIe massages to ensure proper behaviour */
2269 if (ah->config.pcie_waen) {
2270 val = ah->config.pcie_waen;
2271 if (!power_off)
2272 val &= (~AR_WA_D3_L1_DISABLE);
2273 } else {
2274 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2275 AR_SREV_9287(ah)) {
2276 val = AR9285_WA_DEFAULT;
2277 if (!power_off)
2278 val &= (~AR_WA_D3_L1_DISABLE);
2279 } else if (AR_SREV_9280(ah)) {
2280 /*
2281 * On AR9280 chips bit 22 of 0x4004 needs to be
2282 * set otherwise card may disappear.
2283 */
2284 val = AR9280_WA_DEFAULT;
2285 if (!power_off)
2286 val &= (~AR_WA_D3_L1_DISABLE);
2287 } else
2288 val = AR_WA_DEFAULT;
2289 }
2290
2291 REG_WRITE(ah, AR_WA, val);
2292 }
2293
2294 if (power_off) {
2295 /*
2296 * Set PCIe workaround bits
2297 * bit 14 in WA register (disable L1) should only
2298 * be set when device enters D3 and be cleared
2299 * when device comes back to D0.
2300 */
2301 if (ah->config.pcie_waen) {
2302 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2303 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2304 } else {
2305 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2306 AR_SREV_9287(ah)) &&
2307 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2308 (AR_SREV_9280(ah) &&
2309 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2310 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2311 }
2312 }
2313 }
2314}
2315
2316/**********************/ 1886/**********************/
2317/* Interrupt Handling */ 1887/* Interrupt Handling */
2318/**********************/ 1888/**********************/
@@ -2594,37 +2164,6 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2594} 2164}
2595EXPORT_SYMBOL(ath9k_hw_set_interrupts); 2165EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2596 2166
2597/*
2598 * Helper for ASPM support.
2599 *
2600 * Disable PLL when in L0s as well as receiver clock when in L1.
2601 * This power saving option must be enabled through the SerDes.
2602 *
2603 * Programming the SerDes must go through the same 288 bit serial shift
2604 * register as the other analog registers. Hence the 9 writes.
2605 */
2606static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
2607 int restore,
2608 int power_off)
2609{
2610 if (ah->is_pciexpress != true)
2611 return;
2612
2613 /* Do not touch SerDes registers */
2614 if (ah->config.pcie_powersave_enable == 2)
2615 return;
2616
2617 /* Nothing to do on restore for 11N */
2618 if (!restore) {
2619 /* set bit 19 to allow forcing of pcie core into L1 state */
2620 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2621
2622 /* Several PCIe massages to ensure proper behaviour */
2623 if (ah->config.pcie_waen)
2624 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2625 }
2626}
2627
2628/*******************/ 2167/*******************/
2629/* Beacon Handling */ 2168/* Beacon Handling */
2630/*******************/ 2169/*******************/
@@ -3635,38 +3174,3 @@ void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3635 hw_name[used] = '\0'; 3174 hw_name[used] = '\0';
3636} 3175}
3637EXPORT_SYMBOL(ath9k_hw_name); 3176EXPORT_SYMBOL(ath9k_hw_name);
3638
3639/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
3640static void ar9002_hw_attach_ops(struct ath_hw *ah)
3641{
3642 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
3643 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
3644
3645 priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
3646 priv_ops->macversion_supported = ar9002_hw_macversion_supported;
3647
3648 ops->config_pci_powersave = ar9002_hw_configpcipowersave;
3649
3650 ar5008_hw_attach_phy_ops(ah);
3651 if (AR_SREV_9280_10_OR_LATER(ah))
3652 ar9002_hw_attach_phy_ops(ah);
3653
3654 ar9002_hw_attach_calib_ops(ah);
3655 ar9002_hw_attach_mac_ops(ah);
3656}
3657
3658/* Sets up the AR9003 hardware familiy callbacks */
3659static void ar9003_hw_attach_ops(struct ath_hw *ah)
3660{
3661 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
3662 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
3663
3664 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
3665 priv_ops->macversion_supported = ar9003_hw_macversion_supported;
3666
3667 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
3668
3669 ar9003_hw_attach_phy_ops(ah);
3670 ar9003_hw_attach_calib_ops(ah);
3671 ar9003_hw_attach_mac_ops(ah);
3672}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 01:34:14 -0500