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-rw-r--r--drivers/net/wan/pc300.h228
1 files changed, 91 insertions, 137 deletions
diff --git a/drivers/net/wan/pc300.h b/drivers/net/wan/pc300.h
index 63e9fcf31fb..2e4f84f6cad 100644
--- a/drivers/net/wan/pc300.h
+++ b/drivers/net/wan/pc300.h
@@ -100,31 +100,14 @@
100#define _PC300_H 100#define _PC300_H
101 101
102#include <linux/hdlc.h> 102#include <linux/hdlc.h>
103#include <net/syncppp.h>
104#include "hd64572.h" 103#include "hd64572.h"
105#include "pc300-falc-lh.h" 104#include "pc300-falc-lh.h"
106 105
107#ifndef CY_TYPES 106#define PC300_PROTO_MLPPP 1
108#define CY_TYPES
109typedef __u64 ucdouble; /* 64 bits, unsigned */
110typedef __u32 uclong; /* 32 bits, unsigned */
111typedef __u16 ucshort; /* 16 bits, unsigned */
112typedef __u8 ucchar; /* 8 bits, unsigned */
113#endif /* CY_TYPES */
114 107
115#define PC300_PROTO_MLPPP 1
116
117#define PC300_KERNEL "2.4.x" /* Kernel supported by this driver */
118
119#define PC300_DEVNAME "hdlc" /* Dev. name base (for hdlc0, hdlc1, etc.) */
120#define PC300_MAXINDEX 100 /* Max dev. name index (the '0' in hdlc0) */
121
122#define PC300_MAXCARDS 4 /* Max number of cards per system */
123#define PC300_MAXCHAN 2 /* Number of channels per card */ 108#define PC300_MAXCHAN 2 /* Number of channels per card */
124 109
125#define PC300_PLX_WIN 0x80 /* PLX control window size (128b) */
126#define PC300_RAMSIZE 0x40000 /* RAM window size (256Kb) */ 110#define PC300_RAMSIZE 0x40000 /* RAM window size (256Kb) */
127#define PC300_SCASIZE 0x400 /* SCA window size (1Kb) */
128#define PC300_FALCSIZE 0x400 /* FALC window size (1Kb) */ 111#define PC300_FALCSIZE 0x400 /* FALC window size (1Kb) */
129 112
130#define PC300_OSC_CLOCK 24576000 113#define PC300_OSC_CLOCK 24576000
@@ -160,26 +143,14 @@ typedef __u8 ucchar; /* 8 bits, unsigned */
160 * Memory access functions/macros * 143 * Memory access functions/macros *
161 * (required to support Alpha systems) * 144 * (required to support Alpha systems) *
162 ***************************************/ 145 ***************************************/
163#ifdef __KERNEL__ 146#define cpc_writeb(port,val) {writeb((u8)(val),(port)); mb();}
164#define cpc_writeb(port,val) {writeb((ucchar)(val),(port)); mb();}
165#define cpc_writew(port,val) {writew((ushort)(val),(port)); mb();} 147#define cpc_writew(port,val) {writew((ushort)(val),(port)); mb();}
166#define cpc_writel(port,val) {writel((uclong)(val),(port)); mb();} 148#define cpc_writel(port,val) {writel((u32)(val),(port)); mb();}
167 149
168#define cpc_readb(port) readb(port) 150#define cpc_readb(port) readb(port)
169#define cpc_readw(port) readw(port) 151#define cpc_readw(port) readw(port)
170#define cpc_readl(port) readl(port) 152#define cpc_readl(port) readl(port)
171 153
172#else /* __KERNEL__ */
173#define cpc_writeb(port,val) (*(volatile ucchar *)(port) = (ucchar)(val))
174#define cpc_writew(port,val) (*(volatile ucshort *)(port) = (ucshort)(val))
175#define cpc_writel(port,val) (*(volatile uclong *)(port) = (uclong)(val))
176
177#define cpc_readb(port) (*(volatile ucchar *)(port))
178#define cpc_readw(port) (*(volatile ucshort *)(port))
179#define cpc_readl(port) (*(volatile uclong *)(port))
180
181#endif /* __KERNEL__ */
182
183/****** Data Structures *****************************************************/ 154/****** Data Structures *****************************************************/
184 155
185/* 156/*
@@ -188,15 +159,15 @@ typedef __u8 ucchar; /* 8 bits, unsigned */
188 * (memory mapped). 159 * (memory mapped).
189 */ 160 */
190struct RUNTIME_9050 { 161struct RUNTIME_9050 {
191 uclong loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */ 162 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
192 uclong loc_rom_range; /* 10h : Local ROM Range */ 163 u32 loc_rom_range; /* 10h : Local ROM Range */
193 uclong loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */ 164 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
194 uclong loc_rom_base; /* 24h : Local ROM Base */ 165 u32 loc_rom_base; /* 24h : Local ROM Base */
195 uclong loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */ 166 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
196 uclong rom_bus_descr; /* 38h : ROM Bus Descriptor */ 167 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
197 uclong cs_base[4]; /* 3C-48h : Chip Select Base Addrs */ 168 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
198 uclong intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */ 169 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
199 uclong init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */ 170 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
200}; 171};
201 172
202#define PLX_9050_LINT1_ENABLE 0x01 173#define PLX_9050_LINT1_ENABLE 0x01
@@ -240,66 +211,66 @@ struct RUNTIME_9050 {
240#define PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */ 211#define PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */
241 212
242typedef struct falc { 213typedef struct falc {
243 ucchar sync; /* If true FALC is synchronized */ 214 u8 sync; /* If true FALC is synchronized */
244 ucchar active; /* if TRUE then already active */ 215 u8 active; /* if TRUE then already active */
245 ucchar loop_active; /* if TRUE a line loopback UP was received */ 216 u8 loop_active; /* if TRUE a line loopback UP was received */
246 ucchar loop_gen; /* if TRUE a line loopback UP was issued */ 217 u8 loop_gen; /* if TRUE a line loopback UP was issued */
247 218
248 ucchar num_channels; 219 u8 num_channels;
249 ucchar offset; /* 1 for T1, 0 for E1 */ 220 u8 offset; /* 1 for T1, 0 for E1 */
250 ucchar full_bandwidth; 221 u8 full_bandwidth;
251 222
252 ucchar xmb_cause; 223 u8 xmb_cause;
253 ucchar multiframe_mode; 224 u8 multiframe_mode;
254 225
255 /* Statistics */ 226 /* Statistics */
256 ucshort pden; /* Pulse Density violation count */ 227 u16 pden; /* Pulse Density violation count */
257 ucshort los; /* Loss of Signal count */ 228 u16 los; /* Loss of Signal count */
258 ucshort losr; /* Loss of Signal recovery count */ 229 u16 losr; /* Loss of Signal recovery count */
259 ucshort lfa; /* Loss of frame alignment count */ 230 u16 lfa; /* Loss of frame alignment count */
260 ucshort farec; /* Frame Alignment Recovery count */ 231 u16 farec; /* Frame Alignment Recovery count */
261 ucshort lmfa; /* Loss of multiframe alignment count */ 232 u16 lmfa; /* Loss of multiframe alignment count */
262 ucshort ais; /* Remote Alarm indication Signal count */ 233 u16 ais; /* Remote Alarm indication Signal count */
263 ucshort sec; /* One-second timer */ 234 u16 sec; /* One-second timer */
264 ucshort es; /* Errored second */ 235 u16 es; /* Errored second */
265 ucshort rai; /* remote alarm received */ 236 u16 rai; /* remote alarm received */
266 ucshort bec; 237 u16 bec;
267 ucshort fec; 238 u16 fec;
268 ucshort cvc; 239 u16 cvc;
269 ucshort cec; 240 u16 cec;
270 ucshort ebc; 241 u16 ebc;
271 242
272 /* Status */ 243 /* Status */
273 ucchar red_alarm; 244 u8 red_alarm;
274 ucchar blue_alarm; 245 u8 blue_alarm;
275 ucchar loss_fa; 246 u8 loss_fa;
276 ucchar yellow_alarm; 247 u8 yellow_alarm;
277 ucchar loss_mfa; 248 u8 loss_mfa;
278 ucchar prbs; 249 u8 prbs;
279} falc_t; 250} falc_t;
280 251
281typedef struct falc_status { 252typedef struct falc_status {
282 ucchar sync; /* If true FALC is synchronized */ 253 u8 sync; /* If true FALC is synchronized */
283 ucchar red_alarm; 254 u8 red_alarm;
284 ucchar blue_alarm; 255 u8 blue_alarm;
285 ucchar loss_fa; 256 u8 loss_fa;
286 ucchar yellow_alarm; 257 u8 yellow_alarm;
287 ucchar loss_mfa; 258 u8 loss_mfa;
288 ucchar prbs; 259 u8 prbs;
289} falc_status_t; 260} falc_status_t;
290 261
291typedef struct rsv_x21_status { 262typedef struct rsv_x21_status {
292 ucchar dcd; 263 u8 dcd;
293 ucchar dsr; 264 u8 dsr;
294 ucchar cts; 265 u8 cts;
295 ucchar rts; 266 u8 rts;
296 ucchar dtr; 267 u8 dtr;
297} rsv_x21_status_t; 268} rsv_x21_status_t;
298 269
299typedef struct pc300stats { 270typedef struct pc300stats {
300 int hw_type; 271 int hw_type;
301 uclong line_on; 272 u32 line_on;
302 uclong line_off; 273 u32 line_off;
303 struct net_device_stats gen_stats; 274 struct net_device_stats gen_stats;
304 falc_t te_stats; 275 falc_t te_stats;
305} pc300stats_t; 276} pc300stats_t;
@@ -317,28 +288,19 @@ typedef struct pc300loopback {
317 288
318typedef struct pc300patterntst { 289typedef struct pc300patterntst {
319 char patrntst_on; /* 0 - off; 1 - on; 2 - read num_errors */ 290 char patrntst_on; /* 0 - off; 1 - on; 2 - read num_errors */
320 ucshort num_errors; 291 u16 num_errors;
321} pc300patterntst_t; 292} pc300patterntst_t;
322 293
323typedef struct pc300dev { 294typedef struct pc300dev {
324 void *if_ptr; /* General purpose pointer */
325 struct pc300ch *chan; 295 struct pc300ch *chan;
326 ucchar trace_on; 296 u8 trace_on;
327 uclong line_on; /* DCD(X.21, RSV) / sync(TE) change counters */ 297 u32 line_on; /* DCD(X.21, RSV) / sync(TE) change counters */
328 uclong line_off; 298 u32 line_off;
329#ifdef __KERNEL__
330 char name[16]; 299 char name[16];
331 struct net_device *dev; 300 struct net_device *dev;
332
333 void *private;
334 struct sk_buff *tx_skb;
335 union { /* This union has all the protocol-specific structures */
336 struct ppp_device pppdev;
337 }ifu;
338#ifdef CONFIG_PC300_MLPPP 301#ifdef CONFIG_PC300_MLPPP
339 void *cpc_tty; /* information to PC300 TTY driver */ 302 void *cpc_tty; /* information to PC300 TTY driver */
340#endif 303#endif
341#endif /* __KERNEL__ */
342}pc300dev_t; 304}pc300dev_t;
343 305
344typedef struct pc300hw { 306typedef struct pc300hw {
@@ -346,43 +308,42 @@ typedef struct pc300hw {
346 int bus; /* Bus (PCI, PMC, etc.) */ 308 int bus; /* Bus (PCI, PMC, etc.) */
347 int nchan; /* number of channels */ 309 int nchan; /* number of channels */
348 int irq; /* interrupt request level */ 310 int irq; /* interrupt request level */
349 uclong clock; /* Board clock */ 311 u32 clock; /* Board clock */
350 ucchar cpld_id; /* CPLD ID (TE only) */ 312 u8 cpld_id; /* CPLD ID (TE only) */
351 ucshort cpld_reg1; /* CPLD reg 1 (TE only) */ 313 u16 cpld_reg1; /* CPLD reg 1 (TE only) */
352 ucshort cpld_reg2; /* CPLD reg 2 (TE only) */ 314 u16 cpld_reg2; /* CPLD reg 2 (TE only) */
353 ucshort gpioc_reg; /* PLX GPIOC reg */ 315 u16 gpioc_reg; /* PLX GPIOC reg */
354 ucshort intctl_reg; /* PLX Int Ctrl/Status reg */ 316 u16 intctl_reg; /* PLX Int Ctrl/Status reg */
355 uclong iophys; /* PLX registers I/O base */ 317 u32 iophys; /* PLX registers I/O base */
356 uclong iosize; /* PLX registers I/O size */ 318 u32 iosize; /* PLX registers I/O size */
357 uclong plxphys; /* PLX registers MMIO base (physical) */ 319 u32 plxphys; /* PLX registers MMIO base (physical) */
358 void __iomem * plxbase; /* PLX registers MMIO base (virtual) */ 320 void __iomem * plxbase; /* PLX registers MMIO base (virtual) */
359 uclong plxsize; /* PLX registers MMIO size */ 321 u32 plxsize; /* PLX registers MMIO size */
360 uclong scaphys; /* SCA registers MMIO base (physical) */ 322 u32 scaphys; /* SCA registers MMIO base (physical) */
361 void __iomem * scabase; /* SCA registers MMIO base (virtual) */ 323 void __iomem * scabase; /* SCA registers MMIO base (virtual) */
362 uclong scasize; /* SCA registers MMIO size */ 324 u32 scasize; /* SCA registers MMIO size */
363 uclong ramphys; /* On-board RAM MMIO base (physical) */ 325 u32 ramphys; /* On-board RAM MMIO base (physical) */
364 void __iomem * rambase; /* On-board RAM MMIO base (virtual) */ 326 void __iomem * rambase; /* On-board RAM MMIO base (virtual) */
365 uclong alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */ 327 u32 alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */
366 uclong ramsize; /* On-board RAM MMIO size */ 328 u32 ramsize; /* On-board RAM MMIO size */
367 uclong falcphys; /* FALC registers MMIO base (physical) */ 329 u32 falcphys; /* FALC registers MMIO base (physical) */
368 void __iomem * falcbase;/* FALC registers MMIO base (virtual) */ 330 void __iomem * falcbase;/* FALC registers MMIO base (virtual) */
369 uclong falcsize; /* FALC registers MMIO size */ 331 u32 falcsize; /* FALC registers MMIO size */
370} pc300hw_t; 332} pc300hw_t;
371 333
372typedef struct pc300chconf { 334typedef struct pc300chconf {
373 sync_serial_settings phys_settings; /* Clock type/rate (in bps), 335 sync_serial_settings phys_settings; /* Clock type/rate (in bps),
374 loopback mode */ 336 loopback mode */
375 raw_hdlc_proto proto_settings; /* Encoding, parity (CRC) */ 337 raw_hdlc_proto proto_settings; /* Encoding, parity (CRC) */
376 uclong media; /* HW media (RS232, V.35, etc.) */ 338 u32 media; /* HW media (RS232, V.35, etc.) */
377 uclong proto; /* Protocol (PPP, X.25, etc.) */ 339 u32 proto; /* Protocol (PPP, X.25, etc.) */
378 ucchar monitor; /* Monitor mode (0 = off, !0 = on) */
379 340
380 /* TE-specific parameters */ 341 /* TE-specific parameters */
381 ucchar lcode; /* Line Code (AMI, B8ZS, etc.) */ 342 u8 lcode; /* Line Code (AMI, B8ZS, etc.) */
382 ucchar fr_mode; /* Frame Mode (ESF, D4, etc.) */ 343 u8 fr_mode; /* Frame Mode (ESF, D4, etc.) */
383 ucchar lbo; /* Line Build Out */ 344 u8 lbo; /* Line Build Out */
384 ucchar rx_sens; /* Rx Sensitivity (long- or short-haul) */ 345 u8 rx_sens; /* Rx Sensitivity (long- or short-haul) */
385 uclong tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */ 346 u32 tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */
386} pc300chconf_t; 347} pc300chconf_t;
387 348
388typedef struct pc300ch { 349typedef struct pc300ch {
@@ -390,20 +351,18 @@ typedef struct pc300ch {
390 int channel; 351 int channel;
391 pc300dev_t d; 352 pc300dev_t d;
392 pc300chconf_t conf; 353 pc300chconf_t conf;
393 ucchar tx_first_bd; /* First TX DMA block descr. w/ data */ 354 u8 tx_first_bd; /* First TX DMA block descr. w/ data */
394 ucchar tx_next_bd; /* Next free TX DMA block descriptor */ 355 u8 tx_next_bd; /* Next free TX DMA block descriptor */
395 ucchar rx_first_bd; /* First free RX DMA block descriptor */ 356 u8 rx_first_bd; /* First free RX DMA block descriptor */
396 ucchar rx_last_bd; /* Last free RX DMA block descriptor */ 357 u8 rx_last_bd; /* Last free RX DMA block descriptor */
397 ucchar nfree_tx_bd; /* Number of free TX DMA block descriptors */ 358 u8 nfree_tx_bd; /* Number of free TX DMA block descriptors */
398 falc_t falc; /* FALC structure (TE only) */ 359 falc_t falc; /* FALC structure (TE only) */
399} pc300ch_t; 360} pc300ch_t;
400 361
401typedef struct pc300 { 362typedef struct pc300 {
402 pc300hw_t hw; /* hardware config. */ 363 pc300hw_t hw; /* hardware config. */
403 pc300ch_t chan[PC300_MAXCHAN]; 364 pc300ch_t chan[PC300_MAXCHAN];
404#ifdef __KERNEL__
405 spinlock_t card_lock; 365 spinlock_t card_lock;
406#endif /* __KERNEL__ */
407} pc300_t; 366} pc300_t;
408 367
409typedef struct pc300conf { 368typedef struct pc300conf {
@@ -471,12 +430,7 @@ enum pc300_loopback_cmds {
471#define PC300_TX_QUEUE_LEN 100 430#define PC300_TX_QUEUE_LEN 100
472#define PC300_DEF_MTU 1600 431#define PC300_DEF_MTU 1600
473 432
474#ifdef __KERNEL__
475/* Function Prototypes */ 433/* Function Prototypes */
476void tx_dma_start(pc300_t *, int);
477int cpc_open(struct net_device *dev); 434int cpc_open(struct net_device *dev);
478int cpc_set_media(hdlc_device *, int);
479#endif /* __KERNEL__ */
480 435
481#endif /* _PC300_H */ 436#endif /* _PC300_H */
482