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Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r--drivers/net/tg3.h21
1 files changed, 14 insertions, 7 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index ff0faab94bd..8209da5dd15 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2074,12 +2074,22 @@ struct tg3 {
2074 2074
2075 /* SMP locking strategy: 2075 /* SMP locking strategy:
2076 * 2076 *
2077 * lock: Held during all operations except TX packet 2077 * lock: Held during reset, PHY access, timer, and when
2078 * processing. 2078 * updating tg3_flags and tg3_flags2.
2079 * 2079 *
2080 * tx_lock: Held during tg3_start_xmit and tg3_tx 2080 * tx_lock: Held during tg3_start_xmit and tg3_tx only
2081 * when calling netif_[start|stop]_queue.
2082 * tg3_start_xmit is protected by netif_tx_lock.
2081 * 2083 *
2082 * Both of these locks are to be held with BH safety. 2084 * Both of these locks are to be held with BH safety.
2085 *
2086 * Because the IRQ handler, tg3_poll, and tg3_start_xmit
2087 * are running lockless, it is necessary to completely
2088 * quiesce the chip with tg3_netif_stop and tg3_full_lock
2089 * before reconfiguring the device.
2090 *
2091 * indirect_lock: Held when accessing registers indirectly
2092 * with IRQ disabling.
2083 */ 2093 */
2084 spinlock_t lock; 2094 spinlock_t lock;
2085 spinlock_t indirect_lock; 2095 spinlock_t indirect_lock;
@@ -2155,11 +2165,7 @@ struct tg3 {
2155#define TG3_FLAG_ENABLE_ASF 0x00000020 2165#define TG3_FLAG_ENABLE_ASF 0x00000020
2156#define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040 2166#define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040
2157#define TG3_FLAG_POLL_SERDES 0x00000080 2167#define TG3_FLAG_POLL_SERDES 0x00000080
2158#if defined(CONFIG_X86)
2159#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 2168#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
2160#else
2161#define TG3_FLAG_MBOX_WRITE_REORDER 0 /* disables code too */
2162#endif
2163#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 2169#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
2164#define TG3_FLAG_WOL_SPEED_100MB 0x00000400 2170#define TG3_FLAG_WOL_SPEED_100MB 0x00000400
2165#define TG3_FLAG_WOL_ENABLE 0x00000800 2171#define TG3_FLAG_WOL_ENABLE 0x00000800
@@ -2172,6 +2178,7 @@ struct tg3 {
2172#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000 2178#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
2173#define TG3_FLAG_PCI_32BIT 0x00080000 2179#define TG3_FLAG_PCI_32BIT 0x00080000
2174#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000 2180#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
2181#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
2175#define TG3_FLAG_SERDES_WOL_CAP 0x00400000 2182#define TG3_FLAG_SERDES_WOL_CAP 0x00400000
2176#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000 2183#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
2177#define TG3_FLAG_10_100_ONLY 0x01000000 2184#define TG3_FLAG_10_100_ONLY 0x01000000