diff options
Diffstat (limited to 'drivers/net/igb')
-rw-r--r-- | drivers/net/igb/e1000_82575.h | 16 | ||||
-rw-r--r-- | drivers/net/igb/e1000_defines.h | 113 | ||||
-rw-r--r-- | drivers/net/igb/e1000_mac.h | 5 | ||||
-rw-r--r-- | drivers/net/igb/e1000_phy.c | 3 | ||||
-rw-r--r-- | drivers/net/igb/e1000_regs.h | 14 | ||||
-rw-r--r-- | drivers/net/igb/igb.h | 17 | ||||
-rw-r--r-- | drivers/net/igb/igb_ethtool.c | 6 | ||||
-rw-r--r-- | drivers/net/igb/igb_main.c | 12 |
8 files changed, 11 insertions, 175 deletions
diff --git a/drivers/net/igb/e1000_82575.h b/drivers/net/igb/e1000_82575.h index e613d5a606d..49b41c92a8c 100644 --- a/drivers/net/igb/e1000_82575.h +++ b/drivers/net/igb/e1000_82575.h | |||
@@ -58,9 +58,6 @@ extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); | |||
58 | E1000_EICR_RX_QUEUE2 | \ | 58 | E1000_EICR_RX_QUEUE2 | \ |
59 | E1000_EICR_RX_QUEUE3) | 59 | E1000_EICR_RX_QUEUE3) |
60 | 60 | ||
61 | #define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE | ||
62 | #define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE | ||
63 | |||
64 | /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ | 61 | /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ |
65 | 62 | ||
66 | /* Receive Descriptor - Advanced */ | 63 | /* Receive Descriptor - Advanced */ |
@@ -95,12 +92,6 @@ union e1000_adv_rx_desc { | |||
95 | #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 | 92 | #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 |
96 | #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 | 93 | #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 |
97 | 94 | ||
98 | /* RSS Hash results */ | ||
99 | |||
100 | /* RSS Packet Types as indicated in the receive descriptor */ | ||
101 | #define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */ | ||
102 | #define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ | ||
103 | |||
104 | /* Transmit Descriptor - Advanced */ | 95 | /* Transmit Descriptor - Advanced */ |
105 | union e1000_adv_tx_desc { | 96 | union e1000_adv_tx_desc { |
106 | struct { | 97 | struct { |
@@ -150,11 +141,8 @@ struct e1000_adv_tx_context_desc { | |||
150 | #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ | 141 | #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ |
151 | 142 | ||
152 | /* Direct Cache Access (DCA) definitions */ | 143 | /* Direct Cache Access (DCA) definitions */ |
153 | #define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ | 144 | #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */ |
154 | #define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ | 145 | #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ |
155 | |||
156 | #define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ | ||
157 | #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ | ||
158 | 146 | ||
159 | #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ | 147 | #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ |
160 | #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ | 148 | #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ |
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h index 79168eeaaa0..5a32a7004e0 100644 --- a/drivers/net/igb/e1000_defines.h +++ b/drivers/net/igb/e1000_defines.h | |||
@@ -42,33 +42,9 @@ | |||
42 | #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ | 42 | #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ |
43 | #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ | 43 | #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ |
44 | #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ | 44 | #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ |
45 | #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ | ||
46 | #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ | ||
47 | #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ | ||
48 | #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ | ||
49 | #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ | ||
50 | #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ | ||
51 | #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ | ||
52 | #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ | ||
53 | |||
54 | /* Wake Up Status */ | ||
55 | |||
56 | /* Wake Up Packet Length */ | ||
57 | |||
58 | /* Four Flexible Filters are supported */ | ||
59 | #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 | ||
60 | |||
61 | /* Each Flexible Filter is at most 128 (0x80) bytes in length */ | ||
62 | #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 | ||
63 | |||
64 | 45 | ||
65 | /* Extended Device Control */ | 46 | /* Extended Device Control */ |
66 | #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ | ||
67 | #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ | ||
68 | #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ | ||
69 | #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ | 47 | #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ |
70 | #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ | ||
71 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ | ||
72 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 | 48 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
73 | #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 | 49 | #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 |
74 | #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 | 50 | #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 |
@@ -103,14 +79,7 @@ | |||
103 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ | 79 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ |
104 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ | 80 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ |
105 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ | 81 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ |
106 | #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ | ||
107 | #define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */ | 82 | #define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */ |
108 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ | ||
109 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ | ||
110 | #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ | ||
111 | #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ | ||
112 | #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ | ||
113 | #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ | ||
114 | 83 | ||
115 | #define E1000_RXDEXT_STATERR_CE 0x01000000 | 84 | #define E1000_RXDEXT_STATERR_CE 0x01000000 |
116 | #define E1000_RXDEXT_STATERR_SE 0x02000000 | 85 | #define E1000_RXDEXT_STATERR_SE 0x02000000 |
@@ -120,14 +89,6 @@ | |||
120 | #define E1000_RXDEXT_STATERR_IPE 0x40000000 | 89 | #define E1000_RXDEXT_STATERR_IPE 0x40000000 |
121 | #define E1000_RXDEXT_STATERR_RXE 0x80000000 | 90 | #define E1000_RXDEXT_STATERR_RXE 0x80000000 |
122 | 91 | ||
123 | /* mask to determine if packets should be dropped due to frame errors */ | ||
124 | #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ | ||
125 | E1000_RXD_ERR_CE | \ | ||
126 | E1000_RXD_ERR_SE | \ | ||
127 | E1000_RXD_ERR_SEQ | \ | ||
128 | E1000_RXD_ERR_CXE | \ | ||
129 | E1000_RXD_ERR_RXE) | ||
130 | |||
131 | /* Same mask, but for extended and packet split descriptors */ | 92 | /* Same mask, but for extended and packet split descriptors */ |
132 | #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ | 93 | #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ |
133 | E1000_RXDEXT_STATERR_CE | \ | 94 | E1000_RXDEXT_STATERR_CE | \ |
@@ -146,16 +107,11 @@ | |||
146 | /* Management Control */ | 107 | /* Management Control */ |
147 | #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ | 108 | #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ |
148 | #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ | 109 | #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ |
149 | #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ | ||
150 | /* Enable Neighbor Discovery Filtering */ | 110 | /* Enable Neighbor Discovery Filtering */ |
151 | #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ | 111 | #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ |
152 | #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ | 112 | #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ |
153 | /* Enable MAC address filtering */ | 113 | /* Enable MAC address filtering */ |
154 | #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 | 114 | #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 |
155 | /* Enable MNG packets to host memory */ | ||
156 | #define E1000_MANC_EN_MNG2HOST 0x00200000 | ||
157 | /* Enable IP address filtering */ | ||
158 | |||
159 | 115 | ||
160 | /* Receive Control */ | 116 | /* Receive Control */ |
161 | #define E1000_RCTL_EN 0x00000002 /* enable */ | 117 | #define E1000_RCTL_EN 0x00000002 /* enable */ |
@@ -163,14 +119,11 @@ | |||
163 | #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ | 119 | #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ |
164 | #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ | 120 | #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ |
165 | #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ | 121 | #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ |
166 | #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ | ||
167 | #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ | 122 | #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ |
168 | #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ | 123 | #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ |
169 | #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ | 124 | #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ |
170 | #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ | 125 | #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ |
171 | #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ | 126 | #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ |
172 | #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ | ||
173 | #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ | ||
174 | #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ | 127 | #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ |
175 | #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ | 128 | #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ |
176 | #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ | 129 | #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ |
@@ -227,11 +180,7 @@ | |||
227 | /* enable link status from external LINK_0 and LINK_1 pins */ | 180 | /* enable link status from external LINK_0 and LINK_1 pins */ |
228 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ | 181 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ |
229 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ | 182 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ |
230 | #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ | ||
231 | #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ | ||
232 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ | 183 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ |
233 | #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ | ||
234 | #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ | ||
235 | #define E1000_CTRL_RST 0x04000000 /* Global reset */ | 184 | #define E1000_CTRL_RST 0x04000000 /* Global reset */ |
236 | #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ | 185 | #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ |
237 | #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ | 186 | #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ |
@@ -309,9 +258,7 @@ | |||
309 | #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX | 258 | #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX |
310 | 259 | ||
311 | /* LED Control */ | 260 | /* LED Control */ |
312 | #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F | ||
313 | #define E1000_LEDCTL_LED0_MODE_SHIFT 0 | 261 | #define E1000_LEDCTL_LED0_MODE_SHIFT 0 |
314 | #define E1000_LEDCTL_LED0_IVRT 0x00000040 | ||
315 | #define E1000_LEDCTL_LED0_BLINK 0x00000080 | 262 | #define E1000_LEDCTL_LED0_BLINK 0x00000080 |
316 | 263 | ||
317 | #define E1000_LEDCTL_MODE_LED_ON 0xE | 264 | #define E1000_LEDCTL_MODE_LED_ON 0xE |
@@ -358,12 +305,7 @@ | |||
358 | 305 | ||
359 | #define MAX_JUMBO_FRAME_SIZE 0x3F00 | 306 | #define MAX_JUMBO_FRAME_SIZE 0x3F00 |
360 | 307 | ||
361 | /* Extended Configuration Control and Size */ | ||
362 | #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 | ||
363 | |||
364 | /* PBA constants */ | 308 | /* PBA constants */ |
365 | #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ | ||
366 | #define E1000_PBA_24K 0x0018 | ||
367 | #define E1000_PBA_34K 0x0022 | 309 | #define E1000_PBA_34K 0x0022 |
368 | #define E1000_PBA_64K 0x0040 /* 64KB */ | 310 | #define E1000_PBA_64K 0x0040 /* 64KB */ |
369 | 311 | ||
@@ -379,41 +321,13 @@ | |||
379 | 321 | ||
380 | /* Interrupt Cause Read */ | 322 | /* Interrupt Cause Read */ |
381 | #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ | 323 | #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ |
382 | #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ | ||
383 | #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ | 324 | #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ |
384 | #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ | 325 | #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ |
385 | #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ | 326 | #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ |
386 | #define E1000_ICR_RXO 0x00000040 /* rx overrun */ | ||
387 | #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ | 327 | #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ |
388 | #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ | ||
389 | #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ | ||
390 | #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ | ||
391 | #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ | ||
392 | #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ | ||
393 | #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ | ||
394 | #define E1000_ICR_TXD_LOW 0x00008000 | ||
395 | #define E1000_ICR_SRPD 0x00010000 | ||
396 | #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ | ||
397 | #define E1000_ICR_MNG 0x00040000 /* Manageability event */ | ||
398 | #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ | ||
399 | /* If this bit asserted, the driver should claim the interrupt */ | 328 | /* If this bit asserted, the driver should claim the interrupt */ |
400 | #define E1000_ICR_INT_ASSERTED 0x80000000 | 329 | #define E1000_ICR_INT_ASSERTED 0x80000000 |
401 | /* queue 0 Rx descriptor FIFO parity error */ | ||
402 | #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 | ||
403 | /* queue 0 Tx descriptor FIFO parity error */ | ||
404 | #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 | ||
405 | /* host arb read buffer parity error */ | ||
406 | #define E1000_ICR_HOST_ARB_PAR 0x00400000 | ||
407 | #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ | ||
408 | /* queue 1 Rx descriptor FIFO parity error */ | ||
409 | #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 | ||
410 | /* queue 1 Tx descriptor FIFO parity error */ | ||
411 | #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 | ||
412 | /* FW changed the status of DISSW bit in the FWSM */ | ||
413 | #define E1000_ICR_DSW 0x00000020 | ||
414 | /* LAN connected device generates an interrupt */ | 330 | /* LAN connected device generates an interrupt */ |
415 | #define E1000_ICR_PHYINT 0x00001000 | ||
416 | #define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ | ||
417 | #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ | 331 | #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ |
418 | 332 | ||
419 | /* Extended Interrupt Cause Read */ | 333 | /* Extended Interrupt Cause Read */ |
@@ -425,7 +339,6 @@ | |||
425 | #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ | 339 | #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ |
426 | #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ | 340 | #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ |
427 | #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ | 341 | #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ |
428 | #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ | ||
429 | #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ | 342 | #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ |
430 | /* TCP Timer */ | 343 | /* TCP Timer */ |
431 | 344 | ||
@@ -455,13 +368,11 @@ | |||
455 | #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ | 368 | #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ |
456 | 369 | ||
457 | /* Extended Interrupt Mask Set */ | 370 | /* Extended Interrupt Mask Set */ |
458 | #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ | ||
459 | #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ | 371 | #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ |
460 | 372 | ||
461 | /* Interrupt Cause Set */ | 373 | /* Interrupt Cause Set */ |
462 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ | 374 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ |
463 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | 375 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ |
464 | #define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ | ||
465 | 376 | ||
466 | /* Extended Interrupt Cause Set */ | 377 | /* Extended Interrupt Cause Set */ |
467 | 378 | ||
@@ -497,7 +408,6 @@ | |||
497 | #define E1000_ERR_MAC_INIT 5 | 408 | #define E1000_ERR_MAC_INIT 5 |
498 | #define E1000_ERR_RESET 9 | 409 | #define E1000_ERR_RESET 9 |
499 | #define E1000_ERR_MASTER_REQUESTS_PENDING 10 | 410 | #define E1000_ERR_MASTER_REQUESTS_PENDING 10 |
500 | #define E1000_ERR_HOST_INTERFACE_COMMAND 11 | ||
501 | #define E1000_BLK_PHY_RESET 12 | 411 | #define E1000_BLK_PHY_RESET 12 |
502 | #define E1000_ERR_SWFW_SYNC 13 | 412 | #define E1000_ERR_SWFW_SYNC 13 |
503 | #define E1000_NOT_IMPLEMENTED 14 | 413 | #define E1000_NOT_IMPLEMENTED 14 |
@@ -517,30 +427,9 @@ | |||
517 | /* Flow Control */ | 427 | /* Flow Control */ |
518 | #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ | 428 | #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ |
519 | 429 | ||
520 | /* Transmit Configuration Word */ | ||
521 | #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ | ||
522 | |||
523 | /* Receive Configuration Word */ | ||
524 | |||
525 | /* PCI Express Control */ | ||
526 | #define E1000_GCR_RXD_NO_SNOOP 0x00000001 | ||
527 | #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 | ||
528 | #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 | ||
529 | #define E1000_GCR_TXD_NO_SNOOP 0x00000008 | ||
530 | #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 | ||
531 | #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 | ||
532 | |||
533 | #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ | ||
534 | E1000_GCR_RXDSCW_NO_SNOOP | \ | ||
535 | E1000_GCR_RXDSCR_NO_SNOOP | \ | ||
536 | E1000_GCR_TXD_NO_SNOOP | \ | ||
537 | E1000_GCR_TXDSCW_NO_SNOOP | \ | ||
538 | E1000_GCR_TXDSCR_NO_SNOOP) | ||
539 | |||
540 | /* PHY Control Register */ | 430 | /* PHY Control Register */ |
541 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ | 431 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ |
542 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ | 432 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ |
543 | #define MII_CR_POWER_DOWN 0x0800 /* Power down */ | ||
544 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ | 433 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ |
545 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ | 434 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ |
546 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ | 435 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ |
@@ -670,10 +559,8 @@ | |||
670 | #define IGP_LED3_MODE 0x07000000 | 559 | #define IGP_LED3_MODE 0x07000000 |
671 | 560 | ||
672 | /* PCI/PCI-X/PCI-EX Config space */ | 561 | /* PCI/PCI-X/PCI-EX Config space */ |
673 | #define PCI_HEADER_TYPE_REGISTER 0x0E | ||
674 | #define PCIE_LINK_STATUS 0x12 | 562 | #define PCIE_LINK_STATUS 0x12 |
675 | 563 | ||
676 | #define PCI_HEADER_TYPE_MULTIFUNC 0x80 | ||
677 | #define PCIE_LINK_WIDTH_MASK 0x3F0 | 564 | #define PCIE_LINK_WIDTH_MASK 0x3F0 |
678 | #define PCIE_LINK_WIDTH_SHIFT 4 | 565 | #define PCIE_LINK_WIDTH_SHIFT 4 |
679 | 566 | ||
diff --git a/drivers/net/igb/e1000_mac.h b/drivers/net/igb/e1000_mac.h index 91461de083f..e5200def582 100644 --- a/drivers/net/igb/e1000_mac.h +++ b/drivers/net/igb/e1000_mac.h | |||
@@ -82,13 +82,8 @@ enum e1000_mng_mode { | |||
82 | #define E1000_FWSM_MODE_MASK 0xE | 82 | #define E1000_FWSM_MODE_MASK 0xE |
83 | #define E1000_FWSM_MODE_SHIFT 1 | 83 | #define E1000_FWSM_MODE_SHIFT 1 |
84 | 84 | ||
85 | #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 | ||
86 | #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 | 85 | #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 |
87 | 86 | ||
88 | #define E1000_HICR_EN 0x01 /* Enable bit - RO */ | ||
89 | /* Driver sets this bit when done to put command in RAM */ | ||
90 | #define E1000_HICR_C 0x02 | ||
91 | |||
92 | extern void e1000_init_function_pointers_82575(struct e1000_hw *hw); | 87 | extern void e1000_init_function_pointers_82575(struct e1000_hw *hw); |
93 | extern u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr); | 88 | extern u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr); |
94 | 89 | ||
diff --git a/drivers/net/igb/e1000_phy.c b/drivers/net/igb/e1000_phy.c index ff0050e5d0b..de2d4862468 100644 --- a/drivers/net/igb/e1000_phy.c +++ b/drivers/net/igb/e1000_phy.c | |||
@@ -39,9 +39,6 @@ static s32 igb_wait_autoneg(struct e1000_hw *hw); | |||
39 | /* Cable length tables */ | 39 | /* Cable length tables */ |
40 | static const u16 e1000_m88_cable_length_table[] = | 40 | static const u16 e1000_m88_cable_length_table[] = |
41 | { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; | 41 | { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; |
42 | #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ | ||
43 | (sizeof(e1000_m88_cable_length_table) / \ | ||
44 | sizeof(e1000_m88_cable_length_table[0])) | ||
45 | 42 | ||
46 | static const u16 e1000_igp_2_cable_length_table[] = | 43 | static const u16 e1000_igp_2_cable_length_table[] = |
47 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, | 44 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, |
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h index 1fb19ca081c..95ed8ec1577 100644 --- a/drivers/net/igb/e1000_regs.h +++ b/drivers/net/igb/e1000_regs.h | |||
@@ -73,7 +73,6 @@ | |||
73 | #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ | 73 | #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ |
74 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ | 74 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ |
75 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ | 75 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ |
76 | #define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n))) | ||
77 | #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ | 76 | #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ |
78 | 77 | ||
79 | /* IEEE 1588 TIMESYNCH */ | 78 | /* IEEE 1588 TIMESYNCH */ |
@@ -178,7 +177,6 @@ enum { | |||
178 | : (0x0E018 + ((_n) * 0x40))) | 177 | : (0x0E018 + ((_n) * 0x40))) |
179 | #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \ | 178 | #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \ |
180 | : (0x0E028 + ((_n) * 0x40))) | 179 | : (0x0E028 + ((_n) * 0x40))) |
181 | #define E1000_TARC(_n) (0x03840 + (_n << 8)) | ||
182 | #define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) | 180 | #define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) |
183 | #define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) | 181 | #define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) |
184 | #define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \ | 182 | #define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \ |
@@ -301,9 +299,7 @@ enum { | |||
301 | #define E1000_MANC 0x05820 /* Management Control - RW */ | 299 | #define E1000_MANC 0x05820 /* Management Control - RW */ |
302 | #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ | 300 | #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ |
303 | #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ | 301 | #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ |
304 | #define E1000_HOST_IF 0x08800 /* Host Interface */ | ||
305 | 302 | ||
306 | #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ | ||
307 | #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ | 303 | #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ |
308 | #define E1000_CCMCTL 0x05B48 /* CCM Control Register */ | 304 | #define E1000_CCMCTL 0x05B48 /* CCM Control Register */ |
309 | #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ | 305 | #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ |
@@ -311,9 +307,7 @@ enum { | |||
311 | #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ | 307 | #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ |
312 | #define E1000_SWSM 0x05B50 /* SW Semaphore */ | 308 | #define E1000_SWSM 0x05B50 /* SW Semaphore */ |
313 | #define E1000_FWSM 0x05B54 /* FW Semaphore */ | 309 | #define E1000_FWSM 0x05B54 /* FW Semaphore */ |
314 | #define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ | ||
315 | #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ | 310 | #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ |
316 | #define E1000_HICR 0x08F00 /* Host Inteface Control */ | ||
317 | 311 | ||
318 | /* RSS registers */ | 312 | /* RSS registers */ |
319 | #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ | 313 | #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ |
@@ -322,14 +316,6 @@ enum { | |||
322 | #define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */ | 316 | #define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */ |
323 | /* MSI-X Allocation Register (_i) - RW */ | 317 | /* MSI-X Allocation Register (_i) - RW */ |
324 | #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) | 318 | #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) |
325 | /* MSI-X Table entry addr low reg 0 - RW */ | ||
326 | #define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) | ||
327 | /* MSI-X Table entry addr upper reg 0 - RW */ | ||
328 | #define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) | ||
329 | /* MSI-X Table entry message reg 0 - RW */ | ||
330 | #define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) | ||
331 | /* MSI-X Table entry vector ctrl reg 0 - RW */ | ||
332 | #define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) | ||
333 | /* Redirection Table - RW Array */ | 319 | /* Redirection Table - RW Array */ |
334 | #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) | 320 | #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) |
335 | #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ | 321 | #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ |
diff --git a/drivers/net/igb/igb.h b/drivers/net/igb/igb.h index bb8c35cec1a..1f09e042a5f 100644 --- a/drivers/net/igb/igb.h +++ b/drivers/net/igb/igb.h | |||
@@ -40,17 +40,9 @@ | |||
40 | 40 | ||
41 | struct igb_adapter; | 41 | struct igb_adapter; |
42 | 42 | ||
43 | /* Interrupt defines */ | ||
44 | #define IGB_MIN_DYN_ITR 3000 | ||
45 | #define IGB_MAX_DYN_ITR 96000 | ||
46 | |||
47 | /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */ | 43 | /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */ |
48 | #define IGB_START_ITR 648 | 44 | #define IGB_START_ITR 648 |
49 | 45 | ||
50 | #define IGB_DYN_ITR_PACKET_THRESHOLD 2 | ||
51 | #define IGB_DYN_ITR_LENGTH_LOW 200 | ||
52 | #define IGB_DYN_ITR_LENGTH_HIGH 1000 | ||
53 | |||
54 | /* TX/RX descriptor defines */ | 46 | /* TX/RX descriptor defines */ |
55 | #define IGB_DEFAULT_TXD 256 | 47 | #define IGB_DEFAULT_TXD 256 |
56 | #define IGB_MIN_TXD 80 | 48 | #define IGB_MIN_TXD 80 |
@@ -92,8 +84,6 @@ struct igb_adapter; | |||
92 | #define IGB_RXBUFFER_512 512 | 84 | #define IGB_RXBUFFER_512 512 |
93 | #define IGB_RXBUFFER_1024 1024 | 85 | #define IGB_RXBUFFER_1024 1024 |
94 | #define IGB_RXBUFFER_2048 2048 | 86 | #define IGB_RXBUFFER_2048 2048 |
95 | #define IGB_RXBUFFER_4096 4096 | ||
96 | #define IGB_RXBUFFER_8192 8192 | ||
97 | #define IGB_RXBUFFER_16384 16384 | 87 | #define IGB_RXBUFFER_16384 16384 |
98 | 88 | ||
99 | /* Packet Buffer allocations */ | 89 | /* Packet Buffer allocations */ |
@@ -286,10 +276,9 @@ struct igb_adapter { | |||
286 | }; | 276 | }; |
287 | 277 | ||
288 | #define IGB_FLAG_HAS_MSI (1 << 0) | 278 | #define IGB_FLAG_HAS_MSI (1 << 0) |
289 | #define IGB_FLAG_MSI_ENABLE (1 << 1) | 279 | #define IGB_FLAG_DCA_ENABLED (1 << 1) |
290 | #define IGB_FLAG_DCA_ENABLED (1 << 2) | 280 | #define IGB_FLAG_QUAD_PORT_A (1 << 2) |
291 | #define IGB_FLAG_QUAD_PORT_A (1 << 3) | 281 | #define IGB_FLAG_NEED_CTX_IDX (1 << 3) |
292 | #define IGB_FLAG_NEED_CTX_IDX (1 << 4) | ||
293 | 282 | ||
294 | enum e1000_state_t { | 283 | enum e1000_state_t { |
295 | __IGB_TESTING, | 284 | __IGB_TESTING, |
diff --git a/drivers/net/igb/igb_ethtool.c b/drivers/net/igb/igb_ethtool.c index bd050b1dab7..30b7bc008d9 100644 --- a/drivers/net/igb/igb_ethtool.c +++ b/drivers/net/igb/igb_ethtool.c | |||
@@ -1366,8 +1366,7 @@ static int igb_setup_desc_rings(struct igb_adapter *adapter) | |||
1366 | wr32(E1000_RDH(0), 0); | 1366 | wr32(E1000_RDH(0), 0); |
1367 | wr32(E1000_RDT(0), 0); | 1367 | wr32(E1000_RDT(0), 0); |
1368 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); | 1368 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); |
1369 | rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 | | 1369 | rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | |
1370 | E1000_RCTL_RDMTS_HALF | | ||
1371 | (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); | 1370 | (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); |
1372 | wr32(E1000_RCTL, rctl); | 1371 | wr32(E1000_RCTL, rctl); |
1373 | wr32(E1000_SRRCTL(0), 0); | 1372 | wr32(E1000_SRRCTL(0), 0); |
@@ -1855,9 +1854,6 @@ static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | |||
1855 | return 0; | 1854 | return 0; |
1856 | } | 1855 | } |
1857 | 1856 | ||
1858 | /* toggle LED 4 times per second = 2 "blinks" per second */ | ||
1859 | #define IGB_ID_INTERVAL (HZ/4) | ||
1860 | |||
1861 | /* bit defines for adapter->led_status */ | 1857 | /* bit defines for adapter->led_status */ |
1862 | #define IGB_LED_ON 0 | 1858 | #define IGB_LED_ON 0 |
1863 | 1859 | ||
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c index 18bc5700faf..23209bd4f40 100644 --- a/drivers/net/igb/igb_main.c +++ b/drivers/net/igb/igb_main.c | |||
@@ -1305,7 +1305,7 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1305 | hw->fc.original_type = e1000_fc_default; | 1305 | hw->fc.original_type = e1000_fc_default; |
1306 | hw->fc.type = e1000_fc_default; | 1306 | hw->fc.type = e1000_fc_default; |
1307 | 1307 | ||
1308 | adapter->itr_setting = 3; | 1308 | adapter->itr_setting = IGB_DEFAULT_ITR; |
1309 | adapter->itr = IGB_START_ITR; | 1309 | adapter->itr = IGB_START_ITR; |
1310 | 1310 | ||
1311 | igb_validate_mdi_setting(hw); | 1311 | igb_validate_mdi_setting(hw); |
@@ -1366,7 +1366,7 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1366 | dev_info(&pdev->dev, "DCA enabled\n"); | 1366 | dev_info(&pdev->dev, "DCA enabled\n"); |
1367 | /* Always use CB2 mode, difference is masked | 1367 | /* Always use CB2 mode, difference is masked |
1368 | * in the CB driver. */ | 1368 | * in the CB driver. */ |
1369 | wr32(E1000_DCA_CTRL, 2); | 1369 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); |
1370 | igb_setup_dca(adapter); | 1370 | igb_setup_dca(adapter); |
1371 | } | 1371 | } |
1372 | #endif | 1372 | #endif |
@@ -1498,7 +1498,7 @@ static void __devexit igb_remove(struct pci_dev *pdev) | |||
1498 | dev_info(&pdev->dev, "DCA disabled\n"); | 1498 | dev_info(&pdev->dev, "DCA disabled\n"); |
1499 | dca_remove_requester(&pdev->dev); | 1499 | dca_remove_requester(&pdev->dev); |
1500 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; | 1500 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
1501 | wr32(E1000_DCA_CTRL, 1); | 1501 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
1502 | } | 1502 | } |
1503 | #endif | 1503 | #endif |
1504 | 1504 | ||
@@ -3058,8 +3058,6 @@ static int igb_maybe_stop_tx(struct net_device *netdev, | |||
3058 | return __igb_maybe_stop_tx(netdev, tx_ring, size); | 3058 | return __igb_maybe_stop_tx(netdev, tx_ring, size); |
3059 | } | 3059 | } |
3060 | 3060 | ||
3061 | #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1) | ||
3062 | |||
3063 | static int igb_xmit_frame_ring_adv(struct sk_buff *skb, | 3061 | static int igb_xmit_frame_ring_adv(struct sk_buff *skb, |
3064 | struct net_device *netdev, | 3062 | struct net_device *netdev, |
3065 | struct igb_ring *tx_ring) | 3063 | struct igb_ring *tx_ring) |
@@ -3586,7 +3584,7 @@ static int __igb_notify_dca(struct device *dev, void *data) | |||
3586 | break; | 3584 | break; |
3587 | /* Always use CB2 mode, difference is masked | 3585 | /* Always use CB2 mode, difference is masked |
3588 | * in the CB driver. */ | 3586 | * in the CB driver. */ |
3589 | wr32(E1000_DCA_CTRL, 2); | 3587 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); |
3590 | if (dca_add_requester(dev) == 0) { | 3588 | if (dca_add_requester(dev) == 0) { |
3591 | adapter->flags |= IGB_FLAG_DCA_ENABLED; | 3589 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
3592 | dev_info(&adapter->pdev->dev, "DCA enabled\n"); | 3590 | dev_info(&adapter->pdev->dev, "DCA enabled\n"); |
@@ -3601,7 +3599,7 @@ static int __igb_notify_dca(struct device *dev, void *data) | |||
3601 | dca_remove_requester(dev); | 3599 | dca_remove_requester(dev); |
3602 | dev_info(&adapter->pdev->dev, "DCA disabled\n"); | 3600 | dev_info(&adapter->pdev->dev, "DCA disabled\n"); |
3603 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; | 3601 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
3604 | wr32(E1000_DCA_CTRL, 1); | 3602 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
3605 | } | 3603 | } |
3606 | break; | 3604 | break; |
3607 | } | 3605 | } |