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-rw-r--r--drivers/net/ehea/ehea_phyp.h455
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diff --git a/drivers/net/ehea/ehea_phyp.h b/drivers/net/ehea/ehea_phyp.h
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1/*
2 * linux/drivers/net/ehea/ehea_phyp.h
3 *
4 * eHEA ethernet device driver for IBM eServer System p
5 *
6 * (C) Copyright IBM Corp. 2006
7 *
8 * Authors:
9 * Christoph Raisch <raisch@de.ibm.com>
10 * Jan-Bernd Themann <themann@de.ibm.com>
11 * Thomas Klein <tklein@de.ibm.com>
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2, or (at your option)
17 * any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __EHEA_PHYP_H__
30#define __EHEA_PHYP_H__
31
32#include <linux/delay.h>
33#include <asm/hvcall.h>
34#include "ehea.h"
35#include "ehea_hw.h"
36#include "ehea_hcall.h"
37
38/* Some abbreviations used here:
39 *
40 * hcp_* - structures, variables and functions releated to Hypervisor Calls
41 */
42
43static inline u32 get_longbusy_msecs(int long_busy_ret_code)
44{
45 switch (long_busy_ret_code) {
46 case H_LONG_BUSY_ORDER_1_MSEC:
47 return 1;
48 case H_LONG_BUSY_ORDER_10_MSEC:
49 return 10;
50 case H_LONG_BUSY_ORDER_100_MSEC:
51 return 100;
52 case H_LONG_BUSY_ORDER_1_SEC:
53 return 1000;
54 case H_LONG_BUSY_ORDER_10_SEC:
55 return 10000;
56 case H_LONG_BUSY_ORDER_100_SEC:
57 return 100000;
58 default:
59 return 1;
60 }
61}
62
63/* Notification Event Queue (NEQ) Entry bit masks */
64#define NEQE_EVENT_CODE EHEA_BMASK_IBM(2, 7)
65#define NEQE_PORTNUM EHEA_BMASK_IBM(32, 47)
66#define NEQE_PORT_UP EHEA_BMASK_IBM(16, 16)
67#define NEQE_EXTSWITCH_PORT_UP EHEA_BMASK_IBM(17, 17)
68#define NEQE_EXTSWITCH_PRIMARY EHEA_BMASK_IBM(18, 18)
69#define NEQE_PLID EHEA_BMASK_IBM(16, 47)
70
71/* Notification Event Codes */
72#define EHEA_EC_PORTSTATE_CHG 0x30
73#define EHEA_EC_ADAPTER_MALFUNC 0x32
74#define EHEA_EC_PORT_MALFUNC 0x33
75
76/* Notification Event Log Register (NELR) bit masks */
77#define NELR_PORT_MALFUNC EHEA_BMASK_IBM(61, 61)
78#define NELR_ADAPTER_MALFUNC EHEA_BMASK_IBM(62, 62)
79#define NELR_PORTSTATE_CHG EHEA_BMASK_IBM(63, 63)
80
81static inline void hcp_epas_ctor(struct h_epas *epas, u64 paddr_kernel,
82 u64 paddr_user)
83{
84 epas->kernel.addr = ioremap(paddr_kernel, PAGE_SIZE);
85 epas->user.addr = paddr_user;
86}
87
88static inline void hcp_epas_dtor(struct h_epas *epas)
89{
90 if (epas->kernel.addr)
91 iounmap(epas->kernel.addr);
92
93 epas->user.addr = 0;
94 epas->kernel.addr = 0;
95}
96
97struct hcp_modify_qp_cb0 {
98 u64 qp_ctl_reg; /* 00 */
99 u32 max_swqe; /* 02 */
100 u32 max_rwqe; /* 03 */
101 u32 port_nb; /* 04 */
102 u32 reserved0; /* 05 */
103 u64 qp_aer; /* 06 */
104 u64 qp_tenure; /* 08 */
105};
106
107/* Hcall Query/Modify Queue Pair Control Block 0 Selection Mask Bits */
108#define H_QPCB0_ALL EHEA_BMASK_IBM(0, 5)
109#define H_QPCB0_QP_CTL_REG EHEA_BMASK_IBM(0, 0)
110#define H_QPCB0_MAX_SWQE EHEA_BMASK_IBM(1, 1)
111#define H_QPCB0_MAX_RWQE EHEA_BMASK_IBM(2, 2)
112#define H_QPCB0_PORT_NB EHEA_BMASK_IBM(3, 3)
113#define H_QPCB0_QP_AER EHEA_BMASK_IBM(4, 4)
114#define H_QPCB0_QP_TENURE EHEA_BMASK_IBM(5, 5)
115
116/* Queue Pair Control Register Status Bits */
117#define H_QP_CR_ENABLED 0x8000000000000000ULL /* QP enabled */
118 /* QP States: */
119#define H_QP_CR_STATE_RESET 0x0000010000000000ULL /* Reset */
120#define H_QP_CR_STATE_INITIALIZED 0x0000020000000000ULL /* Initialized */
121#define H_QP_CR_STATE_RDY2RCV 0x0000030000000000ULL /* Ready to recv */
122#define H_QP_CR_STATE_RDY2SND 0x0000050000000000ULL /* Ready to send */
123#define H_QP_CR_STATE_ERROR 0x0000800000000000ULL /* Error */
124
125struct hcp_modify_qp_cb1 {
126 u32 qpn; /* 00 */
127 u32 qp_asyn_ev_eq_nb; /* 01 */
128 u64 sq_cq_handle; /* 02 */
129 u64 rq_cq_handle; /* 04 */
130 /* sgel = scatter gather element */
131 u32 sgel_nb_sq; /* 06 */
132 u32 sgel_nb_rq1; /* 07 */
133 u32 sgel_nb_rq2; /* 08 */
134 u32 sgel_nb_rq3; /* 09 */
135};
136
137/* Hcall Query/Modify Queue Pair Control Block 1 Selection Mask Bits */
138#define H_QPCB1_ALL EHEA_BMASK_IBM(0, 7)
139#define H_QPCB1_QPN EHEA_BMASK_IBM(0, 0)
140#define H_QPCB1_ASYN_EV_EQ_NB EHEA_BMASK_IBM(1, 1)
141#define H_QPCB1_SQ_CQ_HANDLE EHEA_BMASK_IBM(2, 2)
142#define H_QPCB1_RQ_CQ_HANDLE EHEA_BMASK_IBM(3, 3)
143#define H_QPCB1_SGEL_NB_SQ EHEA_BMASK_IBM(4, 4)
144#define H_QPCB1_SGEL_NB_RQ1 EHEA_BMASK_IBM(5, 5)
145#define H_QPCB1_SGEL_NB_RQ2 EHEA_BMASK_IBM(6, 6)
146#define H_QPCB1_SGEL_NB_RQ3 EHEA_BMASK_IBM(7, 7)
147
148struct hcp_query_ehea {
149 u32 cur_num_qps; /* 00 */
150 u32 cur_num_cqs; /* 01 */
151 u32 cur_num_eqs; /* 02 */
152 u32 cur_num_mrs; /* 03 */
153 u32 auth_level; /* 04 */
154 u32 max_num_qps; /* 05 */
155 u32 max_num_cqs; /* 06 */
156 u32 max_num_eqs; /* 07 */
157 u32 max_num_mrs; /* 08 */
158 u32 reserved0; /* 09 */
159 u32 int_clock_freq; /* 10 */
160 u32 max_num_pds; /* 11 */
161 u32 max_num_addr_handles; /* 12 */
162 u32 max_num_cqes; /* 13 */
163 u32 max_num_wqes; /* 14 */
164 u32 max_num_sgel_rq1wqe; /* 15 */
165 u32 max_num_sgel_rq2wqe; /* 16 */
166 u32 max_num_sgel_rq3wqe; /* 17 */
167 u32 mr_page_size; /* 18 */
168 u32 reserved1; /* 19 */
169 u64 max_mr_size; /* 20 */
170 u64 reserved2; /* 22 */
171 u32 num_ports; /* 24 */
172 u32 reserved3; /* 25 */
173 u32 reserved4; /* 26 */
174 u32 reserved5; /* 27 */
175 u64 max_mc_mac; /* 28 */
176 u64 ehea_cap; /* 30 */
177 u32 max_isn_per_eq; /* 32 */
178 u32 max_num_neq; /* 33 */
179 u64 max_num_vlan_ids; /* 34 */
180 u32 max_num_port_group; /* 36 */
181 u32 max_num_phys_port; /* 37 */
182
183};
184
185/* Hcall Query/Modify Port Control Block defines */
186#define H_PORT_CB0 0
187#define H_PORT_CB1 1
188#define H_PORT_CB2 2
189#define H_PORT_CB3 3
190#define H_PORT_CB4 4
191#define H_PORT_CB5 5
192#define H_PORT_CB6 6
193#define H_PORT_CB7 7
194
195struct hcp_ehea_port_cb0 {
196 u64 port_mac_addr;
197 u64 port_rc;
198 u64 reserved0;
199 u32 port_op_state;
200 u32 port_speed;
201 u32 ext_swport_op_state;
202 u32 neg_tpf_prpf;
203 u32 num_default_qps;
204 u32 reserved1;
205 u64 default_qpn_arr[16];
206};
207
208/* Hcall Query/Modify Port Control Block 0 Selection Mask Bits */
209#define H_PORT_CB0_ALL EHEA_BMASK_IBM(0, 7) /* Set all bits */
210#define H_PORT_CB0_MAC EHEA_BMASK_IBM(0, 0) /* MAC address */
211#define H_PORT_CB0_PRC EHEA_BMASK_IBM(1, 1) /* Port Recv Control */
212#define H_PORT_CB0_DEFQPNARRAY EHEA_BMASK_IBM(7, 7) /* Default QPN Array */
213
214/* Hcall Query Port: Returned port speed values */
215#define H_SPEED_10M_H 1 /* 10 Mbps, Half Duplex */
216#define H_SPEED_10M_F 2 /* 10 Mbps, Full Duplex */
217#define H_SPEED_100M_H 3 /* 100 Mbps, Half Duplex */
218#define H_SPEED_100M_F 4 /* 100 Mbps, Full Duplex */
219#define H_SPEED_1G_F 6 /* 1 Gbps, Full Duplex */
220#define H_SPEED_10G_F 8 /* 10 Gbps, Full Duplex */
221
222/* Port Receive Control Status Bits */
223#define PXLY_RC_VALID EHEA_BMASK_IBM(49, 49)
224#define PXLY_RC_VLAN_XTRACT EHEA_BMASK_IBM(50, 50)
225#define PXLY_RC_TCP_6_TUPLE EHEA_BMASK_IBM(51, 51)
226#define PXLY_RC_UDP_6_TUPLE EHEA_BMASK_IBM(52, 52)
227#define PXLY_RC_TCP_3_TUPLE EHEA_BMASK_IBM(53, 53)
228#define PXLY_RC_TCP_2_TUPLE EHEA_BMASK_IBM(54, 54)
229#define PXLY_RC_LLC_SNAP EHEA_BMASK_IBM(55, 55)
230#define PXLY_RC_JUMBO_FRAME EHEA_BMASK_IBM(56, 56)
231#define PXLY_RC_FRAG_IP_PKT EHEA_BMASK_IBM(57, 57)
232#define PXLY_RC_TCP_UDP_CHKSUM EHEA_BMASK_IBM(58, 58)
233#define PXLY_RC_IP_CHKSUM EHEA_BMASK_IBM(59, 59)
234#define PXLY_RC_MAC_FILTER EHEA_BMASK_IBM(60, 60)
235#define PXLY_RC_UNTAG_FILTER EHEA_BMASK_IBM(61, 61)
236#define PXLY_RC_VLAN_TAG_FILTER EHEA_BMASK_IBM(62, 63)
237
238#define PXLY_RC_VLAN_FILTER 2
239#define PXLY_RC_VLAN_PERM 0
240
241
242#define H_PORT_CB1_ALL 0x8000000000000000ULL
243
244struct hcp_ehea_port_cb1 {
245 u64 vlan_filter[64];
246};
247
248#define H_PORT_CB2_ALL 0xFFE0000000000000ULL
249
250struct hcp_ehea_port_cb2 {
251 u64 rxo;
252 u64 rxucp;
253 u64 rxufd;
254 u64 rxuerr;
255 u64 rxftl;
256 u64 rxmcp;
257 u64 rxbcp;
258 u64 txo;
259 u64 txucp;
260 u64 txmcp;
261 u64 txbcp;
262};
263
264struct hcp_ehea_port_cb3 {
265 u64 vlan_bc_filter[64];
266 u64 vlan_mc_filter[64];
267 u64 vlan_un_filter[64];
268 u64 port_mac_hash_array[64];
269};
270
271#define H_PORT_CB4_ALL 0xF000000000000000ULL
272#define H_PORT_CB4_JUMBO 0x1000000000000000ULL
273#define H_PORT_CB4_SPEED 0x8000000000000000ULL
274
275struct hcp_ehea_port_cb4 {
276 u32 port_speed;
277 u32 pause_frame;
278 u32 ens_port_op_state;
279 u32 jumbo_frame;
280 u32 ens_port_wrap;
281};
282
283/* Hcall Query/Modify Port Control Block 5 Selection Mask Bits */
284#define H_PORT_CB5_RCU 0x0001000000000000ULL
285#define PXS_RCU EHEA_BMASK_IBM(61, 63)
286
287struct hcp_ehea_port_cb5 {
288 u64 prc; /* 00 */
289 u64 uaa; /* 01 */
290 u64 macvc; /* 02 */
291 u64 xpcsc; /* 03 */
292 u64 xpcsp; /* 04 */
293 u64 pcsid; /* 05 */
294 u64 xpcsst; /* 06 */
295 u64 pthlb; /* 07 */
296 u64 pthrb; /* 08 */
297 u64 pqu; /* 09 */
298 u64 pqd; /* 10 */
299 u64 prt; /* 11 */
300 u64 wsth; /* 12 */
301 u64 rcb; /* 13 */
302 u64 rcm; /* 14 */
303 u64 rcu; /* 15 */
304 u64 macc; /* 16 */
305 u64 pc; /* 17 */
306 u64 pst; /* 18 */
307 u64 ducqpn; /* 19 */
308 u64 mcqpn; /* 20 */
309 u64 mma; /* 21 */
310 u64 pmc0h; /* 22 */
311 u64 pmc0l; /* 23 */
312 u64 lbc; /* 24 */
313};
314
315#define H_PORT_CB6_ALL 0xFFFFFE7FFFFF8000ULL
316
317struct hcp_ehea_port_cb6 {
318 u64 rxo; /* 00 */
319 u64 rx64; /* 01 */
320 u64 rx65; /* 02 */
321 u64 rx128; /* 03 */
322 u64 rx256; /* 04 */
323 u64 rx512; /* 05 */
324 u64 rx1024; /* 06 */
325 u64 rxbfcs; /* 07 */
326 u64 rxime; /* 08 */
327 u64 rxrle; /* 09 */
328 u64 rxorle; /* 10 */
329 u64 rxftl; /* 11 */
330 u64 rxjab; /* 12 */
331 u64 rxse; /* 13 */
332 u64 rxce; /* 14 */
333 u64 rxrf; /* 15 */
334 u64 rxfrag; /* 16 */
335 u64 rxuoc; /* 17 */
336 u64 rxcpf; /* 18 */
337 u64 rxsb; /* 19 */
338 u64 rxfd; /* 20 */
339 u64 rxoerr; /* 21 */
340 u64 rxaln; /* 22 */
341 u64 ducqpn; /* 23 */
342 u64 reserved0; /* 24 */
343 u64 rxmcp; /* 25 */
344 u64 rxbcp; /* 26 */
345 u64 txmcp; /* 27 */
346 u64 txbcp; /* 28 */
347 u64 txo; /* 29 */
348 u64 tx64; /* 30 */
349 u64 tx65; /* 31 */
350 u64 tx128; /* 32 */
351 u64 tx256; /* 33 */
352 u64 tx512; /* 34 */
353 u64 tx1024; /* 35 */
354 u64 txbfcs; /* 36 */
355 u64 txcpf; /* 37 */
356 u64 txlf; /* 38 */
357 u64 txrf; /* 39 */
358 u64 txime; /* 40 */
359 u64 txsc; /* 41 */
360 u64 txmc; /* 42 */
361 u64 txsqe; /* 43 */
362 u64 txdef; /* 44 */
363 u64 txlcol; /* 45 */
364 u64 txexcol; /* 46 */
365 u64 txcse; /* 47 */
366 u64 txbor; /* 48 */
367};
368
369#define H_PORT_CB7_DUCQPN 0x8000000000000000ULL
370
371struct hcp_ehea_port_cb7 {
372 u64 def_uc_qpn;
373};
374
375u64 ehea_h_query_ehea_qp(const u64 adapter_handle,
376 const u8 qp_category,
377 const u64 qp_handle, const u64 sel_mask,
378 void *cb_addr);
379
380u64 ehea_h_modify_ehea_qp(const u64 adapter_handle,
381 const u8 cat,
382 const u64 qp_handle,
383 const u64 sel_mask,
384 void *cb_addr,
385 u64 * inv_attr_id,
386 u64 * proc_mask, u16 * out_swr, u16 * out_rwr);
387
388u64 ehea_h_alloc_resource_eq(const u64 adapter_handle,
389 struct ehea_eq_attr *eq_attr, u64 * eq_handle);
390
391u64 ehea_h_alloc_resource_cq(const u64 adapter_handle,
392 struct ehea_cq_attr *cq_attr,
393 u64 * cq_handle, struct h_epas *epas);
394
395u64 ehea_h_alloc_resource_qp(const u64 adapter_handle,
396 struct ehea_qp_init_attr *init_attr,
397 const u32 pd,
398 u64 * qp_handle, struct h_epas *h_epas);
399
400#define H_REG_RPAGE_PAGE_SIZE EHEA_BMASK_IBM(48,55)
401#define H_REG_RPAGE_QT EHEA_BMASK_IBM(62,63)
402
403u64 ehea_h_register_rpage(const u64 adapter_handle,
404 const u8 pagesize,
405 const u8 queue_type,
406 const u64 resource_handle,
407 const u64 log_pageaddr, u64 count);
408
409#define H_DISABLE_GET_EHEA_WQE_P 1
410#define H_DISABLE_GET_SQ_WQE_P 2
411#define H_DISABLE_GET_RQC 3
412
413u64 ehea_h_disable_and_get_hea(const u64 adapter_handle, const u64 qp_handle);
414
415u64 ehea_h_free_resource(const u64 adapter_handle, const u64 res_handle);
416
417u64 ehea_h_alloc_resource_mr(const u64 adapter_handle, const u64 vaddr,
418 const u64 length, const u32 access_ctrl,
419 const u32 pd, u64 * mr_handle, u32 * lkey);
420
421u64 ehea_h_register_rpage_mr(const u64 adapter_handle, const u64 mr_handle,
422 const u8 pagesize, const u8 queue_type,
423 const u64 log_pageaddr, const u64 count);
424
425u64 ehea_h_register_smr(const u64 adapter_handle, const u64 orig_mr_handle,
426 const u64 vaddr_in, const u32 access_ctrl, const u32 pd,
427 struct ehea_mr *mr);
428
429u64 ehea_h_query_ehea(const u64 adapter_handle, void *cb_addr);
430
431/* output param R5 */
432#define H_MEHEAPORT_CAT EHEA_BMASK_IBM(40,47)
433#define H_MEHEAPORT_PN EHEA_BMASK_IBM(48,63)
434
435u64 ehea_h_query_ehea_port(const u64 adapter_handle, const u16 port_num,
436 const u8 cb_cat, const u64 select_mask,
437 void *cb_addr);
438
439u64 ehea_h_modify_ehea_port(const u64 adapter_handle, const u16 port_num,
440 const u8 cb_cat, const u64 select_mask,
441 void *cb_addr);
442
443#define H_REGBCMC_PN EHEA_BMASK_IBM(48, 63)
444#define H_REGBCMC_REGTYPE EHEA_BMASK_IBM(61, 63)
445#define H_REGBCMC_MACADDR EHEA_BMASK_IBM(16, 63)
446#define H_REGBCMC_VLANID EHEA_BMASK_IBM(52, 63)
447
448u64 ehea_h_reg_dereg_bcmc(const u64 adapter_handle, const u16 port_num,
449 const u8 reg_type, const u64 mc_mac_addr,
450 const u16 vlan_id, const u32 hcall_id);
451
452u64 ehea_h_reset_events(const u64 adapter_handle, const u64 neq_handle,
453 const u64 event_mask);
454
455#endif /* __EHEA_PHYP_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 07:31:20 -0500