diff options
Diffstat (limited to 'drivers/net/e1000e/defines.h')
| -rw-r--r-- | drivers/net/e1000e/defines.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index 14b0e6cd3b8..48f79ecb82a 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h | |||
| @@ -71,9 +71,11 @@ | |||
| 71 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ | 71 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ |
| 72 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 | 72 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
| 73 | #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 | 73 | #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 |
| 74 | #define E1000_CTRL_EXT_EIAME 0x01000000 | ||
| 74 | #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ | 75 | #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ |
| 75 | #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ | 76 | #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ |
| 76 | #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ | 77 | #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ |
| 78 | #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ | ||
| 77 | 79 | ||
| 78 | /* Receive Descriptor bit definitions */ | 80 | /* Receive Descriptor bit definitions */ |
| 79 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ | 81 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ |
| @@ -299,6 +301,7 @@ | |||
| 299 | #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ | 301 | #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ |
| 300 | 302 | ||
| 301 | /* Header split receive */ | 303 | /* Header split receive */ |
| 304 | #define E1000_RFCTL_ACK_DIS 0x00001000 | ||
| 302 | #define E1000_RFCTL_EXTEN 0x00008000 | 305 | #define E1000_RFCTL_EXTEN 0x00008000 |
| 303 | #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 | 306 | #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 |
| 304 | #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 | 307 | #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 |
| @@ -363,6 +366,11 @@ | |||
| 363 | #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ | 366 | #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ |
| 364 | #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ | 367 | #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ |
| 365 | #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ | 368 | #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ |
| 369 | #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ | ||
| 370 | #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ | ||
| 371 | #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ | ||
| 372 | #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ | ||
| 373 | #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ | ||
| 366 | 374 | ||
| 367 | /* | 375 | /* |
| 368 | * This defines the bits that are set in the Interrupt Mask | 376 | * This defines the bits that are set in the Interrupt Mask |
| @@ -386,6 +394,11 @@ | |||
| 386 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ | 394 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ |
| 387 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ | 395 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ |
| 388 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ | 396 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ |
| 397 | #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ | ||
| 398 | #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ | ||
| 399 | #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ | ||
| 400 | #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ | ||
| 401 | #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ | ||
| 389 | 402 | ||
| 390 | /* Interrupt Cause Set */ | 403 | /* Interrupt Cause Set */ |
| 391 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ | 404 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ |
| @@ -505,6 +518,7 @@ | |||
| 505 | #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ | 518 | #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ |
| 506 | 519 | ||
| 507 | /* Autoneg Expansion Register */ | 520 | /* Autoneg Expansion Register */ |
| 521 | #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ | ||
| 508 | 522 | ||
| 509 | /* 1000BASE-T Control Register */ | 523 | /* 1000BASE-T Control Register */ |
| 510 | #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ | 524 | #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ |
| @@ -540,6 +554,7 @@ | |||
| 540 | #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ | 554 | #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ |
| 541 | #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ | 555 | #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ |
| 542 | #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ | 556 | #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ |
| 557 | #define E1000_EECD_PRES 0x00000100 /* NVM Present */ | ||
| 543 | #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ | 558 | #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ |
| 544 | /* NVM Addressing bits based on type (0-small, 1-large) */ | 559 | /* NVM Addressing bits based on type (0-small, 1-large) */ |
| 545 | #define E1000_EECD_ADDR_BITS 0x00000400 | 560 | #define E1000_EECD_ADDR_BITS 0x00000400 |