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-rw-r--r--drivers/net/chelsio/osdep.h169
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diff --git a/drivers/net/chelsio/osdep.h b/drivers/net/chelsio/osdep.h
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--- a/drivers/net/chelsio/osdep.h
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1/*****************************************************************************
2 * *
3 * File: osdep.h *
4 * $Revision: 1.9 $ *
5 * $Date: 2005/03/23 07:41:27 $ *
6 * Description: *
7 * part of the Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
38
39#ifndef __CHELSIO_OSDEP_H
40#define __CHELSIO_OSDEP_H
41
42#include <linux/version.h>
43#include <linux/module.h>
44#include <linux/config.h>
45#include <linux/types.h>
46#include <linux/delay.h>
47#include <linux/pci.h>
48#include <linux/ethtool.h>
49#include <linux/mii.h>
50#include <linux/crc32.h>
51#include <linux/init.h>
52#include <asm/io.h>
53
54#include "cxgb2.h"
55
56#define DRV_NAME "cxgb"
57#define PFX DRV_NAME ": "
58
59#define CH_ERR(fmt, ...) printk(KERN_ERR PFX fmt, ## __VA_ARGS__)
60#define CH_WARN(fmt, ...) printk(KERN_WARNING PFX fmt, ## __VA_ARGS__)
61#define CH_ALERT(fmt, ...) printk(KERN_ALERT PFX fmt, ## __VA_ARGS__)
62
63/*
64 * More powerful macro that selectively prints messages based on msg_enable.
65 * For info and debugging messages.
66 */
67#define CH_MSG(adapter, level, category, fmt, ...) do { \
68 if ((adapter)->msg_enable & NETIF_MSG_##category) \
69 printk(KERN_##level PFX "%s: " fmt, (adapter)->name, \
70 ## __VA_ARGS__); \
71} while (0)
72
73#ifdef DEBUG
74# define CH_DBG(adapter, category, fmt, ...) \
75 CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
76#else
77# define CH_DBG(fmt, ...)
78#endif
79
80/* Additional NETIF_MSG_* categories */
81#define NETIF_MSG_MMIO 0x8000000
82
83#define CH_DEVICE(devid, ssid, idx) \
84 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
85
86#define SUPPORTED_PAUSE (1 << 13)
87#define SUPPORTED_LOOPBACK (1 << 15)
88
89#define ADVERTISED_PAUSE (1 << 13)
90#define ADVERTISED_ASYM_PAUSE (1 << 14)
91
92/*
93 * Now that we have included the driver's main data structure,
94 * we typedef it to something the rest of the system understands.
95 */
96typedef struct adapter adapter_t;
97
98#define TPI_LOCK(adapter) spin_lock(&(adapter)->tpi_lock)
99#define TPI_UNLOCK(adapter) spin_unlock(&(adapter)->tpi_lock)
100
101void t1_elmer0_ext_intr(adapter_t *adapter);
102void t1_link_changed(adapter_t *adapter, int port_id, int link_status,
103 int speed, int duplex, int fc);
104
105static inline u16 t1_read_reg_2(adapter_t *adapter, u32 reg_addr)
106{
107 u16 val = readw(adapter->regs + reg_addr);
108
109 CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr,
110 val);
111 return val;
112}
113
114static inline void t1_write_reg_2(adapter_t *adapter, u32 reg_addr, u16 val)
115{
116 CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr,
117 val);
118 writew(val, adapter->regs + reg_addr);
119}
120
121static inline u32 t1_read_reg_4(adapter_t *adapter, u32 reg_addr)
122{
123 u32 val = readl(adapter->regs + reg_addr);
124
125 CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr,
126 val);
127 return val;
128}
129
130static inline void t1_write_reg_4(adapter_t *adapter, u32 reg_addr, u32 val)
131{
132 CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr,
133 val);
134 writel(val, adapter->regs + reg_addr);
135}
136
137static inline const char *port_name(adapter_t *adapter, int port_idx)
138{
139 return adapter->port[port_idx].dev->name;
140}
141
142static inline void t1_set_hw_addr(adapter_t *adapter, int port_idx,
143 u8 hw_addr[])
144{
145 memcpy(adapter->port[port_idx].dev->dev_addr, hw_addr, ETH_ALEN);
146}
147
148struct t1_rx_mode {
149 struct net_device *dev;
150 u32 idx;
151 struct dev_mc_list *list;
152};
153
154#define t1_rx_mode_promisc(rm) (rm->dev->flags & IFF_PROMISC)
155#define t1_rx_mode_allmulti(rm) (rm->dev->flags & IFF_ALLMULTI)
156#define t1_rx_mode_mc_cnt(rm) (rm->dev->mc_count)
157
158static inline u8 *t1_get_next_mcaddr(struct t1_rx_mode *rm)
159{
160 u8 *addr = 0;
161
162 if (rm->idx++ < rm->dev->mc_count) {
163 addr = rm->list->dmi_addr;
164 rm->list = rm->list->next;
165 }
166 return addr;
167}
168
169#endif
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