diff options
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_link.c')
-rw-r--r-- | drivers/net/bnx2x/bnx2x_link.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c index f2f367d4e74..974ef2be36a 100644 --- a/drivers/net/bnx2x/bnx2x_link.c +++ b/drivers/net/bnx2x/bnx2x_link.c | |||
@@ -2823,7 +2823,7 @@ static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, | |||
2823 | struct link_params *params) | 2823 | struct link_params *params) |
2824 | { | 2824 | { |
2825 | u16 cnt, ctrl; | 2825 | u16 cnt, ctrl; |
2826 | /* Wait for soft reset to get cleared upto 1 sec */ | 2826 | /* Wait for soft reset to get cleared up to 1 sec */ |
2827 | for (cnt = 0; cnt < 1000; cnt++) { | 2827 | for (cnt = 0; cnt < 1000; cnt++) { |
2828 | bnx2x_cl45_read(bp, phy, | 2828 | bnx2x_cl45_read(bp, phy, |
2829 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl); | 2829 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl); |
@@ -4141,7 +4141,7 @@ static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy, | |||
4141 | val = (1<<5); | 4141 | val = (1<<5); |
4142 | /* | 4142 | /* |
4143 | * Note that 2.5G works only when used with 1G | 4143 | * Note that 2.5G works only when used with 1G |
4144 | * advertisment | 4144 | * advertisement |
4145 | */ | 4145 | */ |
4146 | } else | 4146 | } else |
4147 | val = (1<<5); | 4147 | val = (1<<5); |
@@ -4151,7 +4151,7 @@ static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy, | |||
4151 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | 4151 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
4152 | val |= (1<<7); | 4152 | val |= (1<<7); |
4153 | 4153 | ||
4154 | /* Note that 2.5G works only when used with 1G advertisment */ | 4154 | /* Note that 2.5G works only when used with 1G advertisement */ |
4155 | if (phy->speed_cap_mask & | 4155 | if (phy->speed_cap_mask & |
4156 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | | 4156 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | |
4157 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) | 4157 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
@@ -5232,14 +5232,14 @@ static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, | |||
5232 | bnx2x_cl45_write(bp, phy, | 5232 | bnx2x_cl45_write(bp, phy, |
5233 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1); | 5233 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1); |
5234 | } else { | 5234 | } else { |
5235 | /* Force 1Gbps using autoneg with 1G advertisment */ | 5235 | /* Force 1Gbps using autoneg with 1G advertisement */ |
5236 | 5236 | ||
5237 | /* Allow CL37 through CL73 */ | 5237 | /* Allow CL37 through CL73 */ |
5238 | DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); | 5238 | DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); |
5239 | bnx2x_cl45_write(bp, phy, | 5239 | bnx2x_cl45_write(bp, phy, |
5240 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | 5240 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); |
5241 | 5241 | ||
5242 | /* Enable Full-Duplex advertisment on CL37 */ | 5242 | /* Enable Full-Duplex advertisement on CL37 */ |
5243 | bnx2x_cl45_write(bp, phy, | 5243 | bnx2x_cl45_write(bp, phy, |
5244 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); | 5244 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); |
5245 | /* Enable CL37 AN */ | 5245 | /* Enable CL37 AN */ |
@@ -6269,7 +6269,7 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy, | |||
6269 | 6269 | ||
6270 | switch (actual_phy_selection) { | 6270 | switch (actual_phy_selection) { |
6271 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | 6271 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: |
6272 | /* Do nothing. Essentialy this is like the priority copper */ | 6272 | /* Do nothing. Essentially this is like the priority copper */ |
6273 | break; | 6273 | break; |
6274 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | 6274 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: |
6275 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; | 6275 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; |
@@ -7765,7 +7765,7 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars, | |||
7765 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | 7765 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); |
7766 | 7766 | ||
7767 | msleep(10); | 7767 | msleep(10); |
7768 | /* The PHY reset is controled by GPIO 1 | 7768 | /* The PHY reset is controlled by GPIO 1 |
7769 | * Hold it as vars low | 7769 | * Hold it as vars low |
7770 | */ | 7770 | */ |
7771 | /* clear link led */ | 7771 | /* clear link led */ |