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-rw-r--r--drivers/net/benet/be.h328
1 files changed, 328 insertions, 0 deletions
diff --git a/drivers/net/benet/be.h b/drivers/net/benet/be.h
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1/*
2 * Copyright (C) 2005 - 2009 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18#ifndef BE_H
19#define BE_H
20
21#include <linux/pci.h>
22#include <linux/etherdevice.h>
23#include <linux/version.h>
24#include <linux/delay.h>
25#include <net/tcp.h>
26#include <net/ip.h>
27#include <net/ipv6.h>
28#include <linux/if_vlan.h>
29#include <linux/workqueue.h>
30#include <linux/interrupt.h>
31#include <linux/inet_lro.h>
32
33#include "be_hw.h"
34
35#define DRV_VER "2.0.348"
36#define DRV_NAME "be2net"
37#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
38#define DRV_DESC BE_NAME "Driver"
39
40/* Number of bytes of an RX frame that are copied to skb->data */
41#define BE_HDR_LEN 64
42#define BE_MAX_JUMBO_FRAME_SIZE 9018
43#define BE_MIN_MTU 256
44
45#define BE_NUM_VLANS_SUPPORTED 64
46#define BE_MAX_EQD 96
47#define BE_MAX_TX_FRAG_COUNT 30
48
49#define EVNT_Q_LEN 1024
50#define TX_Q_LEN 2048
51#define TX_CQ_LEN 1024
52#define RX_Q_LEN 1024 /* Does not support any other value */
53#define RX_CQ_LEN 1024
54#define MCC_Q_LEN 64 /* total size not to exceed 8 pages */
55#define MCC_CQ_LEN 256
56
57#define BE_NAPI_WEIGHT 64
58#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
59#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
60
61#define BE_MAX_LRO_DESCRIPTORS 16
62#define BE_MAX_FRAGS_PER_FRAME 16
63
64struct be_dma_mem {
65 void *va;
66 dma_addr_t dma;
67 u32 size;
68};
69
70struct be_queue_info {
71 struct be_dma_mem dma_mem;
72 u16 len;
73 u16 entry_size; /* Size of an element in the queue */
74 u16 id;
75 u16 tail, head;
76 bool created;
77 atomic_t used; /* Number of valid elements in the queue */
78};
79
80struct be_ctrl_info {
81 u8 __iomem *csr;
82 u8 __iomem *db; /* Door Bell */
83 u8 __iomem *pcicfg; /* PCI config space */
84 int pci_func;
85
86 /* Mbox used for cmd request/response */
87 spinlock_t cmd_lock; /* For serializing cmds to BE card */
88 struct be_dma_mem mbox_mem;
89 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
90 * is stored for freeing purpose */
91 struct be_dma_mem mbox_mem_alloced;
92};
93
94#include "be_cmds.h"
95
96struct be_drvr_stats {
97 u32 be_tx_reqs; /* number of TX requests initiated */
98 u32 be_tx_stops; /* number of times TX Q was stopped */
99 u32 be_fwd_reqs; /* number of send reqs through forwarding i/f */
100 u32 be_tx_wrbs; /* number of tx WRBs used */
101 u32 be_tx_events; /* number of tx completion events */
102 u32 be_tx_compl; /* number of tx completion entries processed */
103 u64 be_tx_jiffies;
104 ulong be_tx_bytes;
105 ulong be_tx_bytes_prev;
106 u32 be_tx_rate;
107
108 u32 cache_barrier[16];
109
110 u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */
111 u32 be_polls; /* number of times NAPI called poll function */
112 u32 be_rx_events; /* number of ucast rx completion events */
113 u32 be_rx_compl; /* number of rx completion entries processed */
114 u32 be_lro_hgram_data[8]; /* histogram of LRO data packets */
115 u32 be_lro_hgram_ack[8]; /* histogram of LRO ACKs */
116 u64 be_rx_jiffies;
117 ulong be_rx_bytes;
118 ulong be_rx_bytes_prev;
119 u32 be_rx_rate;
120 /* number of non ether type II frames dropped where
121 * frame len > length field of Mac Hdr */
122 u32 be_802_3_dropped_frames;
123 /* number of non ether type II frames malformed where
124 * in frame len < length field of Mac Hdr */
125 u32 be_802_3_malformed_frames;
126 u32 be_rxcp_err; /* Num rx completion entries w/ err set. */
127 ulong rx_fps_jiffies; /* jiffies at last FPS calc */
128 u32 be_rx_frags;
129 u32 be_prev_rx_frags;
130 u32 be_rx_fps; /* Rx frags per second */
131};
132
133struct be_stats_obj {
134 struct be_drvr_stats drvr_stats;
135 struct net_device_stats net_stats;
136 struct be_dma_mem cmd;
137};
138
139struct be_eq_obj {
140 struct be_queue_info q;
141 char desc[32];
142
143 /* Adaptive interrupt coalescing (AIC) info */
144 bool enable_aic;
145 u16 min_eqd; /* in usecs */
146 u16 max_eqd; /* in usecs */
147 u16 cur_eqd; /* in usecs */
148
149 struct napi_struct napi;
150};
151
152struct be_tx_obj {
153 struct be_queue_info q;
154 struct be_queue_info cq;
155 /* Remember the skbs that were transmitted */
156 struct sk_buff *sent_skb_list[TX_Q_LEN];
157};
158
159/* Struct to remember the pages posted for rx frags */
160struct be_rx_page_info {
161 struct page *page;
162 dma_addr_t bus;
163 u16 page_offset;
164 bool last_page_user;
165};
166
167struct be_rx_obj {
168 struct be_queue_info q;
169 struct be_queue_info cq;
170 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
171 struct net_lro_mgr lro_mgr;
172 struct net_lro_desc lro_desc[BE_MAX_LRO_DESCRIPTORS];
173};
174
175#define BE_NUM_MSIX_VECTORS 2 /* 1 each for Tx and Rx */
176struct be_adapter {
177 struct pci_dev *pdev;
178 struct net_device *netdev;
179
180 /* Mbox, pci config, csr address information */
181 struct be_ctrl_info ctrl;
182
183 struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS];
184 bool msix_enabled;
185 bool isr_registered;
186
187 /* TX Rings */
188 struct be_eq_obj tx_eq;
189 struct be_tx_obj tx_obj;
190
191 u32 cache_line_break[8];
192
193 /* Rx rings */
194 struct be_eq_obj rx_eq;
195 struct be_rx_obj rx_obj;
196 u32 big_page_size; /* Compounded page size shared by rx wrbs */
197 bool rx_post_starved; /* Zero rx frags have been posted to BE */
198
199 struct vlan_group *vlan_grp;
200 u16 num_vlans;
201 u8 vlan_tag[VLAN_GROUP_ARRAY_LEN];
202
203 struct be_stats_obj stats;
204 /* Work queue used to perform periodic tasks like getting statistics */
205 struct delayed_work work;
206
207 /* Ethtool knobs and info */
208 bool rx_csum; /* BE card must perform rx-checksumming */
209 u32 max_rx_coal;
210 char fw_ver[FW_VER_LEN];
211 u32 if_handle; /* Used to configure filtering */
212 u32 pmac_id; /* MAC addr handle used by BE card */
213
214 struct be_link_info link;
215 u32 port_num;
216};
217
218extern struct ethtool_ops be_ethtool_ops;
219
220#define drvr_stats(adapter) (&adapter->stats.drvr_stats)
221
222#define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
223
224static inline u32 MODULO(u16 val, u16 limit)
225{
226 BUG_ON(limit & (limit - 1));
227 return val & (limit - 1);
228}
229
230static inline void index_adv(u16 *index, u16 val, u16 limit)
231{
232 *index = MODULO((*index + val), limit);
233}
234
235static inline void index_inc(u16 *index, u16 limit)
236{
237 *index = MODULO((*index + 1), limit);
238}
239
240#define PAGE_SHIFT_4K 12
241#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
242
243/* Returns number of pages spanned by the data starting at the given addr */
244#define PAGES_4K_SPANNED(_address, size) \
245 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
246 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
247
248/* Byte offset into the page corresponding to given address */
249#define OFFSET_IN_PAGE(addr) \
250 ((size_t)(addr) & (PAGE_SIZE_4K-1))
251
252/* Returns bit offset within a DWORD of a bitfield */
253#define AMAP_BIT_OFFSET(_struct, field) \
254 (((size_t)&(((_struct *)0)->field))%32)
255
256/* Returns the bit mask of the field that is NOT shifted into location. */
257static inline u32 amap_mask(u32 bitsize)
258{
259 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
260}
261
262static inline void
263amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
264{
265 u32 *dw = (u32 *) ptr + dw_offset;
266 *dw &= ~(mask << offset);
267 *dw |= (mask & value) << offset;
268}
269
270#define AMAP_SET_BITS(_struct, field, ptr, val) \
271 amap_set(ptr, \
272 offsetof(_struct, field)/32, \
273 amap_mask(sizeof(((_struct *)0)->field)), \
274 AMAP_BIT_OFFSET(_struct, field), \
275 val)
276
277static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
278{
279 u32 *dw = (u32 *) ptr;
280 return mask & (*(dw + dw_offset) >> offset);
281}
282
283#define AMAP_GET_BITS(_struct, field, ptr) \
284 amap_get(ptr, \
285 offsetof(_struct, field)/32, \
286 amap_mask(sizeof(((_struct *)0)->field)), \
287 AMAP_BIT_OFFSET(_struct, field))
288
289#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
290#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
291static inline void swap_dws(void *wrb, int len)
292{
293#ifdef __BIG_ENDIAN
294 u32 *dw = wrb;
295 BUG_ON(len % 4);
296 do {
297 *dw = cpu_to_le32(*dw);
298 dw++;
299 len -= 4;
300 } while (len);
301#endif /* __BIG_ENDIAN */
302}
303
304static inline u8 is_tcp_pkt(struct sk_buff *skb)
305{
306 u8 val = 0;
307
308 if (ip_hdr(skb)->version == 4)
309 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
310 else if (ip_hdr(skb)->version == 6)
311 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
312
313 return val;
314}
315
316static inline u8 is_udp_pkt(struct sk_buff *skb)
317{
318 u8 val = 0;
319
320 if (ip_hdr(skb)->version == 4)
321 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
322 else if (ip_hdr(skb)->version == 6)
323 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
324
325 return val;
326}
327
328#endif /* BE_H */
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