diff options
Diffstat (limited to 'drivers/mmc/host/mmci.h')
-rw-r--r-- | drivers/mmc/host/mmci.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index 0f39c490f02..0441bac1c0e 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h | |||
@@ -11,13 +11,23 @@ | |||
11 | #define MCI_PWR_OFF 0x00 | 11 | #define MCI_PWR_OFF 0x00 |
12 | #define MCI_PWR_UP 0x02 | 12 | #define MCI_PWR_UP 0x02 |
13 | #define MCI_PWR_ON 0x03 | 13 | #define MCI_PWR_ON 0x03 |
14 | #define MCI_DATA2DIREN (1 << 2) | ||
15 | #define MCI_CMDDIREN (1 << 3) | ||
16 | #define MCI_DATA0DIREN (1 << 4) | ||
17 | #define MCI_DATA31DIREN (1 << 5) | ||
14 | #define MCI_OD (1 << 6) | 18 | #define MCI_OD (1 << 6) |
15 | #define MCI_ROD (1 << 7) | 19 | #define MCI_ROD (1 << 7) |
20 | /* The ST Micro version does not have ROD */ | ||
21 | #define MCI_FBCLKEN (1 << 7) | ||
22 | #define MCI_DATA74DIREN (1 << 8) | ||
16 | 23 | ||
17 | #define MMCICLOCK 0x004 | 24 | #define MMCICLOCK 0x004 |
18 | #define MCI_CLK_ENABLE (1 << 8) | 25 | #define MCI_CLK_ENABLE (1 << 8) |
19 | #define MCI_CLK_PWRSAVE (1 << 9) | 26 | #define MCI_CLK_PWRSAVE (1 << 9) |
20 | #define MCI_CLK_BYPASS (1 << 10) | 27 | #define MCI_CLK_BYPASS (1 << 10) |
28 | #define MCI_WIDE_BUS (1 << 11) | ||
29 | /* HW flow control on the ST Micro version */ | ||
30 | #define MCI_FCEN (1 << 13) | ||
21 | 31 | ||
22 | #define MMCIARGUMENT 0x008 | 32 | #define MMCIARGUMENT 0x008 |
23 | #define MMCICOMMAND 0x00c | 33 | #define MMCICOMMAND 0x00c |
@@ -26,6 +36,10 @@ | |||
26 | #define MCI_CPSM_INTERRUPT (1 << 8) | 36 | #define MCI_CPSM_INTERRUPT (1 << 8) |
27 | #define MCI_CPSM_PENDING (1 << 9) | 37 | #define MCI_CPSM_PENDING (1 << 9) |
28 | #define MCI_CPSM_ENABLE (1 << 10) | 38 | #define MCI_CPSM_ENABLE (1 << 10) |
39 | #define MCI_SDIO_SUSP (1 << 11) | ||
40 | #define MCI_ENCMD_COMPL (1 << 12) | ||
41 | #define MCI_NIEN (1 << 13) | ||
42 | #define MCI_CE_ATACMD (1 << 14) | ||
29 | 43 | ||
30 | #define MMCIRESPCMD 0x010 | 44 | #define MMCIRESPCMD 0x010 |
31 | #define MMCIRESPONSE0 0x014 | 45 | #define MMCIRESPONSE0 0x014 |
@@ -39,6 +53,11 @@ | |||
39 | #define MCI_DPSM_DIRECTION (1 << 1) | 53 | #define MCI_DPSM_DIRECTION (1 << 1) |
40 | #define MCI_DPSM_MODE (1 << 2) | 54 | #define MCI_DPSM_MODE (1 << 2) |
41 | #define MCI_DPSM_DMAENABLE (1 << 3) | 55 | #define MCI_DPSM_DMAENABLE (1 << 3) |
56 | #define MCI_DPSM_BLOCKSIZE (1 << 4) | ||
57 | #define MCI_DPSM_RWSTART (1 << 8) | ||
58 | #define MCI_DPSM_RWSTOP (1 << 9) | ||
59 | #define MCI_DPSM_RWMOD (1 << 10) | ||
60 | #define MCI_DPSM_SDIOEN (1 << 11) | ||
42 | 61 | ||
43 | #define MMCIDATACNT 0x030 | 62 | #define MMCIDATACNT 0x030 |
44 | #define MMCISTATUS 0x034 | 63 | #define MMCISTATUS 0x034 |
@@ -63,6 +82,8 @@ | |||
63 | #define MCI_RXFIFOEMPTY (1 << 19) | 82 | #define MCI_RXFIFOEMPTY (1 << 19) |
64 | #define MCI_TXDATAAVLBL (1 << 20) | 83 | #define MCI_TXDATAAVLBL (1 << 20) |
65 | #define MCI_RXDATAAVLBL (1 << 21) | 84 | #define MCI_RXDATAAVLBL (1 << 21) |
85 | #define MCI_SDIOIT (1 << 22) | ||
86 | #define MCI_CEATAEND (1 << 23) | ||
66 | 87 | ||
67 | #define MMCICLEAR 0x038 | 88 | #define MMCICLEAR 0x038 |
68 | #define MCI_CMDCRCFAILCLR (1 << 0) | 89 | #define MCI_CMDCRCFAILCLR (1 << 0) |
@@ -75,6 +96,8 @@ | |||
75 | #define MCI_CMDSENTCLR (1 << 7) | 96 | #define MCI_CMDSENTCLR (1 << 7) |
76 | #define MCI_DATAENDCLR (1 << 8) | 97 | #define MCI_DATAENDCLR (1 << 8) |
77 | #define MCI_DATABLOCKENDCLR (1 << 10) | 98 | #define MCI_DATABLOCKENDCLR (1 << 10) |
99 | #define MCI_SDIOITC (1 << 22) | ||
100 | #define MCI_CEATAENDC (1 << 23) | ||
78 | 101 | ||
79 | #define MMCIMASK0 0x03c | 102 | #define MMCIMASK0 0x03c |
80 | #define MCI_CMDCRCFAILMASK (1 << 0) | 103 | #define MCI_CMDCRCFAILMASK (1 << 0) |
@@ -98,6 +121,8 @@ | |||
98 | #define MCI_RXFIFOEMPTYMASK (1 << 19) | 121 | #define MCI_RXFIFOEMPTYMASK (1 << 19) |
99 | #define MCI_TXDATAAVLBLMASK (1 << 20) | 122 | #define MCI_TXDATAAVLBLMASK (1 << 20) |
100 | #define MCI_RXDATAAVLBLMASK (1 << 21) | 123 | #define MCI_RXDATAAVLBLMASK (1 << 21) |
124 | #define MCI_SDIOITMASK (1 << 22) | ||
125 | #define MCI_CEATAENDMASK (1 << 23) | ||
101 | 126 | ||
102 | #define MMCIMASK1 0x040 | 127 | #define MMCIMASK1 0x040 |
103 | #define MMCIFIFOCNT 0x048 | 128 | #define MMCIFIFOCNT 0x048 |
@@ -136,6 +161,9 @@ struct mmci_host { | |||
136 | u32 pwr; | 161 | u32 pwr; |
137 | struct mmc_platform_data *plat; | 162 | struct mmc_platform_data *plat; |
138 | 163 | ||
164 | u8 hw_designer; | ||
165 | u8 hw_revision:4; | ||
166 | |||
139 | struct timer_list timer; | 167 | struct timer_list timer; |
140 | unsigned int oldstat; | 168 | unsigned int oldstat; |
141 | 169 | ||