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path: root/drivers/infiniband/hw/cxgb4/t4.h
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Diffstat (limited to 'drivers/infiniband/hw/cxgb4/t4.h')
-rw-r--r--drivers/infiniband/hw/cxgb4/t4.h76
1 files changed, 37 insertions, 39 deletions
diff --git a/drivers/infiniband/hw/cxgb4/t4.h b/drivers/infiniband/hw/cxgb4/t4.h
index d0e8af35240..1057cb96302 100644
--- a/drivers/infiniband/hw/cxgb4/t4.h
+++ b/drivers/infiniband/hw/cxgb4/t4.h
@@ -41,11 +41,13 @@
41#define T4_MAX_NUM_QP (1<<16) 41#define T4_MAX_NUM_QP (1<<16)
42#define T4_MAX_NUM_CQ (1<<15) 42#define T4_MAX_NUM_CQ (1<<15)
43#define T4_MAX_NUM_PD (1<<15) 43#define T4_MAX_NUM_PD (1<<15)
44#define T4_MAX_PBL_SIZE 256 44#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
45#define T4_MAX_RQ_SIZE 1024 45#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
46#define T4_MAX_SQ_SIZE 1024 46#define T4_MAX_IQ_SIZE (65520 - 1)
47#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE-1) 47#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
48#define T4_MAX_CQ_DEPTH 8192 48#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
49#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
50#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
49#define T4_MAX_NUM_STAG (1<<15) 51#define T4_MAX_NUM_STAG (1<<15)
50#define T4_MAX_MR_SIZE (~0ULL - 1) 52#define T4_MAX_MR_SIZE (~0ULL - 1)
51#define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */ 53#define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
@@ -79,12 +81,11 @@ struct t4_status_page {
79 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) 81 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
80#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ 82#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
81 sizeof(struct fw_ri_immd))) 83 sizeof(struct fw_ri_immd)))
82#define T4_MAX_FR_DEPTH 255 84#define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
83 85
84#define T4_RQ_NUM_SLOTS 2 86#define T4_RQ_NUM_SLOTS 2
85#define T4_RQ_NUM_BYTES (T4_EQ_SIZE * T4_RQ_NUM_SLOTS) 87#define T4_RQ_NUM_BYTES (T4_EQ_SIZE * T4_RQ_NUM_SLOTS)
86#define T4_MAX_RECV_SGE ((T4_RQ_NUM_BYTES - sizeof(struct fw_ri_recv_wr) - \ 88#define T4_MAX_RECV_SGE 4
87 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
88 89
89union t4_wr { 90union t4_wr {
90 struct fw_ri_res_wr res; 91 struct fw_ri_res_wr res;
@@ -434,7 +435,7 @@ struct t4_cq {
434 struct c4iw_rdev *rdev; 435 struct c4iw_rdev *rdev;
435 u64 ugts; 436 u64 ugts;
436 size_t memsize; 437 size_t memsize;
437 u64 timestamp; 438 __be64 bits_type_ts;
438 u32 cqid; 439 u32 cqid;
439 u16 size; /* including status page */ 440 u16 size; /* including status page */
440 u16 cidx; 441 u16 cidx;
@@ -449,25 +450,17 @@ struct t4_cq {
449static inline int t4_arm_cq(struct t4_cq *cq, int se) 450static inline int t4_arm_cq(struct t4_cq *cq, int se)
450{ 451{
451 u32 val; 452 u32 val;
452 u16 inc; 453
453 454 while (cq->cidx_inc > CIDXINC_MASK) {
454 do { 455 val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) |
455 /* 456 INGRESSQID(cq->cqid);
456 * inc must be less the both the max update value -and-
457 * the size of the CQ.
458 */
459 inc = cq->cidx_inc <= CIDXINC_MASK ? cq->cidx_inc :
460 CIDXINC_MASK;
461 inc = inc <= (cq->size - 1) ? inc : (cq->size - 1);
462 if (inc == cq->cidx_inc)
463 val = SEINTARM(se) | CIDXINC(inc) | TIMERREG(6) |
464 INGRESSQID(cq->cqid);
465 else
466 val = SEINTARM(0) | CIDXINC(inc) | TIMERREG(7) |
467 INGRESSQID(cq->cqid);
468 cq->cidx_inc -= inc;
469 writel(val, cq->gts); 457 writel(val, cq->gts);
470 } while (cq->cidx_inc); 458 cq->cidx_inc -= CIDXINC_MASK;
459 }
460 val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) |
461 INGRESSQID(cq->cqid);
462 writel(val, cq->gts);
463 cq->cidx_inc = 0;
471 return 0; 464 return 0;
472} 465}
473 466
@@ -487,7 +480,9 @@ static inline void t4_swcq_consume(struct t4_cq *cq)
487 480
488static inline void t4_hwcq_consume(struct t4_cq *cq) 481static inline void t4_hwcq_consume(struct t4_cq *cq)
489{ 482{
490 cq->cidx_inc++; 483 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
484 if (++cq->cidx_inc == cq->size)
485 cq->cidx_inc = 0;
491 if (++cq->cidx == cq->size) { 486 if (++cq->cidx == cq->size) {
492 cq->cidx = 0; 487 cq->cidx = 0;
493 cq->gen ^= 1; 488 cq->gen ^= 1;
@@ -501,20 +496,23 @@ static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
501 496
502static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe) 497static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
503{ 498{
504 int ret = 0; 499 int ret;
505 u64 bits_type_ts = be64_to_cpu(cq->queue[cq->cidx].bits_type_ts); 500 u16 prev_cidx;
506 501
507 if (G_CQE_GENBIT(bits_type_ts) == cq->gen) { 502 if (cq->cidx == 0)
508 *cqe = &cq->queue[cq->cidx]; 503 prev_cidx = cq->size - 1;
509 cq->timestamp = G_CQE_TS(bits_type_ts);
510 } else if (G_CQE_TS(bits_type_ts) > cq->timestamp)
511 ret = -EOVERFLOW;
512 else 504 else
513 ret = -ENODATA; 505 prev_cidx = cq->cidx - 1;
514 if (ret == -EOVERFLOW) { 506
515 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid); 507 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
508 ret = -EOVERFLOW;
516 cq->error = 1; 509 cq->error = 1;
517 } 510 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
511 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
512 *cqe = &cq->queue[cq->cidx];
513 ret = 0;
514 } else
515 ret = -ENODATA;
518 return ret; 516 return ret;
519} 517}
520 518