aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/ide/cris/ide-cris.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/ide/cris/ide-cris.c')
-rw-r--r--drivers/ide/cris/ide-cris.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/ide/cris/ide-cris.c b/drivers/ide/cris/ide-cris.c
index a62ca75c7e2..9df26855bc0 100644
--- a/drivers/ide/cris/ide-cris.c
+++ b/drivers/ide/cris/ide-cris.c
@@ -88,8 +88,8 @@ enum /* Transfer types */
88int 88int
89cris_ide_ack_intr(ide_hwif_t* hwif) 89cris_ide_ack_intr(ide_hwif_t* hwif)
90{ 90{
91 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, 91 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
92 int, hwif->io_ports[0]); 92 hwif->io_ports.data_addr);
93 REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel); 93 REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel);
94 return 1; 94 return 1;
95} 95}
@@ -231,7 +231,7 @@ cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,
231 ide_hwif_t *hwif = drive->hwif; 231 ide_hwif_t *hwif = drive->hwif;
232 232
233 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, 233 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
234 hwif->io_ports[IDE_DATA_OFFSET]); 234 hwif->io_ports.data_addr);
235 reg_ata_rw_trf_cnt trf_cnt = {0}; 235 reg_ata_rw_trf_cnt trf_cnt = {0};
236 236
237 mycontext.saved_data = (dma_descr_data*)virt_to_phys(d); 237 mycontext.saved_data = (dma_descr_data*)virt_to_phys(d);
@@ -271,7 +271,7 @@ static int cris_dma_test_irq(ide_drive_t *drive)
271 int intr = REG_RD_INT(ata, regi_ata, r_intr); 271 int intr = REG_RD_INT(ata, regi_ata, r_intr);
272 272
273 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int, 273 reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
274 hwif->io_ports[IDE_DATA_OFFSET]); 274 hwif->io_ports.data_addr);
275 275
276 return intr & (1 << ctrl2.sel) ? 1 : 0; 276 return intr & (1 << ctrl2.sel) ? 1 : 0;
277} 277}
@@ -531,7 +531,7 @@ static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int d
531 *R_ATA_CTRL_DATA = 531 *R_ATA_CTRL_DATA =
532 cmd | 532 cmd |
533 IO_FIELD(R_ATA_CTRL_DATA, data, 533 IO_FIELD(R_ATA_CTRL_DATA, data,
534 drive->hwif->io_ports[IDE_DATA_OFFSET]) | 534 drive->hwif->io_ports.data_addr) |
535 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) | 535 IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
536 IO_STATE(R_ATA_CTRL_DATA, multi, on) | 536 IO_STATE(R_ATA_CTRL_DATA, multi, on) |
537 IO_STATE(R_ATA_CTRL_DATA, dma_size, word); 537 IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
@@ -550,7 +550,7 @@ static int cris_dma_test_irq(ide_drive_t *drive)
550{ 550{
551 int intr = *R_IRQ_MASK0_RD; 551 int intr = *R_IRQ_MASK0_RD;
552 int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel, 552 int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel,
553 drive->hwif->io_ports[IDE_DATA_OFFSET]); 553 drive->hwif->io_ports.data_addr);
554 554
555 return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0; 555 return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0;
556} 556}
@@ -644,7 +644,7 @@ cris_ide_inw(unsigned long reg) {
644 * call will also timeout on busy, but as long as the 644 * call will also timeout on busy, but as long as the
645 * write is still performed, everything will be fine. 645 * write is still performed, everything will be fine.
646 */ 646 */
647 if (cris_ide_get_reg(reg) == IDE_STATUS_OFFSET) 647 if (cris_ide_get_reg(reg) == 7)
648 return BUSY_STAT; 648 return BUSY_STAT;
649 else 649 else
650 /* For other rare cases we assume 0 is good enough. */ 650 /* For other rare cases we assume 0 is good enough. */
@@ -765,13 +765,13 @@ static void __init cris_setup_ports(hw_regs_t *hw, unsigned long base)
765 memset(hw, 0, sizeof(*hw)); 765 memset(hw, 0, sizeof(*hw));
766 766
767 for (i = 0; i <= 7; i++) 767 for (i = 0; i <= 7; i++)
768 hw->io_ports[i] = base + cris_ide_reg_addr(i, 0, 1); 768 hw->io_ports_array[i] = base + cris_ide_reg_addr(i, 0, 1);
769 769
770 /* 770 /*
771 * the IDE control register is at ATA address 6, 771 * the IDE control register is at ATA address 6,
772 * with CS1 active instead of CS0 772 * with CS1 active instead of CS0
773 */ 773 */
774 hw->io_ports[IDE_CONTROL_OFFSET] = base + cris_ide_reg_addr(6, 1, 0); 774 hw->io_ports.ctl_addr = base + cris_ide_reg_addr(6, 1, 0);
775 775
776 hw->irq = ide_default_irq(0); 776 hw->irq = ide_default_irq(0);
777 hw->ack_intr = cris_ide_ack_intr; 777 hw->ack_intr = cris_ide_ack_intr;