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path: root/drivers/gpu/drm/radeon/radeon_encoders.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_encoders.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c63
1 files changed, 50 insertions, 13 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index b5dff14ea8c..1ebb100015b 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -254,6 +254,53 @@ radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
254 return dig_connector; 254 return dig_connector;
255} 255}
256 256
257void radeon_panel_mode_fixup(struct drm_encoder *encoder,
258 struct drm_display_mode *adjusted_mode)
259{
260 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
261 struct drm_device *dev = encoder->dev;
262 struct radeon_device *rdev = dev->dev_private;
263 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
264 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
265 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
266 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
267 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
268 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
269 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
270
271 adjusted_mode->clock = native_mode->clock;
272 adjusted_mode->flags = native_mode->flags;
273
274 if (ASIC_IS_AVIVO(rdev)) {
275 adjusted_mode->hdisplay = native_mode->hdisplay;
276 adjusted_mode->vdisplay = native_mode->vdisplay;
277 }
278
279 adjusted_mode->htotal = native_mode->hdisplay + hblank;
280 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
281 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
282
283 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
284 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
285 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
286
287 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
288
289 if (ASIC_IS_AVIVO(rdev)) {
290 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
291 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
292 }
293
294 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
295 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
296 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
297
298 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
299 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
300 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
301
302}
303
257static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 304static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
258 struct drm_display_mode *mode, 305 struct drm_display_mode *mode,
259 struct drm_display_mode *adjusted_mode) 306 struct drm_display_mode *adjusted_mode)
@@ -272,18 +319,8 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
272 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 319 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
273 320
274 /* get the native mode for LVDS */ 321 /* get the native mode for LVDS */
275 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 322 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
276 struct drm_display_mode *native_mode = &radeon_encoder->native_mode; 323 radeon_panel_mode_fixup(encoder, adjusted_mode);
277 int mode_id = adjusted_mode->base.id;
278 *adjusted_mode = *native_mode;
279 if (!ASIC_IS_AVIVO(rdev)) {
280 adjusted_mode->hdisplay = mode->hdisplay;
281 adjusted_mode->vdisplay = mode->vdisplay;
282 adjusted_mode->crtc_hdisplay = mode->hdisplay;
283 adjusted_mode->crtc_vdisplay = mode->vdisplay;
284 }
285 adjusted_mode->base.id = mode_id;
286 }
287 324
288 /* get the native mode for TV */ 325 /* get the native mode for TV */
289 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 326 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
@@ -1321,7 +1358,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1321 1358
1322 radeon_encoder->pixel_clock = adjusted_mode->clock; 1359 radeon_encoder->pixel_clock = adjusted_mode->clock;
1323 1360
1324 if (ASIC_IS_AVIVO(rdev)) { 1361 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1325 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 1362 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1326 atombios_yuv_setup(encoder, true); 1363 atombios_yuv_setup(encoder, true);
1327 else 1364 else