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path: root/drivers/gpu/drm/radeon/radeon_drv.h
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_drv.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h635
1 files changed, 610 insertions, 25 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 490bc7ceef6..ed4d27e6ee6 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -126,6 +126,7 @@ enum radeon_family {
126 CHIP_RV410, 126 CHIP_RV410,
127 CHIP_RS400, 127 CHIP_RS400,
128 CHIP_RS480, 128 CHIP_RS480,
129 CHIP_RS600,
129 CHIP_RS690, 130 CHIP_RS690,
130 CHIP_RS740, 131 CHIP_RS740,
131 CHIP_RV515, 132 CHIP_RV515,
@@ -134,6 +135,16 @@ enum radeon_family {
134 CHIP_RV560, 135 CHIP_RV560,
135 CHIP_RV570, 136 CHIP_RV570,
136 CHIP_R580, 137 CHIP_R580,
138 CHIP_R600,
139 CHIP_RV610,
140 CHIP_RV630,
141 CHIP_RV620,
142 CHIP_RV635,
143 CHIP_RV670,
144 CHIP_RS780,
145 CHIP_RV770,
146 CHIP_RV730,
147 CHIP_RV710,
137 CHIP_LAST, 148 CHIP_LAST,
138}; 149};
139 150
@@ -160,10 +171,6 @@ enum radeon_chip_flags {
160 RADEON_IS_IGPGART = 0x01000000UL, 171 RADEON_IS_IGPGART = 0x01000000UL,
161}; 172};
162 173
163#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
164 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
165#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
166
167typedef struct drm_radeon_freelist { 174typedef struct drm_radeon_freelist {
168 unsigned int age; 175 unsigned int age;
169 struct drm_buf *buf; 176 struct drm_buf *buf;
@@ -221,10 +228,11 @@ struct radeon_virt_surface {
221 u32 upper; 228 u32 upper;
222 u32 flags; 229 u32 flags;
223 struct drm_file *file_priv; 230 struct drm_file *file_priv;
231#define PCIGART_FILE_PRIV ((void *) -1L)
224}; 232};
225 233
226#define RADEON_FLUSH_EMITED (1 < 0) 234#define RADEON_FLUSH_EMITED (1 << 0)
227#define RADEON_PURGE_EMITED (1 < 1) 235#define RADEON_PURGE_EMITED (1 << 1)
228 236
229struct drm_radeon_master_private { 237struct drm_radeon_master_private {
230 drm_local_map_t *sarea; 238 drm_local_map_t *sarea;
@@ -248,7 +256,6 @@ typedef struct drm_radeon_private {
248 drm_radeon_freelist_t *head; 256 drm_radeon_freelist_t *head;
249 drm_radeon_freelist_t *tail; 257 drm_radeon_freelist_t *tail;
250 int last_buf; 258 int last_buf;
251 volatile u32 *scratch;
252 int writeback_works; 259 int writeback_works;
253 260
254 int usec_timeout; 261 int usec_timeout;
@@ -316,11 +323,31 @@ typedef struct drm_radeon_private {
316 323
317 /* starting from here on, data is preserved accross an open */ 324 /* starting from here on, data is preserved accross an open */
318 uint32_t flags; /* see radeon_chip_flags */ 325 uint32_t flags; /* see radeon_chip_flags */
319 unsigned long fb_aper_offset; 326 resource_size_t fb_aper_offset;
320 327
321 int num_gb_pipes; 328 int num_gb_pipes;
322 int track_flush; 329 int track_flush;
323 drm_local_map_t *mmio; 330 drm_local_map_t *mmio;
331
332 /* r6xx/r7xx pipe/shader config */
333 int r600_max_pipes;
334 int r600_max_tile_pipes;
335 int r600_max_simds;
336 int r600_max_backends;
337 int r600_max_gprs;
338 int r600_max_threads;
339 int r600_max_stack_entries;
340 int r600_max_hw_contexts;
341 int r600_max_gs_threads;
342 int r600_sx_max_export_size;
343 int r600_sx_max_export_pos_size;
344 int r600_sx_max_export_smx_size;
345 int r600_sq_num_cf_insts;
346 int r700_sx_num_of_sets;
347 int r700_sc_prim_fifo_size;
348 int r700_sc_hiz_tile_fifo_size;
349 int r700_sc_earlyz_tile_fifo_fize;
350
324} drm_radeon_private_t; 351} drm_radeon_private_t;
325 352
326typedef struct drm_radeon_buf_priv { 353typedef struct drm_radeon_buf_priv {
@@ -338,6 +365,12 @@ extern int radeon_no_wb;
338extern struct drm_ioctl_desc radeon_ioctls[]; 365extern struct drm_ioctl_desc radeon_ioctls[];
339extern int radeon_max_ioctl; 366extern int radeon_max_ioctl;
340 367
368extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
369extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
370
371#define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)
372#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
373
341/* Check whether the given hardware address is inside the framebuffer or the 374/* Check whether the given hardware address is inside the framebuffer or the
342 * GART area. 375 * GART area.
343 */ 376 */
@@ -364,6 +397,9 @@ extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_fi
364extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 397extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
365extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 398extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
366extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 399extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
400extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
401extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
402extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);
367 403
368extern void radeon_freelist_reset(struct drm_device * dev); 404extern void radeon_freelist_reset(struct drm_device * dev);
369extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 405extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
@@ -383,6 +419,10 @@ extern void radeon_mem_takedown(struct mem_block **heap);
383extern void radeon_mem_release(struct drm_file *file_priv, 419extern void radeon_mem_release(struct drm_file *file_priv,
384 struct mem_block *heap); 420 struct mem_block *heap);
385 421
422extern void radeon_enable_bm(struct drm_radeon_private *dev_priv);
423extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off);
424extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val);
425
386 /* radeon_irq.c */ 426 /* radeon_irq.c */
387extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 427extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
388extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 428extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
@@ -423,6 +463,21 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
423 struct drm_file *file_priv, 463 struct drm_file *file_priv,
424 drm_radeon_kcmd_buffer_t *cmdbuf); 464 drm_radeon_kcmd_buffer_t *cmdbuf);
425 465
466/* r600_cp.c */
467extern int r600_do_engine_reset(struct drm_device *dev);
468extern int r600_do_cleanup_cp(struct drm_device *dev);
469extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
470 struct drm_file *file_priv);
471extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv);
472extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv);
473extern void r600_do_cp_start(drm_radeon_private_t *dev_priv);
474extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv);
475extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv);
476extern int r600_cp_dispatch_indirect(struct drm_device *dev,
477 struct drm_buf *buf, int start, int end);
478extern int r600_page_table_init(struct drm_device *dev);
479extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
480
426/* Flags for stats.boxes 481/* Flags for stats.boxes
427 */ 482 */
428#define RADEON_BOX_DMA_IDLE 0x1 483#define RADEON_BOX_DMA_IDLE 0x1
@@ -434,6 +489,8 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
434/* Register definitions, register access macros and drmAddMap constants 489/* Register definitions, register access macros and drmAddMap constants
435 * for Radeon kernel driver. 490 * for Radeon kernel driver.
436 */ 491 */
492#define RADEON_MM_INDEX 0x0000
493#define RADEON_MM_DATA 0x0004
437 494
438#define RADEON_AGP_COMMAND 0x0f60 495#define RADEON_AGP_COMMAND 0x0f60
439#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 496#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
@@ -556,6 +613,56 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
556#define RS690_MC_AGP_BASE 0x102 613#define RS690_MC_AGP_BASE 0x102
557#define RS690_MC_AGP_BASE_2 0x103 614#define RS690_MC_AGP_BASE_2 0x103
558 615
616#define RS600_MC_INDEX 0x70
617# define RS600_MC_ADDR_MASK 0xffff
618# define RS600_MC_IND_SEQ_RBS_0 (1 << 16)
619# define RS600_MC_IND_SEQ_RBS_1 (1 << 17)
620# define RS600_MC_IND_SEQ_RBS_2 (1 << 18)
621# define RS600_MC_IND_SEQ_RBS_3 (1 << 19)
622# define RS600_MC_IND_AIC_RBS (1 << 20)
623# define RS600_MC_IND_CITF_ARB0 (1 << 21)
624# define RS600_MC_IND_CITF_ARB1 (1 << 22)
625# define RS600_MC_IND_WR_EN (1 << 23)
626#define RS600_MC_DATA 0x74
627
628#define RS600_MC_STATUS 0x0
629# define RS600_MC_IDLE (1 << 1)
630#define RS600_MC_FB_LOCATION 0x4
631#define RS600_MC_AGP_LOCATION 0x5
632#define RS600_AGP_BASE 0x6
633#define RS600_AGP_BASE_2 0x7
634#define RS600_MC_CNTL1 0x9
635# define RS600_ENABLE_PAGE_TABLES (1 << 26)
636#define RS600_MC_PT0_CNTL 0x100
637# define RS600_ENABLE_PT (1 << 0)
638# define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15)
639# define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21)
640# define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28)
641# define RS600_INVALIDATE_L2_CACHE (1 << 29)
642#define RS600_MC_PT0_CONTEXT0_CNTL 0x102
643# define RS600_ENABLE_PAGE_TABLE (1 << 0)
644# define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1)
645#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112
646#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114
647#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c
648#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c
649#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c
650#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c
651#define RS600_MC_PT0_CLIENT0_CNTL 0x16c
652# define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0)
653# define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1)
654# define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8)
655# define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8)
656# define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8)
657# define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8)
658# define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8)
659# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10)
660# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10)
661# define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11)
662# define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14)
663# define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
664# define RS600_INVALIDATE_L1_TLB (1 << 20)
665
559#define R520_MC_IND_INDEX 0x70 666#define R520_MC_IND_INDEX 0x70
560#define R520_MC_IND_WR_EN (1 << 24) 667#define R520_MC_IND_WR_EN (1 << 24)
561#define R520_MC_IND_DATA 0x74 668#define R520_MC_IND_DATA 0x74
@@ -580,7 +687,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
580/* pipe config regs */ 687/* pipe config regs */
581#define R400_GB_PIPE_SELECT 0x402c 688#define R400_GB_PIPE_SELECT 0x402c
582#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 689#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
583#define R500_SU_REG_DEST 0x42c8
584#define R300_GB_TILE_CONFIG 0x4018 690#define R300_GB_TILE_CONFIG 0x4018
585# define R300_ENABLE_TILING (1 << 0) 691# define R300_ENABLE_TILING (1 << 0)
586# define R300_PIPE_COUNT_RV350 (0 << 1) 692# define R300_PIPE_COUNT_RV350 (0 << 1)
@@ -639,9 +745,22 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
639 745
640#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 746#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
641 747
642#define GET_SCRATCH( x ) (dev_priv->writeback_works \ 748extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
643 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 749
644 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 750#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
751
752#define R600_SCRATCH_REG0 0x8500
753#define R600_SCRATCH_REG1 0x8504
754#define R600_SCRATCH_REG2 0x8508
755#define R600_SCRATCH_REG3 0x850c
756#define R600_SCRATCH_REG4 0x8510
757#define R600_SCRATCH_REG5 0x8514
758#define R600_SCRATCH_REG6 0x8518
759#define R600_SCRATCH_REG7 0x851c
760#define R600_SCRATCH_UMSK 0x8540
761#define R600_SCRATCH_ADDR 0x8544
762
763#define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x))
645 764
646#define RADEON_GEN_INT_CNTL 0x0040 765#define RADEON_GEN_INT_CNTL 0x0040
647# define RADEON_CRTC_VBLANK_MASK (1 << 0) 766# define RADEON_CRTC_VBLANK_MASK (1 << 0)
@@ -922,6 +1041,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
922#define RADEON_CP_RB_CNTL 0x0704 1041#define RADEON_CP_RB_CNTL 0x0704
923# define RADEON_BUF_SWAP_32BIT (2 << 16) 1042# define RADEON_BUF_SWAP_32BIT (2 << 16)
924# define RADEON_RB_NO_UPDATE (1 << 27) 1043# define RADEON_RB_NO_UPDATE (1 << 27)
1044# define RADEON_RB_RPTR_WR_ENA (1 << 31)
925#define RADEON_CP_RB_RPTR_ADDR 0x070c 1045#define RADEON_CP_RB_RPTR_ADDR 0x070c
926#define RADEON_CP_RB_RPTR 0x0710 1046#define RADEON_CP_RB_RPTR 0x0710
927#define RADEON_CP_RB_WPTR 0x0714 1047#define RADEON_CP_RB_WPTR 0x0714
@@ -983,6 +1103,14 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
983# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 1103# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
984# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 1104# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
985 1105
1106# define R600_IT_INDIRECT_BUFFER 0x00003200
1107# define R600_IT_ME_INITIALIZE 0x00004400
1108# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1109# define R600_IT_EVENT_WRITE 0x00004600
1110# define R600_IT_SET_CONFIG_REG 0x00006800
1111# define R600_SET_CONFIG_REG_OFFSET 0x00008000
1112# define R600_SET_CONFIG_REG_END 0x0000ac00
1113
986#define RADEON_CP_PACKET_MASK 0xC0000000 1114#define RADEON_CP_PACKET_MASK 0xC0000000
987#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 1115#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
988#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 1116#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
@@ -1181,6 +1309,422 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
1181#define R500_D1_VBLANK_INTERRUPT (1 << 4) 1309#define R500_D1_VBLANK_INTERRUPT (1 << 4)
1182#define R500_D2_VBLANK_INTERRUPT (1 << 5) 1310#define R500_D2_VBLANK_INTERRUPT (1 << 5)
1183 1311
1312/* R6xx/R7xx registers */
1313#define R600_MC_VM_FB_LOCATION 0x2180
1314#define R600_MC_VM_AGP_TOP 0x2184
1315#define R600_MC_VM_AGP_BOT 0x2188
1316#define R600_MC_VM_AGP_BASE 0x218c
1317#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
1318#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
1319#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
1320
1321#define R700_MC_VM_FB_LOCATION 0x2024
1322#define R700_MC_VM_AGP_TOP 0x2028
1323#define R700_MC_VM_AGP_BOT 0x202c
1324#define R700_MC_VM_AGP_BASE 0x2030
1325#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
1326#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
1327#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
1328
1329#define R600_MCD_RD_A_CNTL 0x219c
1330#define R600_MCD_RD_B_CNTL 0x21a0
1331
1332#define R600_MCD_WR_A_CNTL 0x21a4
1333#define R600_MCD_WR_B_CNTL 0x21a8
1334
1335#define R600_MCD_RD_SYS_CNTL 0x2200
1336#define R600_MCD_WR_SYS_CNTL 0x2214
1337
1338#define R600_MCD_RD_GFX_CNTL 0x21fc
1339#define R600_MCD_RD_HDP_CNTL 0x2204
1340#define R600_MCD_RD_PDMA_CNTL 0x2208
1341#define R600_MCD_RD_SEM_CNTL 0x220c
1342#define R600_MCD_WR_GFX_CNTL 0x2210
1343#define R600_MCD_WR_HDP_CNTL 0x2218
1344#define R600_MCD_WR_PDMA_CNTL 0x221c
1345#define R600_MCD_WR_SEM_CNTL 0x2220
1346
1347# define R600_MCD_L1_TLB (1 << 0)
1348# define R600_MCD_L1_FRAG_PROC (1 << 1)
1349# define R600_MCD_L1_STRICT_ORDERING (1 << 2)
1350
1351# define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6)
1352# define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
1353# define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
1354# define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
1355# define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
1356
1357# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
1358# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
1359
1360# define R600_MCD_SEMAPHORE_MODE (1 << 10)
1361# define R600_MCD_WAIT_L2_QUERY (1 << 11)
1362# define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12)
1363# define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
1364
1365#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
1366#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
1367#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c
1368
1369#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
1370#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
1371#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c
1372#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
1373
1374# define R700_ENABLE_L1_TLB (1 << 0)
1375# define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
1376# define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
1377# define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
1378# define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15)
1379# define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18)
1380
1381#define R700_MC_ARB_RAMCFG 0x2760
1382# define R700_NOOFBANK_SHIFT 0
1383# define R700_NOOFBANK_MASK 0x3
1384# define R700_NOOFRANK_SHIFT 2
1385# define R700_NOOFRANK_MASK 0x1
1386# define R700_NOOFROWS_SHIFT 3
1387# define R700_NOOFROWS_MASK 0x7
1388# define R700_NOOFCOLS_SHIFT 6
1389# define R700_NOOFCOLS_MASK 0x3
1390# define R700_CHANSIZE_SHIFT 8
1391# define R700_CHANSIZE_MASK 0x1
1392# define R700_BURSTLENGTH_SHIFT 9
1393# define R700_BURSTLENGTH_MASK 0x1
1394#define R600_RAMCFG 0x2408
1395# define R600_NOOFBANK_SHIFT 0
1396# define R600_NOOFBANK_MASK 0x1
1397# define R600_NOOFRANK_SHIFT 1
1398# define R600_NOOFRANK_MASK 0x1
1399# define R600_NOOFROWS_SHIFT 2
1400# define R600_NOOFROWS_MASK 0x7
1401# define R600_NOOFCOLS_SHIFT 5
1402# define R600_NOOFCOLS_MASK 0x3
1403# define R600_CHANSIZE_SHIFT 7
1404# define R600_CHANSIZE_MASK 0x1
1405# define R600_BURSTLENGTH_SHIFT 8
1406# define R600_BURSTLENGTH_MASK 0x1
1407
1408#define R600_VM_L2_CNTL 0x1400
1409# define R600_VM_L2_CACHE_EN (1 << 0)
1410# define R600_VM_L2_FRAG_PROC (1 << 1)
1411# define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9)
1412# define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13)
1413# define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14)
1414
1415#define R600_VM_L2_CNTL2 0x1404
1416# define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0)
1417# define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1)
1418#define R600_VM_L2_CNTL3 0x1408
1419# define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0)
1420# define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5)
1421# define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10)
1422# define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0)
1423# define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6)
1424
1425#define R600_VM_L2_STATUS 0x140c
1426
1427#define R600_VM_CONTEXT0_CNTL 0x1410
1428# define R600_VM_ENABLE_CONTEXT (1 << 0)
1429# define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1)
1430
1431#define R600_VM_CONTEXT0_CNTL2 0x1430
1432#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470
1433#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
1434#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0
1435#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
1436#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
1437#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4
1438
1439#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
1440#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
1441#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c
1442
1443#define R600_HDP_HOST_PATH_CNTL 0x2c00
1444
1445#define R600_GRBM_CNTL 0x8000
1446# define R600_GRBM_READ_TIMEOUT(x) ((x) << 0)
1447
1448#define R600_GRBM_STATUS 0x8010
1449# define R600_CMDFIFO_AVAIL_MASK 0x1f
1450# define R700_CMDFIFO_AVAIL_MASK 0xf
1451# define R600_GUI_ACTIVE (1 << 31)
1452#define R600_GRBM_STATUS2 0x8014
1453#define R600_GRBM_SOFT_RESET 0x8020
1454# define R600_SOFT_RESET_CP (1 << 0)
1455#define R600_WAIT_UNTIL 0x8040
1456
1457#define R600_CP_SEM_WAIT_TIMER 0x85bc
1458#define R600_CP_ME_CNTL 0x86d8
1459# define R600_CP_ME_HALT (1 << 28)
1460#define R600_CP_QUEUE_THRESHOLDS 0x8760
1461# define R600_ROQ_IB1_START(x) ((x) << 0)
1462# define R600_ROQ_IB2_START(x) ((x) << 8)
1463#define R600_CP_MEQ_THRESHOLDS 0x8764
1464# define R700_STQ_SPLIT(x) ((x) << 0)
1465# define R600_MEQ_END(x) ((x) << 16)
1466# define R600_ROQ_END(x) ((x) << 24)
1467#define R600_CP_PERFMON_CNTL 0x87fc
1468#define R600_CP_RB_BASE 0xc100
1469#define R600_CP_RB_CNTL 0xc104
1470# define R600_RB_BUFSZ(x) ((x) << 0)
1471# define R600_RB_BLKSZ(x) ((x) << 8)
1472# define R600_RB_NO_UPDATE (1 << 27)
1473# define R600_RB_RPTR_WR_ENA (1 << 31)
1474#define R600_CP_RB_RPTR_WR 0xc108
1475#define R600_CP_RB_RPTR_ADDR 0xc10c
1476#define R600_CP_RB_RPTR_ADDR_HI 0xc110
1477#define R600_CP_RB_WPTR 0xc114
1478#define R600_CP_RB_WPTR_ADDR 0xc118
1479#define R600_CP_RB_WPTR_ADDR_HI 0xc11c
1480#define R600_CP_RB_RPTR 0x8700
1481#define R600_CP_RB_WPTR_DELAY 0x8704
1482#define R600_CP_PFP_UCODE_ADDR 0xc150
1483#define R600_CP_PFP_UCODE_DATA 0xc154
1484#define R600_CP_ME_RAM_RADDR 0xc158
1485#define R600_CP_ME_RAM_WADDR 0xc15c
1486#define R600_CP_ME_RAM_DATA 0xc160
1487#define R600_CP_DEBUG 0xc1fc
1488
1489#define R600_PA_CL_ENHANCE 0x8a14
1490# define R600_CLIP_VTX_REORDER_ENA (1 << 0)
1491# define R600_NUM_CLIP_SEQ(x) ((x) << 1)
1492#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10
1493#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20
1494#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24
1495# define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1496# define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1497#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40
1498#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44
1499#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48
1500#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c
1501# define R600_S0_X(x) ((x) << 0)
1502# define R600_S0_Y(x) ((x) << 4)
1503# define R600_S1_X(x) ((x) << 8)
1504# define R600_S1_Y(x) ((x) << 12)
1505# define R600_S2_X(x) ((x) << 16)
1506# define R600_S2_Y(x) ((x) << 20)
1507# define R600_S3_X(x) ((x) << 24)
1508# define R600_S3_Y(x) ((x) << 28)
1509# define R600_S4_X(x) ((x) << 0)
1510# define R600_S4_Y(x) ((x) << 4)
1511# define R600_S5_X(x) ((x) << 8)
1512# define R600_S5_Y(x) ((x) << 12)
1513# define R600_S6_X(x) ((x) << 16)
1514# define R600_S6_Y(x) ((x) << 20)
1515# define R600_S7_X(x) ((x) << 24)
1516# define R600_S7_Y(x) ((x) << 28)
1517#define R600_PA_SC_FIFO_SIZE 0x8bd0
1518# define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1519# define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8)
1520# define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16)
1521#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc
1522# define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1523# define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
1524# define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
1525#define R600_PA_SC_ENHANCE 0x8bf0
1526# define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1527# define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
1528#define R600_PA_SC_CLIPRECT_RULE 0x2820c
1529#define R700_PA_SC_EDGERULE 0x28230
1530#define R600_PA_SC_LINE_STIPPLE 0x28a0c
1531#define R600_PA_SC_MODE_CNTL 0x28a4c
1532#define R600_PA_SC_AA_CONFIG 0x28c04
1533
1534#define R600_SX_EXPORT_BUFFER_SIZES 0x900c
1535# define R600_COLOR_BUFFER_SIZE(x) ((x) << 0)
1536# define R600_POSITION_BUFFER_SIZE(x) ((x) << 8)
1537# define R600_SMX_BUFFER_SIZE(x) ((x) << 16)
1538#define R600_SX_DEBUG_1 0x9054
1539# define R600_SMX_EVENT_RELEASE (1 << 0)
1540# define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1541#define R700_SX_DEBUG_1 0x9058
1542# define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1543#define R600_SX_MISC 0x28350
1544
1545#define R600_DB_DEBUG 0x9830
1546# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
1547#define R600_DB_WATERMARKS 0x9838
1548# define R600_DEPTH_FREE(x) ((x) << 0)
1549# define R600_DEPTH_FLUSH(x) ((x) << 5)
1550# define R600_DEPTH_PENDING_FREE(x) ((x) << 15)
1551# define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20)
1552#define R700_DB_DEBUG3 0x98b0
1553# define R700_DB_CLK_OFF_DELAY(x) ((x) << 11)
1554#define RV700_DB_DEBUG4 0x9b8c
1555# define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
1556
1557#define R600_VGT_CACHE_INVALIDATION 0x88c4
1558# define R600_CACHE_INVALIDATION(x) ((x) << 0)
1559# define R600_VC_ONLY 0
1560# define R600_TC_ONLY 1
1561# define R600_VC_AND_TC 2
1562# define R700_AUTO_INVLD_EN(x) ((x) << 6)
1563# define R700_NO_AUTO 0
1564# define R700_ES_AUTO 1
1565# define R700_GS_AUTO 2
1566# define R700_ES_AND_GS_AUTO 3
1567#define R600_VGT_GS_PER_ES 0x88c8
1568#define R600_VGT_ES_PER_GS 0x88cc
1569#define R600_VGT_GS_PER_VS 0x88e8
1570#define R600_VGT_GS_VERTEX_REUSE 0x88d4
1571#define R600_VGT_NUM_INSTANCES 0x8974
1572#define R600_VGT_STRMOUT_EN 0x28ab0
1573#define R600_VGT_EVENT_INITIATOR 0x28a90
1574# define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
1575#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58
1576# define R600_VTX_REUSE_DEPTH_MASK 0xff
1577#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c
1578# define R600_DEALLOC_DIST_MASK 0x7f
1579
1580#define R600_CB_COLOR0_BASE 0x28040
1581#define R600_CB_COLOR1_BASE 0x28044
1582#define R600_CB_COLOR2_BASE 0x28048
1583#define R600_CB_COLOR3_BASE 0x2804c
1584#define R600_CB_COLOR4_BASE 0x28050
1585#define R600_CB_COLOR5_BASE 0x28054
1586#define R600_CB_COLOR6_BASE 0x28058
1587#define R600_CB_COLOR7_BASE 0x2805c
1588#define R600_CB_COLOR7_FRAG 0x280fc
1589
1590#define R600_TC_CNTL 0x9608
1591# define R600_TC_L2_SIZE(x) ((x) << 5)
1592# define R600_L2_DISABLE_LATE_HIT (1 << 9)
1593
1594#define R600_ARB_POP 0x2418
1595# define R600_ENABLE_TC128 (1 << 30)
1596#define R600_ARB_GDEC_RD_CNTL 0x246c
1597
1598#define R600_TA_CNTL_AUX 0x9508
1599# define R600_DISABLE_CUBE_WRAP (1 << 0)
1600# define R600_DISABLE_CUBE_ANISO (1 << 1)
1601# define R700_GETLOD_SELECT(x) ((x) << 2)
1602# define R600_SYNC_GRADIENT (1 << 24)
1603# define R600_SYNC_WALKER (1 << 25)
1604# define R600_SYNC_ALIGNER (1 << 26)
1605# define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
1606# define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
1607
1608#define R700_TCP_CNTL 0x9610
1609
1610#define R600_SMX_DC_CTL0 0xa020
1611# define R700_USE_HASH_FUNCTION (1 << 0)
1612# define R700_CACHE_DEPTH(x) ((x) << 1)
1613# define R700_FLUSH_ALL_ON_EVENT (1 << 10)
1614# define R700_STALL_ON_EVENT (1 << 11)
1615#define R700_SMX_EVENT_CTL 0xa02c
1616# define R700_ES_FLUSH_CTL(x) ((x) << 0)
1617# define R700_GS_FLUSH_CTL(x) ((x) << 3)
1618# define R700_ACK_FLUSH_CTL(x) ((x) << 6)
1619# define R700_SYNC_FLUSH_CTL (1 << 8)
1620
1621#define R600_SQ_CONFIG 0x8c00
1622# define R600_VC_ENABLE (1 << 0)
1623# define R600_EXPORT_SRC_C (1 << 1)
1624# define R600_DX9_CONSTS (1 << 2)
1625# define R600_ALU_INST_PREFER_VECTOR (1 << 3)
1626# define R600_DX10_CLAMP (1 << 4)
1627# define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8)
1628# define R600_PS_PRIO(x) ((x) << 24)
1629# define R600_VS_PRIO(x) ((x) << 26)
1630# define R600_GS_PRIO(x) ((x) << 28)
1631# define R600_ES_PRIO(x) ((x) << 30)
1632#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04
1633# define R600_NUM_PS_GPRS(x) ((x) << 0)
1634# define R600_NUM_VS_GPRS(x) ((x) << 16)
1635# define R700_DYN_GPR_ENABLE (1 << 27)
1636# define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
1637#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08
1638# define R600_NUM_GS_GPRS(x) ((x) << 0)
1639# define R600_NUM_ES_GPRS(x) ((x) << 16)
1640#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c
1641# define R600_NUM_PS_THREADS(x) ((x) << 0)
1642# define R600_NUM_VS_THREADS(x) ((x) << 8)
1643# define R600_NUM_GS_THREADS(x) ((x) << 16)
1644# define R600_NUM_ES_THREADS(x) ((x) << 24)
1645#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10
1646# define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0)
1647# define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16)
1648#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14
1649# define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0)
1650# define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16)
1651#define R600_SQ_MS_FIFO_SIZES 0x8cf0
1652# define R600_CACHE_FIFO_SIZE(x) ((x) << 0)
1653# define R600_FETCH_FIFO_HIWATER(x) ((x) << 8)
1654# define R600_DONE_FIFO_HIWATER(x) ((x) << 16)
1655# define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
1656#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0
1657# define R700_SIMDA_RING0(x) ((x) << 0)
1658# define R700_SIMDA_RING1(x) ((x) << 8)
1659# define R700_SIMDB_RING0(x) ((x) << 16)
1660# define R700_SIMDB_RING1(x) ((x) << 24)
1661#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4
1662#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8
1663#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc
1664#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0
1665#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4
1666#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8
1667#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc
1668
1669#define R600_SPI_PS_IN_CONTROL_0 0x286cc
1670# define R600_NUM_INTERP(x) ((x) << 0)
1671# define R600_POSITION_ENA (1 << 8)
1672# define R600_POSITION_CENTROID (1 << 9)
1673# define R600_POSITION_ADDR(x) ((x) << 10)
1674# define R600_PARAM_GEN(x) ((x) << 15)
1675# define R600_PARAM_GEN_ADDR(x) ((x) << 19)
1676# define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26)
1677# define R600_PERSP_GRADIENT_ENA (1 << 28)
1678# define R600_LINEAR_GRADIENT_ENA (1 << 29)
1679# define R600_POSITION_SAMPLE (1 << 30)
1680# define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
1681#define R600_SPI_PS_IN_CONTROL_1 0x286d0
1682# define R600_GEN_INDEX_PIX (1 << 0)
1683# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)
1684# define R600_FRONT_FACE_ENA (1 << 8)
1685# define R600_FRONT_FACE_CHAN(x) ((x) << 9)
1686# define R600_FRONT_FACE_ALL_BITS (1 << 11)
1687# define R600_FRONT_FACE_ADDR(x) ((x) << 12)
1688# define R600_FOG_ADDR(x) ((x) << 17)
1689# define R600_FIXED_PT_POSITION_ENA (1 << 24)
1690# define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25)
1691# define R700_POSITION_ULC (1 << 30)
1692#define R600_SPI_INPUT_Z 0x286d8
1693
1694#define R600_SPI_CONFIG_CNTL 0x9100
1695# define R600_GPR_WRITE_PRIORITY(x) ((x) << 0)
1696# define R600_DISABLE_INTERP_1 (1 << 5)
1697#define R600_SPI_CONFIG_CNTL_1 0x913c
1698# define R600_VTX_DONE_DELAY(x) ((x) << 0)
1699# define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4)
1700
1701#define R600_GB_TILING_CONFIG 0x98f0
1702# define R600_PIPE_TILING(x) ((x) << 1)
1703# define R600_BANK_TILING(x) ((x) << 4)
1704# define R600_GROUP_SIZE(x) ((x) << 6)
1705# define R600_ROW_TILING(x) ((x) << 8)
1706# define R600_BANK_SWAPS(x) ((x) << 11)
1707# define R600_SAMPLE_SPLIT(x) ((x) << 14)
1708# define R600_BACKEND_MAP(x) ((x) << 16)
1709#define R600_DCP_TILING_CONFIG 0x6ca0
1710#define R600_HDP_TILING_CONFIG 0x2f3c
1711
1712#define R600_CC_RB_BACKEND_DISABLE 0x98f4
1713#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88
1714# define R600_BACKEND_DISABLE(x) ((x) << 16)
1715
1716#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950
1717#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954
1718# define R600_INACTIVE_QD_PIPES(x) ((x) << 8)
1719# define R600_INACTIVE_QD_PIPES_MASK (0xff << 8)
1720# define R600_INACTIVE_SIMDS(x) ((x) << 16)
1721# define R600_INACTIVE_SIMDS_MASK (0xff << 16)
1722
1723#define R700_CGTS_SYS_TCC_DISABLE 0x3f90
1724#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94
1725#define R700_CGTS_TCC_DISABLE 0x9148
1726#define R700_CGTS_USER_TCC_DISABLE 0x914c
1727
1184/* Constants */ 1728/* Constants */
1185#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1729#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1186 1730
@@ -1190,6 +1734,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
1190#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 1734#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1191#define RADEON_LAST_DISPATCH 1 1735#define RADEON_LAST_DISPATCH 1
1192 1736
1737#define R600_LAST_FRAME_REG R600_SCRATCH_REG0
1738#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1
1739#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2
1740#define R600_LAST_SWI_REG R600_SCRATCH_REG3
1741
1193#define RADEON_MAX_VB_AGE 0x7fffffff 1742#define RADEON_MAX_VB_AGE 0x7fffffff
1194#define RADEON_MAX_VB_VERTS (0xffff) 1743#define RADEON_MAX_VB_VERTS (0xffff)
1195 1744
@@ -1198,7 +1747,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
1198#define RADEON_PCIGART_TABLE_SIZE (32*1024) 1747#define RADEON_PCIGART_TABLE_SIZE (32*1024)
1199 1748
1200#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 1749#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1201#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 1750#define RADEON_WRITE(reg, val) \
1751do { \
1752 if (reg < 0x10000) { \
1753 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1754 } else { \
1755 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1756 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1757 } \
1758} while (0)
1202#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1759#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1203#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1760#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1204 1761
@@ -1238,11 +1795,19 @@ do { \
1238 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1795 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1239} while (0) 1796} while (0)
1240 1797
1798#define RS600_WRITE_MCIND(addr, val) \
1799do { \
1800 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \
1801 RADEON_WRITE(RS600_MC_DATA, val); \
1802} while (0)
1803
1241#define IGP_WRITE_MCIND(addr, val) \ 1804#define IGP_WRITE_MCIND(addr, val) \
1242do { \ 1805do { \
1243 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ 1806 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1244 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ 1807 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
1245 RS690_WRITE_MCIND(addr, val); \ 1808 RS690_WRITE_MCIND(addr, val); \
1809 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \
1810 RS600_WRITE_MCIND(addr, val); \
1246 else \ 1811 else \
1247 RS480_WRITE_MCIND(addr, val); \ 1812 RS480_WRITE_MCIND(addr, val); \
1248} while (0) 1813} while (0)
@@ -1346,7 +1911,11 @@ do { \
1346 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \ 1911 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
1347 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \ 1912 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
1348 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 1913 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1349 int __ret = radeon_do_cp_idle( dev_priv ); \ 1914 int __ret; \
1915 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
1916 __ret = r600_do_cp_idle(dev_priv); \
1917 else \
1918 __ret = radeon_do_cp_idle(dev_priv); \
1350 if ( __ret ) return __ret; \ 1919 if ( __ret ) return __ret; \
1351 sarea_priv->last_dispatch = 0; \ 1920 sarea_priv->last_dispatch = 0; \
1352 radeon_freelist_reset( dev ); \ 1921 radeon_freelist_reset( dev ); \
@@ -1368,21 +1937,40 @@ do { \
1368 OUT_RING( age ); \ 1937 OUT_RING( age ); \
1369} while (0) 1938} while (0)
1370 1939
1940#define R600_DISPATCH_AGE(age) do { \
1941 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
1942 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
1943 OUT_RING(age); \
1944} while (0)
1945
1946#define R600_FRAME_AGE(age) do { \
1947 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
1948 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
1949 OUT_RING(age); \
1950} while (0)
1951
1952#define R600_CLEAR_AGE(age) do { \
1953 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
1954 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
1955 OUT_RING(age); \
1956} while (0)
1957
1371/* ================================================================ 1958/* ================================================================
1372 * Ring control 1959 * Ring control
1373 */ 1960 */
1374 1961
1375#define RADEON_VERBOSE 0 1962#define RADEON_VERBOSE 0
1376 1963
1377#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; 1964#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring;
1378 1965
1379#define BEGIN_RING( n ) do { \ 1966#define BEGIN_RING( n ) do { \
1380 if ( RADEON_VERBOSE ) { \ 1967 if ( RADEON_VERBOSE ) { \
1381 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 1968 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1382 } \ 1969 } \
1383 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 1970 _align_nr = (n + 0xf) & ~0xf; \
1971 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \
1384 COMMIT_RING(); \ 1972 COMMIT_RING(); \
1385 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 1973 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \
1386 } \ 1974 } \
1387 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 1975 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1388 ring = dev_priv->ring.start; \ 1976 ring = dev_priv->ring.start; \
@@ -1399,19 +1987,16 @@ do { \
1399 DRM_ERROR( \ 1987 DRM_ERROR( \
1400 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 1988 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1401 ((dev_priv->ring.tail + _nr) & mask), \ 1989 ((dev_priv->ring.tail + _nr) & mask), \
1402 write, __LINE__); \ 1990 write, __LINE__); \
1403 } else \ 1991 } else \
1404 dev_priv->ring.tail = write; \ 1992 dev_priv->ring.tail = write; \
1405} while (0) 1993} while (0)
1406 1994
1995extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
1996
1407#define COMMIT_RING() do { \ 1997#define COMMIT_RING() do { \
1408 /* Flush writes to ring */ \ 1998 radeon_commit_ring(dev_priv); \
1409 DRM_MEMORYBARRIER(); \ 1999 } while(0)
1410 GET_RING_HEAD( dev_priv ); \
1411 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1412 /* read from PCI bus to ensure correct posting */ \
1413 RADEON_READ( RADEON_CP_RB_RPTR ); \
1414} while (0)
1415 2000
1416#define OUT_RING( x ) do { \ 2001#define OUT_RING( x ) do { \
1417 if ( RADEON_VERBOSE ) { \ 2002 if ( RADEON_VERBOSE ) { \
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 20:14:52 -0500