aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/radeon_combios.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_combios.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index a04b7a6ad95..7b7ea269549 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -913,47 +913,47 @@ radeon_combios_get_tv_info(struct radeon_device *rdev)
913 switch (RBIOS8(tv_info + 7) & 0xf) { 913 switch (RBIOS8(tv_info + 7) & 0xf) {
914 case 1: 914 case 1:
915 tv_std = TV_STD_NTSC; 915 tv_std = TV_STD_NTSC;
916 DRM_INFO("Default TV standard: NTSC\n"); 916 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
917 break; 917 break;
918 case 2: 918 case 2:
919 tv_std = TV_STD_PAL; 919 tv_std = TV_STD_PAL;
920 DRM_INFO("Default TV standard: PAL\n"); 920 DRM_DEBUG_KMS("Default TV standard: PAL\n");
921 break; 921 break;
922 case 3: 922 case 3:
923 tv_std = TV_STD_PAL_M; 923 tv_std = TV_STD_PAL_M;
924 DRM_INFO("Default TV standard: PAL-M\n"); 924 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
925 break; 925 break;
926 case 4: 926 case 4:
927 tv_std = TV_STD_PAL_60; 927 tv_std = TV_STD_PAL_60;
928 DRM_INFO("Default TV standard: PAL-60\n"); 928 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
929 break; 929 break;
930 case 5: 930 case 5:
931 tv_std = TV_STD_NTSC_J; 931 tv_std = TV_STD_NTSC_J;
932 DRM_INFO("Default TV standard: NTSC-J\n"); 932 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
933 break; 933 break;
934 case 6: 934 case 6:
935 tv_std = TV_STD_SCART_PAL; 935 tv_std = TV_STD_SCART_PAL;
936 DRM_INFO("Default TV standard: SCART-PAL\n"); 936 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
937 break; 937 break;
938 default: 938 default:
939 tv_std = TV_STD_NTSC; 939 tv_std = TV_STD_NTSC;
940 DRM_INFO 940 DRM_DEBUG_KMS
941 ("Unknown TV standard; defaulting to NTSC\n"); 941 ("Unknown TV standard; defaulting to NTSC\n");
942 break; 942 break;
943 } 943 }
944 944
945 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 945 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
946 case 0: 946 case 0:
947 DRM_INFO("29.498928713 MHz TV ref clk\n"); 947 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
948 break; 948 break;
949 case 1: 949 case 1:
950 DRM_INFO("28.636360000 MHz TV ref clk\n"); 950 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
951 break; 951 break;
952 case 2: 952 case 2:
953 DRM_INFO("14.318180000 MHz TV ref clk\n"); 953 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
954 break; 954 break;
955 case 3: 955 case 3:
956 DRM_INFO("27.000000000 MHz TV ref clk\n"); 956 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
957 break; 957 break;
958 default: 958 default:
959 break; 959 break;
@@ -1324,7 +1324,7 @@ bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1324 1324
1325 if (tmds_info) { 1325 if (tmds_info) {
1326 ver = RBIOS8(tmds_info); 1326 ver = RBIOS8(tmds_info);
1327 DRM_INFO("DFP table revision: %d\n", ver); 1327 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1328 if (ver == 3) { 1328 if (ver == 3) {
1329 n = RBIOS8(tmds_info + 5) + 1; 1329 n = RBIOS8(tmds_info + 5) + 1;
1330 if (n > 4) 1330 if (n > 4)
@@ -1408,7 +1408,7 @@ bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder
1408 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1408 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1409 if (offset) { 1409 if (offset) {
1410 ver = RBIOS8(offset); 1410 ver = RBIOS8(offset);
1411 DRM_INFO("External TMDS Table revision: %d\n", ver); 1411 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1412 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1412 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1413 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1413 tmds->slave_addr >>= 1; /* 7 bit addressing */
1414 gpio = RBIOS8(offset + 4 + 3); 1414 gpio = RBIOS8(offset + 4 + 3);