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path: root/drivers/gpu/drm/radeon/radeon_asic.h
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index dd903d32940..9a75876e0c3 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -75,6 +75,7 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
75 uint32_t tiling_flags, uint32_t pitch, 75 uint32_t tiling_flags, uint32_t pitch,
76 uint32_t offset, uint32_t obj_size); 76 uint32_t offset, uint32_t obj_size);
77int r100_clear_surface_reg(struct radeon_device *rdev, int reg); 77int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
78void r100_bandwidth_update(struct radeon_device *rdev);
78 79
79static struct radeon_asic r100_asic = { 80static struct radeon_asic r100_asic = {
80 .init = &r100_init, 81 .init = &r100_init,
@@ -106,6 +107,7 @@ static struct radeon_asic r100_asic = {
106 .set_clock_gating = &radeon_legacy_set_clock_gating, 107 .set_clock_gating = &radeon_legacy_set_clock_gating,
107 .set_surface_reg = r100_set_surface_reg, 108 .set_surface_reg = r100_set_surface_reg,
108 .clear_surface_reg = r100_clear_surface_reg, 109 .clear_surface_reg = r100_clear_surface_reg,
110 .bandwidth_update = &r100_bandwidth_update,
109}; 111};
110 112
111 113
@@ -165,6 +167,7 @@ static struct radeon_asic r300_asic = {
165 .set_clock_gating = &radeon_legacy_set_clock_gating, 167 .set_clock_gating = &radeon_legacy_set_clock_gating,
166 .set_surface_reg = r100_set_surface_reg, 168 .set_surface_reg = r100_set_surface_reg,
167 .clear_surface_reg = r100_clear_surface_reg, 169 .clear_surface_reg = r100_clear_surface_reg,
170 .bandwidth_update = &r100_bandwidth_update,
168}; 171};
169 172
170/* 173/*
@@ -204,6 +207,7 @@ static struct radeon_asic r420_asic = {
204 .set_clock_gating = &radeon_atom_set_clock_gating, 207 .set_clock_gating = &radeon_atom_set_clock_gating,
205 .set_surface_reg = r100_set_surface_reg, 208 .set_surface_reg = r100_set_surface_reg,
206 .clear_surface_reg = r100_clear_surface_reg, 209 .clear_surface_reg = r100_clear_surface_reg,
210 .bandwidth_update = &r100_bandwidth_update,
207}; 211};
208 212
209 213
@@ -250,6 +254,7 @@ static struct radeon_asic rs400_asic = {
250 .set_clock_gating = &radeon_legacy_set_clock_gating, 254 .set_clock_gating = &radeon_legacy_set_clock_gating,
251 .set_surface_reg = r100_set_surface_reg, 255 .set_surface_reg = r100_set_surface_reg,
252 .clear_surface_reg = r100_clear_surface_reg, 256 .clear_surface_reg = r100_clear_surface_reg,
257 .bandwidth_update = &r100_bandwidth_update,
253}; 258};
254 259
255 260
@@ -267,6 +272,7 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev);
267int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 272int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
268uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 273uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
269void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 274void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
275void rs600_bandwidth_update(struct radeon_device *rdev);
270static struct radeon_asic rs600_asic = { 276static struct radeon_asic rs600_asic = {
271 .init = &r300_init, 277 .init = &r300_init,
272 .errata = &rs600_errata, 278 .errata = &rs600_errata,
@@ -295,6 +301,7 @@ static struct radeon_asic rs600_asic = {
295 .set_memory_clock = &radeon_atom_set_memory_clock, 301 .set_memory_clock = &radeon_atom_set_memory_clock,
296 .set_pcie_lanes = NULL, 302 .set_pcie_lanes = NULL,
297 .set_clock_gating = &radeon_atom_set_clock_gating, 303 .set_clock_gating = &radeon_atom_set_clock_gating,
304 .bandwidth_update = &rs600_bandwidth_update,
298}; 305};
299 306
300 307
@@ -307,6 +314,7 @@ int rs690_mc_init(struct radeon_device *rdev);
307void rs690_mc_fini(struct radeon_device *rdev); 314void rs690_mc_fini(struct radeon_device *rdev);
308uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 315uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
309void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 316void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
317void rs690_bandwidth_update(struct radeon_device *rdev);
310static struct radeon_asic rs690_asic = { 318static struct radeon_asic rs690_asic = {
311 .init = &r300_init, 319 .init = &r300_init,
312 .errata = &rs690_errata, 320 .errata = &rs690_errata,
@@ -337,6 +345,7 @@ static struct radeon_asic rs690_asic = {
337 .set_clock_gating = &radeon_atom_set_clock_gating, 345 .set_clock_gating = &radeon_atom_set_clock_gating,
338 .set_surface_reg = r100_set_surface_reg, 346 .set_surface_reg = r100_set_surface_reg,
339 .clear_surface_reg = r100_clear_surface_reg, 347 .clear_surface_reg = r100_clear_surface_reg,
348 .bandwidth_update = &rs690_bandwidth_update,
340}; 349};
341 350
342 351
@@ -354,6 +363,7 @@ void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
354void rv515_ring_start(struct radeon_device *rdev); 363void rv515_ring_start(struct radeon_device *rdev);
355uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 364uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
356void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 365void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
366void rv515_bandwidth_update(struct radeon_device *rdev);
357static struct radeon_asic rv515_asic = { 367static struct radeon_asic rv515_asic = {
358 .init = &rv515_init, 368 .init = &rv515_init,
359 .errata = &rv515_errata, 369 .errata = &rv515_errata,
@@ -384,6 +394,7 @@ static struct radeon_asic rv515_asic = {
384 .set_clock_gating = &radeon_atom_set_clock_gating, 394 .set_clock_gating = &radeon_atom_set_clock_gating,
385 .set_surface_reg = r100_set_surface_reg, 395 .set_surface_reg = r100_set_surface_reg,
386 .clear_surface_reg = r100_clear_surface_reg, 396 .clear_surface_reg = r100_clear_surface_reg,
397 .bandwidth_update = &rv515_bandwidth_update,
387}; 398};
388 399
389 400
@@ -394,6 +405,7 @@ void r520_errata(struct radeon_device *rdev);
394void r520_vram_info(struct radeon_device *rdev); 405void r520_vram_info(struct radeon_device *rdev);
395int r520_mc_init(struct radeon_device *rdev); 406int r520_mc_init(struct radeon_device *rdev);
396void r520_mc_fini(struct radeon_device *rdev); 407void r520_mc_fini(struct radeon_device *rdev);
408void r520_bandwidth_update(struct radeon_device *rdev);
397static struct radeon_asic r520_asic = { 409static struct radeon_asic r520_asic = {
398 .init = &rv515_init, 410 .init = &rv515_init,
399 .errata = &r520_errata, 411 .errata = &r520_errata,
@@ -424,6 +436,7 @@ static struct radeon_asic r520_asic = {
424 .set_clock_gating = &radeon_atom_set_clock_gating, 436 .set_clock_gating = &radeon_atom_set_clock_gating,
425 .set_surface_reg = r100_set_surface_reg, 437 .set_surface_reg = r100_set_surface_reg,
426 .clear_surface_reg = r100_clear_surface_reg, 438 .clear_surface_reg = r100_clear_surface_reg,
439 .bandwidth_update = &r520_bandwidth_update,
427}; 440};
428 441
429/* 442/*