diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_ramht.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_ramht.c | 160 |
1 files changed, 160 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_ramht.c b/drivers/gpu/drm/nouveau/nouveau_ramht.c new file mode 100644 index 00000000000..8b27ee5411b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nouveau_ramht.c | |||
@@ -0,0 +1,160 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Red Hat Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * Authors: Ben Skeggs | ||
23 | */ | ||
24 | |||
25 | #include "drmP.h" | ||
26 | |||
27 | #include "nouveau_drv.h" | ||
28 | #include "nouveau_ramht.h" | ||
29 | |||
30 | static uint32_t | ||
31 | nouveau_ramht_hash_handle(struct drm_device *dev, int channel, uint32_t handle) | ||
32 | { | ||
33 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
34 | uint32_t hash = 0; | ||
35 | int i; | ||
36 | |||
37 | NV_DEBUG(dev, "ch%d handle=0x%08x\n", channel, handle); | ||
38 | |||
39 | for (i = 32; i > 0; i -= dev_priv->ramht_bits) { | ||
40 | hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1)); | ||
41 | handle >>= dev_priv->ramht_bits; | ||
42 | } | ||
43 | |||
44 | if (dev_priv->card_type < NV_50) | ||
45 | hash ^= channel << (dev_priv->ramht_bits - 4); | ||
46 | hash <<= 3; | ||
47 | |||
48 | NV_DEBUG(dev, "hash=0x%08x\n", hash); | ||
49 | return hash; | ||
50 | } | ||
51 | |||
52 | static int | ||
53 | nouveau_ramht_entry_valid(struct drm_device *dev, struct nouveau_gpuobj *ramht, | ||
54 | uint32_t offset) | ||
55 | { | ||
56 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
57 | uint32_t ctx = nv_ro32(dev, ramht, (offset + 4)/4); | ||
58 | |||
59 | if (dev_priv->card_type < NV_40) | ||
60 | return ((ctx & NV_RAMHT_CONTEXT_VALID) != 0); | ||
61 | return (ctx != 0); | ||
62 | } | ||
63 | |||
64 | int | ||
65 | nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) | ||
66 | { | ||
67 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
68 | struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem; | ||
69 | struct nouveau_channel *chan = ref->channel; | ||
70 | struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; | ||
71 | uint32_t ctx, co, ho; | ||
72 | |||
73 | if (!ramht) { | ||
74 | NV_ERROR(dev, "No hash table!\n"); | ||
75 | return -EINVAL; | ||
76 | } | ||
77 | |||
78 | if (dev_priv->card_type < NV_40) { | ||
79 | ctx = NV_RAMHT_CONTEXT_VALID | (ref->instance >> 4) | | ||
80 | (chan->id << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) | | ||
81 | (ref->gpuobj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT); | ||
82 | } else | ||
83 | if (dev_priv->card_type < NV_50) { | ||
84 | ctx = (ref->instance >> 4) | | ||
85 | (chan->id << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) | | ||
86 | (ref->gpuobj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT); | ||
87 | } else { | ||
88 | if (ref->gpuobj->engine == NVOBJ_ENGINE_DISPLAY) { | ||
89 | ctx = (ref->instance << 10) | 2; | ||
90 | } else { | ||
91 | ctx = (ref->instance >> 4) | | ||
92 | ((ref->gpuobj->engine << | ||
93 | NV40_RAMHT_CONTEXT_ENGINE_SHIFT)); | ||
94 | } | ||
95 | } | ||
96 | |||
97 | co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle); | ||
98 | do { | ||
99 | if (!nouveau_ramht_entry_valid(dev, ramht, co)) { | ||
100 | NV_DEBUG(dev, | ||
101 | "insert ch%d 0x%08x: h=0x%08x, c=0x%08x\n", | ||
102 | chan->id, co, ref->handle, ctx); | ||
103 | nv_wo32(dev, ramht, (co + 0)/4, ref->handle); | ||
104 | nv_wo32(dev, ramht, (co + 4)/4, ctx); | ||
105 | |||
106 | list_add_tail(&ref->list, &chan->ramht_refs); | ||
107 | instmem->flush(dev); | ||
108 | return 0; | ||
109 | } | ||
110 | NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n", | ||
111 | chan->id, co, nv_ro32(dev, ramht, co/4)); | ||
112 | |||
113 | co += 8; | ||
114 | if (co >= dev_priv->ramht_size) | ||
115 | co = 0; | ||
116 | } while (co != ho); | ||
117 | |||
118 | NV_ERROR(dev, "RAMHT space exhausted. ch=%d\n", chan->id); | ||
119 | return -ENOMEM; | ||
120 | } | ||
121 | |||
122 | void | ||
123 | nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) | ||
124 | { | ||
125 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
126 | struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem; | ||
127 | struct nouveau_channel *chan = ref->channel; | ||
128 | struct nouveau_gpuobj *ramht = chan->ramht ? chan->ramht->gpuobj : NULL; | ||
129 | uint32_t co, ho; | ||
130 | |||
131 | if (!ramht) { | ||
132 | NV_ERROR(dev, "No hash table!\n"); | ||
133 | return; | ||
134 | } | ||
135 | |||
136 | co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle); | ||
137 | do { | ||
138 | if (nouveau_ramht_entry_valid(dev, ramht, co) && | ||
139 | (ref->handle == nv_ro32(dev, ramht, (co/4)))) { | ||
140 | NV_DEBUG(dev, | ||
141 | "remove ch%d 0x%08x: h=0x%08x, c=0x%08x\n", | ||
142 | chan->id, co, ref->handle, | ||
143 | nv_ro32(dev, ramht, (co + 4))); | ||
144 | nv_wo32(dev, ramht, (co + 0)/4, 0x00000000); | ||
145 | nv_wo32(dev, ramht, (co + 4)/4, 0x00000000); | ||
146 | |||
147 | list_del(&ref->list); | ||
148 | instmem->flush(dev); | ||
149 | return; | ||
150 | } | ||
151 | |||
152 | co += 8; | ||
153 | if (co >= dev_priv->ramht_size) | ||
154 | co = 0; | ||
155 | } while (co != ho); | ||
156 | list_del(&ref->list); | ||
157 | |||
158 | NV_ERROR(dev, "RAMHT entry not found. ch=%d, handle=0x%08x\n", | ||
159 | chan->id, ref->handle); | ||
160 | } | ||