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path: root/drivers/gpu/drm/i915/i915_reg.h
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h14
1 files changed, 3 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5cfc68940f1..729d4233b76 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -174,7 +174,9 @@
174 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 174 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
175 */ 175 */
176#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) 176#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
177#define MI_FLUSH_DW MI_INSTR(0x26, 2) /* for GEN6 */ 177#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
178#define MI_INVALIDATE_TLB (1<<18)
179#define MI_INVALIDATE_BSD (1<<7)
178#define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 180#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
179#define MI_BATCH_NON_SECURE (1) 181#define MI_BATCH_NON_SECURE (1)
180#define MI_BATCH_NON_SECURE_I965 (1<<8) 182#define MI_BATCH_NON_SECURE_I965 (1<<8)
@@ -1551,17 +1553,7 @@
1551 1553
1552/* Backlight control */ 1554/* Backlight control */
1553#define BLC_PWM_CTL 0x61254 1555#define BLC_PWM_CTL 0x61254
1554#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1555#define BLC_PWM_CTL2 0x61250 /* 965+ only */ 1556#define BLC_PWM_CTL2 0x61250 /* 965+ only */
1556#define BLM_COMBINATION_MODE (1 << 30)
1557/*
1558 * This is the most significant 15 bits of the number of backlight cycles in a
1559 * complete cycle of the modulated backlight control.
1560 *
1561 * The actual value is this field multiplied by two.
1562 */
1563#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1564#define BLM_LEGACY_MODE (1 << 16)
1565/* 1557/*
1566 * This is the number of cycles out of the backlight modulation cycle for which 1558 * This is the number of cycles out of the backlight modulation cycle for which
1567 * the backlight is on. 1559 * the backlight is on.