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-rw-r--r--arch/arm/mach-s3c24a0/include/mach/irqs.h115
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/map.h78
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/memory.h19
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/regs-clock.h88
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/regs-irq.h25
5 files changed, 325 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c24a0/include/mach/irqs.h b/arch/arm/mach-s3c24a0/include/mach/irqs.h
new file mode 100644
index 00000000000..ae8c0e35978
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/irqs.h
@@ -0,0 +1,115 @@
1/* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11
12#ifndef __ASM_ARCH_24A0_IRQS_H
13#define __ASM_ARCH_24A0_IRQS_H __FILE__
14
15#define IRQ_EINT0t2 S3C2410_IRQ(0) /* 16 */
16/* for generic entry-macro.S */
17#define IRQ_EINT0 IRQ_EINT0t2
18
19#define IRQ_EINT3t6 S3C2410_IRQ(1)
20#define IRQ_EINT7t10 S3C2410_IRQ(2)
21#define IRQ_EINT11t14 S3C2410_IRQ(3)
22#define IRQ_EINT15t18 S3C2410_IRQ(4) /* 20 */
23#define IRQ_TICK S3C2410_IRQ(5)
24#define IRQ_DCTQ S3C2410_IRQ(6)
25#define IRQ_MC S3C2410_IRQ(7)
26#define IRQ_ME S3C2410_IRQ(8) /* 24 */
27#define IRQ_KEYPAD S3C2410_IRQ(9)
28#define IRQ_TIMER0 S3C2410_IRQ(10)
29#define IRQ_TIMER1 S3C2410_IRQ(11)
30#define IRQ_TIMER2 S3C2410_IRQ(12)
31#define IRQ_TIMER3_4 S3C2410_IRQ(13)
32#define IRQ_OS_TIMER IRQ_TIMER3_4
33#define IRQ_LCD S3C2410_IRQ(14)
34#define IRQ_CAM_C S3C2410_IRQ(15)
35#define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */
36#define IRQ_UART0 S3C2410_IRQ(17)
37#define IRQ_CAM_P S3C2410_IRQ(18)
38#define IRQ_MODEM S3C2410_IRQ(19)
39#define IRQ_DMA S3C2410_IRQ(20)
40#define IRQ_SDI S3C2410_IRQ(21)
41#define IRQ_SPI0 S3C2410_IRQ(22)
42#define IRQ_UART1 S3C2410_IRQ(23)
43#define IRQ_AC97_NFLASH S3C2410_IRQ(24) /* 40 */
44#define IRQ_USBD S3C2410_IRQ(25)
45#define IRQ_USBH S3C2410_IRQ(26)
46#define IRQ_IIC S3C2410_IRQ(27)
47#define IRQ_IRDA_MSTICK S3C2410_IRQ(28) /* 44 */
48#define IRQ_VLX_SPI1 S3C2410_IRQ(29)
49#define IRQ_RTC S3C2410_IRQ(30) /* 46 */
50#define IRQ_ADC_PEN S3C2410_IRQ(31)
51
52/* interrupts generated from the external interrupts sources */
53#define IRQ_EINT00 S3C2410_IRQ(32) /* 48 */
54#define IRQ_EINT1 S3C2410_IRQ(33)
55#define IRQ_EINT2 S3C2410_IRQ(34)
56#define IRQ_EINT3 S3C2410_IRQ(35)
57#define IRQ_EINT4 S3C2410_IRQ(36)
58#define IRQ_EINT5 S3C2410_IRQ(37)
59#define IRQ_EINT6 S3C2410_IRQ(38)
60#define IRQ_EINT7 S3C2410_IRQ(39)
61#define IRQ_EINT8 S3C2410_IRQ(40)
62#define IRQ_EINT9 S3C2410_IRQ(41)
63#define IRQ_EINT10 S3C2410_IRQ(42)
64#define IRQ_EINT11 S3C2410_IRQ(43)
65#define IRQ_EINT12 S3C2410_IRQ(44)
66#define IRQ_EINT13 S3C2410_IRQ(45)
67#define IRQ_EINT14 S3C2410_IRQ(46)
68#define IRQ_EINT15 S3C2410_IRQ(47)
69#define IRQ_EINT16 S3C2410_IRQ(48)
70#define IRQ_EINT17 S3C2410_IRQ(49)
71#define IRQ_EINT18 S3C2410_IRQ(50)
72
73/* SUB IRQS */
74#define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */
75#define IRQ_S3CUART_TX0 S3C2410_IRQ(52)
76#define IRQ_S3CUART_ERR0 S3C2410_IRQ(53)
77
78#define IRQ_S3CUART_RX1 S3C2410_IRQ(54)
79#define IRQ_S3CUART_TX1 S3C2410_IRQ(55)
80#define IRQ_S3CUART_ERR1 S3C2410_IRQ(56)
81
82#define IRQ_S3CUART_RX2 (0x0)
83#define IRQ_S3CUART_TX2 (0x0)
84#define IRQ_S3CUART_ERR2 (0x0)
85
86
87#define IRQ_IRDA S3C2410_IRQ(57)
88#define IRQ_MSTICK S3C2410_IRQ(58)
89#define IRQ_RESERVED0 S3C2410_IRQ(59)
90#define IRQ_RESERVED1 S3C2410_IRQ(60)
91#define IRQ_RESERVED2 S3C2410_IRQ(61)
92#define IRQ_TIMER3 S3C2410_IRQ(62)
93#define IRQ_TIMER4 S3C2410_IRQ(63)
94#define IRQ_WDT S3C2410_IRQ(64)
95#define IRQ_BATFLT S3C2410_IRQ(65)
96#define IRQ_POST S3C2410_IRQ(66)
97#define IRQ_DISP_FIFO S3C2410_IRQ(67)
98#define IRQ_PENUP S3C2410_IRQ(68)
99#define IRQ_PENDN S3C2410_IRQ(69)
100#define IRQ_ADC S3C2410_IRQ(70)
101#define IRQ_DISP_FRAME S3C2410_IRQ(71)
102#define IRQ_NFLASH S3C2410_IRQ(72)
103#define IRQ_AC97 S3C2410_IRQ(73)
104#define IRQ_SPI1 S3C2410_IRQ(74)
105#define IRQ_VLX S3C2410_IRQ(75)
106#define IRQ_DMA0 S3C2410_IRQ(76)
107#define IRQ_DMA1 S3C2410_IRQ(77)
108#define IRQ_DMA2 S3C2410_IRQ(78)
109#define IRQ_DMA3 S3C2410_IRQ(79)
110
111#define IRQ_TC (0x0)
112
113#define NR_IRQS (IRQ_DMA3+1)
114
115#endif /* __ASM_ARCH_24A0_IRQS_H */
diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h
new file mode 100644
index 00000000000..65a146fd78e
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/map.h
@@ -0,0 +1,78 @@
1/* linux/arch/arm/mach-s3c24a0/include/mach/map.h
2 *
3 * Copyright 2003,2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24A0 - Memory map definitions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_24A0_MAP_H
15#define __ASM_ARCH_24A0_MAP_H __FILE__
16
17#define S3C24A0_PA_IO_BASE (0x40000000)
18#define S3C24A0_PA_CLKPWR (0x40000000)
19#define S3C24A0_PA_IRQ (0x40200000)
20#define S3C24A0_PA_DMA (0x40400000)
21#define S3C24A0_PA_MEMCTRL (0x40C00000)
22#define S3C24A0_PA_NAND (0x40C00000)
23#define S3C24A0_PA_SROM (0x40C20000)
24#define S3C24A0_PA_SDRAM (0x40C40000)
25#define S3C24A0_PA_BUSM (0x40CE0000)
26#define S3C24A0_PA_USBHOST (0x41000000)
27#define S3C24A0_PA_MODEMIF (0x41180000)
28#define S3C24A0_PA_IRDA (0x41800000)
29#define S3C24A0_PA_TIMER (0x44000000)
30#define S3C24A0_PA_WATCHDOG (0x44100000)
31#define S3C24A0_PA_RTC (0x44200000)
32#define S3C24A0_PA_UART (0x44400000)
33#define S3C24A0_PA_UART0 (S3C24A0_PA_UART)
34#define S3C24A0_PA_UART1 (S3C24A0_PA_UART + 0x4000)
35#define S3C24A0_PA_SPI (0x44500000)
36#define S3C24A0_PA_IIC (0x44600000)
37#define S3C24A0_PA_IIS (0x44700000)
38#define S3C24A0_PA_GPIO (0x44800000)
39#define S3C24A0_PA_KEYIF (0x44900000)
40#define S3C24A0_PA_USBDEV (0x44A00000)
41#define S3C24A0_PA_AC97 (0x45000000)
42#define S3C24A0_PA_ADC (0x45800000)
43#define S3C24A0_PA_SDI (0x46000000)
44#define S3C24A0_PA_MS (0x46100000)
45#define S3C24A0_PA_LCD (0x4A000000)
46#define S3C24A0_PA_VPOST (0x4A100000)
47
48/* physical addresses of all the chip-select areas */
49
50#define S3C24A0_CS0 (0x00000000)
51#define S3C24A0_CS1 (0x04000000)
52#define S3C24A0_CS2 (0x08000000)
53#define S3C24A0_CS3 (0x0C000000)
54#define S3C24A0_CS4 (0x10000000)
55#define S3C24A0_CS5 (0x40000000)
56
57#define S3C24A0_SDRAM_PA (S3C24A0_CS4)
58
59/* Use a single interface for common resources between S3C24XX cpus */
60
61#define S3C24XX_PA_IRQ S3C24A0_PA_IRQ
62#define S3C24XX_PA_MEMCTRL S3C24A0_PA_MEMCTRL
63#define S3C24XX_PA_USBHOST S3C24A0_PA_USBHOST
64#define S3C24XX_PA_DMA S3C24A0_PA_DMA
65#define S3C24XX_PA_CLKPWR S3C24A0_PA_CLKPWR
66#define S3C24XX_PA_LCD S3C24A0_PA_LCD
67#define S3C24XX_PA_UART S3C24A0_PA_UART
68#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER
69#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV
70#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG
71#define S3C24XX_PA_IIC S3C24A0_PA_IIC
72#define S3C24XX_PA_IIS S3C24A0_PA_IIS
73#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO
74#define S3C24XX_PA_RTC S3C24A0_PA_RTC
75#define S3C24XX_PA_ADC S3C24A0_PA_ADC
76#define S3C24XX_PA_SPI S3C24A0_PA_SPI
77
78#endif /* __ASM_ARCH_24A0_MAP_H */
diff --git a/arch/arm/mach-s3c24a0/include/mach/memory.h b/arch/arm/mach-s3c24a0/include/mach/memory.h
new file mode 100644
index 00000000000..585211ca018
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/memory.h
@@ -0,0 +1,19 @@
1/* linux/arch/arm/mach-s3c24a0/include/mach/memory.h
2 * from linux/include/asm-arm/arch-rpc/memory.h
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#ifndef __ASM_ARCH_24A0_MEMORY_H
12#define __ASM_ARCH_24A0_MEMORY_H __FILE__
13
14#define PHYS_OFFSET UL(0x10000000)
15
16#define __virt_to_bus(x) __virt_to_phys(x)
17#define __bus_to_virt(x) __phys_to_virt(x)
18
19#endif
diff --git a/arch/arm/mach-s3c24a0/include/mach/regs-clock.h b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
new file mode 100644
index 00000000000..af2abd756c3
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
@@ -0,0 +1,88 @@
1/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C24A0 clock register definitions
11*/
12
13#ifndef __ASM_ARCH_24A0_REGS_CLOCK_H
14#define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__
15
16#define S3C24A0_MPLLCON S3C2410_CLKREG(0x10)
17#define S3C24A0_UPLLCON S3C2410_CLKREG(0x14)
18#define S3C24A0_CLKCON S3C2410_CLKREG(0x20)
19#define S3C24A0_CLKSRC S3C2410_CLKREG(0x24)
20#define S3C24A0_CLKDIVN S3C2410_CLKREG(0x28)
21
22/* CLKCON register bits */
23
24#define S3C24A0_CLKCON_VLX (1<<29)
25#define S3C24A0_CLKCON_VPOST (1<<28)
26#define S3C24A0_CLKCON_WDT (1<<27) /* reserved */
27#define S3C24A0_CLKCON_MPEGDCTQ (1<<26)
28#define S3C24A0_CLKCON_VPOSTIF (1<<25)
29#define S3C24A0_CLKCON_MPEG4IF (1<<24)
30#define S3C24A0_CLKCON_CAM_UPLL (1<<23)
31#define S3C24A0_CLKCON_LCDC (1<<22)
32#define S3C24A0_CLKCON_CAM_HCLK (1<<21)
33#define S3C24A0_CLKCON_MPEG4 (1<<20)
34#define S3C24A0_CLKCON_KEYPAD (1<<19)
35#define S3C24A0_CLKCON_ADC (1<<18)
36#define S3C24A0_CLKCON_SDI (1<<17)
37#define S3C24A0_CLKCON_MS (1<<16) /* memory stick */
38#define S3C24A0_CLKCON_USBD (1<<15)
39#define S3C24A0_CLKCON_GPIO (1<<14)
40#define S3C24A0_CLKCON_IIS (1<<13)
41#define S3C24A0_CLKCON_IIC (1<<12)
42#define S3C24A0_CLKCON_SPI (1<<11)
43#define S3C24A0_CLKCON_UART1 (1<<10)
44#define S3C24A0_CLKCON_UART0 (1<<9)
45#define S3C24A0_CLKCON_PWMT (1<<8)
46#define S3C24A0_CLKCON_USBH (1<<7)
47#define S3C24A0_CLKCON_AC97 (1<<6)
48#define S3C24A0_CLKCON_IrDA (1<<4)
49#define S3C24A0_CLKCON_IDLE (1<<2)
50#define S3C24A0_CLKCON_MON (1<<1)
51#define S3C24A0_CLKCON_STOP (1<<0)
52
53/* CLKSRC register bits */
54
55#define S3C24A0_CLKSRC_OSC (1<<8) /* CLKSRC */
56#define S3C24A0_CLKSRC_UPLL (1<<7)
57#define S3C24A0_CLKSRC_MPLL (1<<5)
58#define S3C24A0_CLKSRC_EXT (1<<4)
59
60/* Use a single interface with the common code, for s3c24xx */
61
62#define S3C2410_MPLLCON S3C24A0_MPLLCON
63#define S3C2410_UPLLCON S3C24A0_UPLLCON
64#define S3C2410_CLKCON S3C24A0_CLKCON
65#define S3C2410_CLKSLOW S3C24A0_CLKSRC
66#define S3C2410_CLKDIVN S3C24A0_CLKDIVN
67
68#define S3C2410_CLKCON_IDLE S3C24A0_CLKCON_IDLE
69#define S3C2410_CLKCON_POWER S3C24A0_CLKCON_STOP
70#define S3C2410_CLKCON_LCDC S3C24A0_CLKCON_LCDC
71#define S3C2410_CLKCON_USBH S3C24A0_CLKCON_USBH
72#define S3C2410_CLKCON_USBD S3C24A0_CLKCON_USBD
73#define S3C2410_CLKCON_PWMT S3C24A0_CLKCON_PWMT
74#define S3C2410_CLKCON_SDI S3C24A0_CLKCON_SDI
75#define S3C2410_CLKCON_UART0 S3C24A0_CLKCON_UART0
76#define S3C2410_CLKCON_UART1 S3C24A0_CLKCON_UART1
77#define S3C2410_CLKCON_GPIO S3C24A0_CLKCON_GPIO
78#define S3C2410_CLKCON_ADC S3C24A0_CLKCON_ADC
79#define S3C2410_CLKCON_IIC S3C24A0_CLKCON_IIC
80#define S3C2410_CLKCON_IIS S3C24A0_CLKCON_IIS
81#define S3C2410_CLKCON_SPI S3C24A0_CLKCON_SPI
82
83#define S3C2410_CLKSLOW_UCLK_OFF S3C24A0_CLKSRC_UPLL
84#define S3C2410_CLKSLOW_MPLL_OFF S3C24A0_CLKSRC_MPLL
85#define S3C2410_CLKSLOW_SLOW (0xFF)
86#define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1)
87
88#endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s3c24a0/include/mach/regs-irq.h b/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
new file mode 100644
index 00000000000..6086f6f189e
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
@@ -0,0 +1,25 @@
1/* linux/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11
12#ifndef ___ASM_ARCH_24A0_REGS_IRQ_H
13#define ___ASM_ARCH_24A0_REGS_IRQ_H __FILE__
14
15
16#define S3C2410_EINTMASK S3C2410_EINTREG(0x034)
17#define S3C2410_EINTPEND S3C2410_EINTREG(0X038)
18
19#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x034)
20#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X038)
21
22#endif /* __ASM_ARCH_24A0_REGS_IRQ_H */
23
24
25
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 10:43:25 -0500