6 files changed, 88 insertions, 108 deletions

diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 98814e6a598..84acef1d0b3 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -600,7 +600,11 @@ static __init void dm365_evm_init(void)
         /* maybe setup mmc1/etc ... _after_ mmc0 */
         evm_init_cpld();
 
+#ifdef CONFIG_SND_DM365_AIC3X_CODEC
         dm365_init_asp(&dm365_evm_snd_data);
+#elif defined(CONFIG_SND_DM365_VOICE_CODEC)
+        dm365_init_vc(&dm365_evm_snd_data);
+#endif
         dm365_init_rtc();
         dm365_init_ks(&dm365evm_ks_data);
 
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 2f3cad6f940..c29337074ad 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -187,32 +187,28 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
                 .phys_base      = OMAP44XX_MCBSP1_BASE,
                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP1_RX,
                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP1_TX,
-                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
+                .tx_irq         = OMAP44XX_IRQ_MCBSP1,
                 .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP44XX_MCBSP2_BASE,
                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP2_RX,
                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP2_TX,
-                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
+                .tx_irq         = OMAP44XX_IRQ_MCBSP2,
                 .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP44XX_MCBSP3_BASE,
                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP3_RX,
                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP3_TX,
-                .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
+                .tx_irq         = OMAP44XX_IRQ_MCBSP3,
                 .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP44XX_MCBSP4_BASE,
                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP4_RX,
                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP4_TX,
-                .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
+                .tx_irq         = OMAP44XX_IRQ_MCBSP4,
                 .ops            = &omap2_mcbsp_ops,
         },
 };
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index e880524904e..7abecfca0b7 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -30,7 +30,6 @@
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
 #include <mach/regs-sdi.h>
-#include <plat/regs-s3c2412-iis.h>
 #include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
@@ -119,13 +118,11 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
                 .name           = "i2s-sdi",
                 .channels       = MAP(S3C2412_DMAREQSEL_I2SRX),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_I2SRX),
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2412_IISRXD,
         },
         [DMACH_I2S_OUT] = {
                 .name           = "i2s-sdo",
                 .channels       = MAP(S3C2412_DMAREQSEL_I2STX),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_I2STX),
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2412_IISTXD,
         },
         [DMACH_USB_EP1] = {
                 .name           = "usb-ep1",
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 7de903d7c1c..975744f10a5 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -149,6 +149,8 @@
 #define OMAP_MCBSP_REG_WAKEUPEN 0xA8
 #define OMAP_MCBSP_REG_XCCR     0xAC
 #define OMAP_MCBSP_REG_RCCR     0xB0
+#define OMAP_MCBSP_REG_XBUFFSTAT        0xB4
+#define OMAP_MCBSP_REG_RBUFFSTAT        0xB8
 #define OMAP_MCBSP_REG_SSELCR   0xBC
 
 #define OMAP_ST_REG_REV         0x00
@@ -471,6 +473,8 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
+u16 omap_mcbsp_get_tx_delay(unsigned int id);
+u16 omap_mcbsp_get_rx_delay(unsigned int id);
 int omap_mcbsp_get_dma_op_mode(unsigned int id);
 #else
 static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
@@ -479,6 +483,8 @@ static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 { }
 static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
 static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
+static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
+static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
 static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
 #endif
 int omap_mcbsp_request(unsigned int id);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index e1d0440fd4a..7e669c9744d 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -489,7 +489,7 @@ void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 {
         struct omap_mcbsp *mcbsp;
 
-        if (!cpu_is_omap34xx())
+        if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
                 return;
 
         if (!omap_mcbsp_check_valid_id(id)) {
@@ -511,7 +511,7 @@ void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 {
         struct omap_mcbsp *mcbsp;
 
-        if (!cpu_is_omap34xx())
+        if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
                 return;
 
         if (!omap_mcbsp_check_valid_id(id)) {
@@ -560,6 +560,61 @@ u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 }
 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 
+#define MCBSP2_FIFO_SIZE        0x500 /* 1024 + 256 locations */
+#define MCBSP1345_FIFO_SIZE     0x80  /* 128 locations */
+/*
+ * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
+ */
+u16 omap_mcbsp_get_tx_delay(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+        u16 buffstat;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+
+        /* Returns the number of free locations in the buffer */
+        buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
+
+        /* Number of slots are different in McBSP ports */
+        if (mcbsp->id == 2)
+                return MCBSP2_FIFO_SIZE - buffstat;
+        else
+                return MCBSP1345_FIFO_SIZE - buffstat;
+}
+EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
+
+/*
+ * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
+ * to reach the threshold value (when the DMA will be triggered to read it)
+ */
+u16 omap_mcbsp_get_rx_delay(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+        u16 buffstat, threshold;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+
+        /* Returns the number of used locations in the buffer */
+        buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
+        /* RX threshold */
+        threshold = MCBSP_READ(mcbsp, THRSH1);
+
+        /* Return the number of location till we reach the threshold limit */
+        if (threshold <= buffstat)
+                return 0;
+        else
+                return threshold - buffstat;
+}
+EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
+
 /*
  * omap_mcbsp_get_dma_op_mode just return the current configured
  * operating mode for the mcbsp channel
@@ -587,7 +642,7 @@ static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
          * Enable wakup behavior, smart idle and all wakeups
          * REVISIT: some wakeups may be unnecessary
          */
-        if (cpu_is_omap34xx()) {
+        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 u16 syscon;
 
                 syscon = MCBSP_READ(mcbsp, SYSCON);
@@ -610,7 +665,7 @@ static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
         /*
          * Disable wakup behavior, smart idle and all wakeups
          */
-        if (cpu_is_omap34xx()) {
+        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 u16 syscon;
 
                 syscon = MCBSP_READ(mcbsp, SYSCON);
@@ -724,14 +779,17 @@ int omap_mcbsp_request(unsigned int id)
                         goto err_clk_disable;
                 }
 
-                init_completion(&mcbsp->rx_irq_completion);
-                err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
+                if (mcbsp->rx_irq) {
+                        init_completion(&mcbsp->rx_irq_completion);
+                        err = request_irq(mcbsp->rx_irq,
+                                        omap_mcbsp_rx_irq_handler,
                                         0, "McBSP", (void *)mcbsp);
-                if (err != 0) {
-                        dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
-                                        "for McBSP%d\n", mcbsp->rx_irq,
-                                        mcbsp->id);
-                        goto err_free_irq;
+                        if (err != 0) {
+                                dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
+                                                "for McBSP%d\n", mcbsp->rx_irq,
+                                                mcbsp->id);
+                                goto err_free_irq;
+                        }
                 }
         }
 
@@ -781,7 +839,8 @@ void omap_mcbsp_free(unsigned int id)
 
         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
                 /* Free IRQs */
-                free_irq(mcbsp->rx_irq, (void *)mcbsp);
+                if (mcbsp->rx_irq)
+                        free_irq(mcbsp->rx_irq, (void *)mcbsp);
                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
         }
 
@@ -855,7 +914,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
         }
 
-        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 /* Release the transmitter and receiver */
                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
                 w &= ~(tx ? XDISABLE : 0);
@@ -885,7 +944,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 
         /* Reset transmitter */
         tx &= 1;
-        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
                 w |= (tx ? XDISABLE : 0);
                 MCBSP_WRITE(mcbsp, XCCR, w);
@@ -895,7 +954,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 
         /* Reset receiver */
         rx &= 1;
-        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
                 w |= (rx ? RDISABLE : 0);
                 MCBSP_WRITE(mcbsp, RCCR, w);
diff --git a/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h b/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h
deleted file mode 100644
index abf2fbc2eb2..00000000000
--- a/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
- *
- * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2412 IIS register definition
-*/
-
-#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
-#define __ASM_ARCH_REGS_S3C2412_IIS_H
-
-#define S3C2412_IISCON                  (0x00)
-#define S3C2412_IISMOD                  (0x04)
-#define S3C2412_IISFIC                  (0x08)
-#define S3C2412_IISPSR                  (0x0C)
-#define S3C2412_IISTXD                  (0x10)
-#define S3C2412_IISRXD                  (0x14)
-
-#define S3C2412_IISCON_LRINDEX          (1 << 11)
-#define S3C2412_IISCON_TXFIFO_EMPTY     (1 << 10)
-#define S3C2412_IISCON_RXFIFO_EMPTY     (1 << 9)
-#define S3C2412_IISCON_TXFIFO_FULL      (1 << 8)
-#define S3C2412_IISCON_RXFIFO_FULL      (1 << 7)
-#define S3C2412_IISCON_TXDMA_PAUSE      (1 << 6)
-#define S3C2412_IISCON_RXDMA_PAUSE      (1 << 5)
-#define S3C2412_IISCON_TXCH_PAUSE       (1 << 4)
-#define S3C2412_IISCON_RXCH_PAUSE       (1 << 3)
-#define S3C2412_IISCON_TXDMA_ACTIVE     (1 << 2)
-#define S3C2412_IISCON_RXDMA_ACTIVE     (1 << 1)
-#define S3C2412_IISCON_IIS_ACTIVE       (1 << 0)
-
-#define S3C64XX_IISMOD_BLC_16BIT        (0 << 13)
-#define S3C64XX_IISMOD_BLC_8BIT         (1 << 13)
-#define S3C64XX_IISMOD_BLC_24BIT        (2 << 13)
-#define S3C64XX_IISMOD_BLC_MASK         (3 << 13)
-
-#define S3C64XX_IISMOD_IMS_PCLK         (0 << 10)
-#define S3C64XX_IISMOD_IMS_SYSMUX       (1 << 10)
-
-#define S3C2412_IISMOD_MASTER_INTERNAL  (0 << 10)
-#define S3C2412_IISMOD_MASTER_EXTERNAL  (1 << 10)
-#define S3C2412_IISMOD_SLAVE            (2 << 10)
-#define S3C2412_IISMOD_MASTER_MASK      (3 << 10)
-#define S3C2412_IISMOD_MODE_TXONLY      (0 << 8)
-#define S3C2412_IISMOD_MODE_RXONLY      (1 << 8)
-#define S3C2412_IISMOD_MODE_TXRX        (2 << 8)
-#define S3C2412_IISMOD_MODE_MASK        (3 << 8)
-#define S3C2412_IISMOD_LR_LLOW          (0 << 7)
-#define S3C2412_IISMOD_LR_RLOW          (1 << 7)
-#define S3C2412_IISMOD_SDF_IIS          (0 << 5)
-#define S3C2412_IISMOD_SDF_MSB          (1 << 5)
-#define S3C2412_IISMOD_SDF_LSB          (2 << 5)
-#define S3C2412_IISMOD_SDF_MASK         (3 << 5)
-#define S3C2412_IISMOD_RCLK_256FS       (0 << 3)
-#define S3C2412_IISMOD_RCLK_512FS       (1 << 3)
-#define S3C2412_IISMOD_RCLK_384FS       (2 << 3)
-#define S3C2412_IISMOD_RCLK_768FS       (3 << 3)
-#define S3C2412_IISMOD_RCLK_MASK        (3 << 3)
-#define S3C2412_IISMOD_BCLK_32FS        (0 << 1)
-#define S3C2412_IISMOD_BCLK_48FS        (1 << 1)
-#define S3C2412_IISMOD_BCLK_16FS        (2 << 1)
-#define S3C2412_IISMOD_BCLK_24FS        (3 << 1)
-#define S3C2412_IISMOD_BCLK_MASK        (3 << 1)
-#define S3C2412_IISMOD_8BIT             (1 << 0)
-
-#define S3C64XX_IISMOD_CDCLKCON         (1 << 12)
-
-#define S3C2412_IISPSR_PSREN            (1 << 15)
-
-#define S3C2412_IISFIC_TXFLUSH          (1 << 15)
-#define S3C2412_IISFIC_RXFLUSH          (1 << 7)
-#define S3C2412_IISFIC_TXCOUNT(x)       (((x) >>  8) & 0xf)
-#define S3C2412_IISFIC_RXCOUNT(x)       (((x) >>  0) & 0xf)
-
-
-
-#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */
-