diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/blackfin/Kconfig | 1 | ||||
-rw-r--r-- | arch/blackfin/include/asm/time.h | 7 | ||||
-rw-r--r-- | arch/blackfin/kernel/time-ts.c | 4 | ||||
-rw-r--r-- | arch/blackfin/mach-common/cpufreq.c | 155 |
4 files changed, 101 insertions, 66 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index ed339b83f5a..970df5b5c52 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig | |||
@@ -1237,7 +1237,6 @@ config PM_BFIN_WAKE_GP | |||
1237 | endmenu | 1237 | endmenu |
1238 | 1238 | ||
1239 | menu "CPU Frequency scaling" | 1239 | menu "CPU Frequency scaling" |
1240 | depends on !SMP | ||
1241 | 1240 | ||
1242 | source "drivers/cpufreq/Kconfig" | 1241 | source "drivers/cpufreq/Kconfig" |
1243 | 1242 | ||
diff --git a/arch/blackfin/include/asm/time.h b/arch/blackfin/include/asm/time.h index 767b938ccf8..9ca7db844d1 100644 --- a/arch/blackfin/include/asm/time.h +++ b/arch/blackfin/include/asm/time.h | |||
@@ -23,9 +23,7 @@ | |||
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifndef CONFIG_CPU_FREQ | 25 | #ifndef CONFIG_CPU_FREQ |
26 | #define TIME_SCALE 1 | 26 | # define TIME_SCALE 1 |
27 | #define __bfin_cycles_off (0) | ||
28 | #define __bfin_cycles_mod (0) | ||
29 | #else | 27 | #else |
30 | /* | 28 | /* |
31 | * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . | 29 | * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . |
@@ -33,8 +31,11 @@ | |||
33 | * adjust the Core Timer Presale Register. This way we don't lose time. | 31 | * adjust the Core Timer Presale Register. This way we don't lose time. |
34 | */ | 32 | */ |
35 | #define TIME_SCALE 4 | 33 | #define TIME_SCALE 4 |
34 | |||
35 | # ifdef CONFIG_CYCLES_CLOCKSOURCE | ||
36 | extern unsigned long long __bfin_cycles_off; | 36 | extern unsigned long long __bfin_cycles_off; |
37 | extern unsigned int __bfin_cycles_mod; | 37 | extern unsigned int __bfin_cycles_mod; |
38 | # endif | ||
38 | #endif | 39 | #endif |
39 | 40 | ||
40 | #if defined(CONFIG_TICKSOURCE_CORETMR) | 41 | #if defined(CONFIG_TICKSOURCE_CORETMR) |
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c index 41a907596c7..cb7a01d4f00 100644 --- a/arch/blackfin/kernel/time-ts.c +++ b/arch/blackfin/kernel/time-ts.c | |||
@@ -51,7 +51,11 @@ | |||
51 | 51 | ||
52 | static notrace cycle_t bfin_read_cycles(struct clocksource *cs) | 52 | static notrace cycle_t bfin_read_cycles(struct clocksource *cs) |
53 | { | 53 | { |
54 | #ifdef CONFIG_CPU_FREQ | ||
54 | return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod); | 55 | return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod); |
56 | #else | ||
57 | return get_cycles(); | ||
58 | #endif | ||
55 | } | 59 | } |
56 | 60 | ||
57 | static struct clocksource bfin_cs_cycles = { | 61 | static struct clocksource bfin_cs_cycles = { |
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c index 77758289725..5d7f8ab5509 100644 --- a/arch/blackfin/mach-common/cpufreq.c +++ b/arch/blackfin/mach-common/cpufreq.c | |||
@@ -15,6 +15,8 @@ | |||
15 | #include <asm/time.h> | 15 | #include <asm/time.h> |
16 | #include <asm/dpmc.h> | 16 | #include <asm/dpmc.h> |
17 | 17 | ||
18 | #define CPUFREQ_CPU 0 | ||
19 | |||
18 | /* this is the table of CCLK frequencies, in Hz */ | 20 | /* this is the table of CCLK frequencies, in Hz */ |
19 | /* .index is the entry in the auxillary dpm_state_table[] */ | 21 | /* .index is the entry in the auxillary dpm_state_table[] */ |
20 | static struct cpufreq_frequency_table bfin_freq_table[] = { | 22 | static struct cpufreq_frequency_table bfin_freq_table[] = { |
@@ -41,64 +43,114 @@ static struct bfin_dpm_state { | |||
41 | unsigned int tscale; /* change the divider on the core timer interrupt */ | 43 | unsigned int tscale; /* change the divider on the core timer interrupt */ |
42 | } dpm_state_table[3]; | 44 | } dpm_state_table[3]; |
43 | 45 | ||
46 | #if defined(CONFIG_CYCLES_CLOCKSOURCE) | ||
44 | /* | 47 | /* |
45 | normalized to maximum frequncy offset for CYCLES, | 48 | * normalized to maximum frequncy offset for CYCLES, |
46 | used in time-ts cycles clock source, but could be used | 49 | * used in time-ts cycles clock source, but could be used |
47 | somewhere also. | 50 | * somewhere also. |
48 | */ | 51 | */ |
49 | unsigned long long __bfin_cycles_off; | 52 | unsigned long long __bfin_cycles_off; |
50 | unsigned int __bfin_cycles_mod; | 53 | unsigned int __bfin_cycles_mod; |
54 | #endif | ||
51 | 55 | ||
52 | /**************************************************************************/ | 56 | /**************************************************************************/ |
57 | static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk) | ||
58 | { | ||
53 | 59 | ||
54 | static unsigned int bfin_getfreq_khz(unsigned int cpu) | 60 | unsigned long csel, min_cclk; |
61 | int index; | ||
62 | |||
63 | /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */ | ||
64 | #if ANOMALY_05000273 || ANOMALY_05000274 || \ | ||
65 | (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE)) | ||
66 | min_cclk = sclk * 2; | ||
67 | #else | ||
68 | min_cclk = sclk; | ||
69 | #endif | ||
70 | csel = ((bfin_read_PLL_DIV() & CSEL) >> 4); | ||
71 | |||
72 | for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) { | ||
73 | bfin_freq_table[index].frequency = cclk >> index; | ||
74 | dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ | ||
75 | dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1; | ||
76 | |||
77 | pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n", | ||
78 | bfin_freq_table[index].frequency, | ||
79 | dpm_state_table[index].csel, | ||
80 | dpm_state_table[index].tscale); | ||
81 | } | ||
82 | return; | ||
83 | } | ||
84 | |||
85 | static void bfin_adjust_core_timer(void *info) | ||
55 | { | 86 | { |
56 | /* The driver only support single cpu */ | 87 | unsigned int tscale; |
57 | if (cpu != 0) | 88 | unsigned int index = *(unsigned int *)info; |
58 | return -1; | 89 | |
90 | /* we have to adjust the core timer, because it is using cclk */ | ||
91 | tscale = dpm_state_table[index].tscale; | ||
92 | bfin_write_TSCALE(tscale); | ||
93 | return; | ||
94 | } | ||
59 | 95 | ||
96 | static unsigned int bfin_getfreq_khz(unsigned int cpu) | ||
97 | { | ||
98 | /* Both CoreA/B have the same core clock */ | ||
60 | return get_cclk() / 1000; | 99 | return get_cclk() / 1000; |
61 | } | 100 | } |
62 | 101 | ||
63 | 102 | ||
64 | static int bfin_target(struct cpufreq_policy *policy, | 103 | static int bfin_target(struct cpufreq_policy *poli, |
65 | unsigned int target_freq, unsigned int relation) | 104 | unsigned int target_freq, unsigned int relation) |
66 | { | 105 | { |
67 | unsigned int index, plldiv, tscale; | 106 | unsigned int index, plldiv, cpu; |
68 | unsigned long flags, cclk_hz; | 107 | unsigned long flags, cclk_hz; |
69 | struct cpufreq_freqs freqs; | 108 | struct cpufreq_freqs freqs; |
109 | #if defined(CONFIG_CYCLES_CLOCKSOURCE) | ||
70 | cycles_t cycles; | 110 | cycles_t cycles; |
111 | #endif | ||
71 | 112 | ||
72 | if (cpufreq_frequency_table_target(policy, bfin_freq_table, | 113 | for_each_online_cpu(cpu) { |
73 | target_freq, relation, &index)) | 114 | struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); |
74 | return -EINVAL; | 115 | |
75 | 116 | if (!policy) | |
76 | cclk_hz = bfin_freq_table[index].frequency; | 117 | continue; |
77 | 118 | ||
78 | freqs.old = bfin_getfreq_khz(0); | 119 | if (cpufreq_frequency_table_target(policy, bfin_freq_table, |
79 | freqs.new = cclk_hz; | 120 | target_freq, relation, &index)) |
80 | freqs.cpu = 0; | 121 | return -EINVAL; |
81 | 122 | ||
82 | pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n", | 123 | cclk_hz = bfin_freq_table[index].frequency; |
83 | cclk_hz, target_freq, freqs.old); | 124 | |
84 | 125 | freqs.old = bfin_getfreq_khz(0); | |
85 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | 126 | freqs.new = cclk_hz; |
86 | local_irq_save_hw(flags); | 127 | freqs.cpu = cpu; |
87 | plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel; | 128 | |
88 | tscale = dpm_state_table[index].tscale; | 129 | pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n", |
89 | bfin_write_PLL_DIV(plldiv); | 130 | cclk_hz, target_freq, freqs.old); |
90 | /* we have to adjust the core timer, because it is using cclk */ | 131 | |
91 | bfin_write_TSCALE(tscale); | 132 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); |
92 | cycles = get_cycles(); | 133 | if (cpu == CPUFREQ_CPU) { |
93 | SSYNC(); | 134 | local_irq_save_hw(flags); |
94 | cycles += 10; /* ~10 cycles we lose after get_cycles() */ | 135 | plldiv = (bfin_read_PLL_DIV() & SSEL) | |
95 | __bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index); | 136 | dpm_state_table[index].csel; |
96 | __bfin_cycles_mod = index; | 137 | bfin_write_PLL_DIV(plldiv); |
97 | local_irq_restore_hw(flags); | 138 | on_each_cpu(bfin_adjust_core_timer, &index, 1); |
98 | /* TODO: just test case for cycles clock source, remove later */ | 139 | #if defined(CONFIG_CYCLES_CLOCKSOURCE) |
99 | pr_debug("cpufreq: done\n"); | 140 | cycles = get_cycles(); |
100 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | 141 | SSYNC(); |
142 | cycles += 10; /* ~10 cycles we lose after get_cycles() */ | ||
143 | __bfin_cycles_off += | ||
144 | (cycles << __bfin_cycles_mod) - (cycles << index); | ||
145 | __bfin_cycles_mod = index; | ||
146 | #endif | ||
147 | local_irq_restore_hw(flags); | ||
148 | } | ||
149 | /* TODO: just test case for cycles clock source, remove later */ | ||
150 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | ||
151 | } | ||
101 | 152 | ||
153 | pr_debug("cpufreq: done\n"); | ||
102 | return 0; | 154 | return 0; |
103 | } | 155 | } |
104 | 156 | ||
@@ -110,37 +162,16 @@ static int bfin_verify_speed(struct cpufreq_policy *policy) | |||
110 | static int __init __bfin_cpu_init(struct cpufreq_policy *policy) | 162 | static int __init __bfin_cpu_init(struct cpufreq_policy *policy) |
111 | { | 163 | { |
112 | 164 | ||
113 | unsigned long cclk, sclk, csel, min_cclk; | 165 | unsigned long cclk, sclk; |
114 | int index; | ||
115 | |||
116 | if (policy->cpu != 0) | ||
117 | return -EINVAL; | ||
118 | 166 | ||
119 | cclk = get_cclk() / 1000; | 167 | cclk = get_cclk() / 1000; |
120 | sclk = get_sclk() / 1000; | 168 | sclk = get_sclk() / 1000; |
121 | 169 | ||
122 | #if ANOMALY_05000273 || ANOMALY_05000274 || \ | 170 | if (policy->cpu == CPUFREQ_CPU) |
123 | (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE)) | 171 | bfin_init_tables(cclk, sclk); |
124 | min_cclk = sclk * 2; | ||
125 | #else | ||
126 | min_cclk = sclk; | ||
127 | #endif | ||
128 | csel = ((bfin_read_PLL_DIV() & CSEL) >> 4); | ||
129 | |||
130 | for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) { | ||
131 | bfin_freq_table[index].frequency = cclk >> index; | ||
132 | dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ | ||
133 | dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1; | ||
134 | |||
135 | pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n", | ||
136 | bfin_freq_table[index].frequency, | ||
137 | dpm_state_table[index].csel, | ||
138 | dpm_state_table[index].tscale); | ||
139 | } | ||
140 | 172 | ||
141 | policy->cpuinfo.transition_latency = 50000; /* 50us assumed */ | 173 | policy->cpuinfo.transition_latency = 50000; /* 50us assumed */ |
142 | 174 | ||
143 | /*Now ,only support one cpu */ | ||
144 | policy->cur = cclk; | 175 | policy->cur = cclk; |
145 | cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu); | 176 | cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu); |
146 | return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table); | 177 | return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table); |