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-rw-r--r--arch/x86/Makefile2
-rw-r--r--arch/x86/ia32/ia32entry.S22
-rw-r--r--arch/x86/include/asm/compat.h2
-rw-r--r--arch/x86/include/asm/cpufeature.h4
-rw-r--r--arch/x86/include/asm/hpet.h1
-rw-r--r--arch/x86/kernel/apic/x2apic_uv_x.c6
-rw-r--r--arch/x86/kernel/early-quirks.c18
-rw-r--r--arch/x86/kernel/hpet.c31
8 files changed, 38 insertions, 48 deletions
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 8aa1b59b907..e8c8881351b 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -74,7 +74,7 @@ endif
74 74
75ifdef CONFIG_CC_STACKPROTECTOR 75ifdef CONFIG_CC_STACKPROTECTOR
76 cc_has_sp := $(srctree)/scripts/gcc-x86_$(BITS)-has-stack-protector.sh 76 cc_has_sp := $(srctree)/scripts/gcc-x86_$(BITS)-has-stack-protector.sh
77 ifeq ($(shell $(CONFIG_SHELL) $(cc_has_sp) $(CC) $(biarch)),y) 77 ifeq ($(shell $(CONFIG_SHELL) $(cc_has_sp) $(CC) $(KBUILD_CPPFLAGS) $(biarch)),y)
78 stackp-y := -fstack-protector 78 stackp-y := -fstack-protector
79 KBUILD_CFLAGS += $(stackp-y) 79 KBUILD_CFLAGS += $(stackp-y)
80 else 80 else
diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S
index b86feabed69..518bb99c339 100644
--- a/arch/x86/ia32/ia32entry.S
+++ b/arch/x86/ia32/ia32entry.S
@@ -50,7 +50,12 @@
50 /* 50 /*
51 * Reload arg registers from stack in case ptrace changed them. 51 * Reload arg registers from stack in case ptrace changed them.
52 * We don't reload %eax because syscall_trace_enter() returned 52 * We don't reload %eax because syscall_trace_enter() returned
53 * the value it wants us to use in the table lookup. 53 * the %rax value we should see. Instead, we just truncate that
54 * value to 32 bits again as we did on entry from user mode.
55 * If it's a new value set by user_regset during entry tracing,
56 * this matches the normal truncation of the user-mode value.
57 * If it's -1 to make us punt the syscall, then (u32)-1 is still
58 * an appropriately invalid value.
54 */ 59 */
55 .macro LOAD_ARGS32 offset, _r9=0 60 .macro LOAD_ARGS32 offset, _r9=0
56 .if \_r9 61 .if \_r9
@@ -60,6 +65,7 @@
60 movl \offset+48(%rsp),%edx 65 movl \offset+48(%rsp),%edx
61 movl \offset+56(%rsp),%esi 66 movl \offset+56(%rsp),%esi
62 movl \offset+64(%rsp),%edi 67 movl \offset+64(%rsp),%edi
68 movl %eax,%eax /* zero extension */
63 .endm 69 .endm
64 70
65 .macro CFI_STARTPROC32 simple 71 .macro CFI_STARTPROC32 simple
@@ -153,7 +159,7 @@ ENTRY(ia32_sysenter_target)
153 testl $_TIF_WORK_SYSCALL_ENTRY,TI_flags(%r10) 159 testl $_TIF_WORK_SYSCALL_ENTRY,TI_flags(%r10)
154 CFI_REMEMBER_STATE 160 CFI_REMEMBER_STATE
155 jnz sysenter_tracesys 161 jnz sysenter_tracesys
156 cmpl $(IA32_NR_syscalls-1),%eax 162 cmpq $(IA32_NR_syscalls-1),%rax
157 ja ia32_badsys 163 ja ia32_badsys
158sysenter_do_call: 164sysenter_do_call:
159 IA32_ARG_FIXUP 165 IA32_ARG_FIXUP
@@ -195,7 +201,7 @@ sysexit_from_sys_call:
195 movl $AUDIT_ARCH_I386,%edi /* 1st arg: audit arch */ 201 movl $AUDIT_ARCH_I386,%edi /* 1st arg: audit arch */
196 call audit_syscall_entry 202 call audit_syscall_entry
197 movl RAX-ARGOFFSET(%rsp),%eax /* reload syscall number */ 203 movl RAX-ARGOFFSET(%rsp),%eax /* reload syscall number */
198 cmpl $(IA32_NR_syscalls-1),%eax 204 cmpq $(IA32_NR_syscalls-1),%rax
199 ja ia32_badsys 205 ja ia32_badsys
200 movl %ebx,%edi /* reload 1st syscall arg */ 206 movl %ebx,%edi /* reload 1st syscall arg */
201 movl RCX-ARGOFFSET(%rsp),%esi /* reload 2nd syscall arg */ 207 movl RCX-ARGOFFSET(%rsp),%esi /* reload 2nd syscall arg */
@@ -248,7 +254,7 @@ sysenter_tracesys:
248 call syscall_trace_enter 254 call syscall_trace_enter
249 LOAD_ARGS32 ARGOFFSET /* reload args from stack in case ptrace changed it */ 255 LOAD_ARGS32 ARGOFFSET /* reload args from stack in case ptrace changed it */
250 RESTORE_REST 256 RESTORE_REST
251 cmpl $(IA32_NR_syscalls-1),%eax 257 cmpq $(IA32_NR_syscalls-1),%rax
252 ja int_ret_from_sys_call /* sysenter_tracesys has set RAX(%rsp) */ 258 ja int_ret_from_sys_call /* sysenter_tracesys has set RAX(%rsp) */
253 jmp sysenter_do_call 259 jmp sysenter_do_call
254 CFI_ENDPROC 260 CFI_ENDPROC
@@ -314,7 +320,7 @@ ENTRY(ia32_cstar_target)
314 testl $_TIF_WORK_SYSCALL_ENTRY,TI_flags(%r10) 320 testl $_TIF_WORK_SYSCALL_ENTRY,TI_flags(%r10)
315 CFI_REMEMBER_STATE 321 CFI_REMEMBER_STATE
316 jnz cstar_tracesys 322 jnz cstar_tracesys
317 cmpl $IA32_NR_syscalls-1,%eax 323 cmpq $IA32_NR_syscalls-1,%rax
318 ja ia32_badsys 324 ja ia32_badsys
319cstar_do_call: 325cstar_do_call:
320 IA32_ARG_FIXUP 1 326 IA32_ARG_FIXUP 1
@@ -367,7 +373,7 @@ cstar_tracesys:
367 LOAD_ARGS32 ARGOFFSET, 1 /* reload args from stack in case ptrace changed it */ 373 LOAD_ARGS32 ARGOFFSET, 1 /* reload args from stack in case ptrace changed it */
368 RESTORE_REST 374 RESTORE_REST
369 xchgl %ebp,%r9d 375 xchgl %ebp,%r9d
370 cmpl $(IA32_NR_syscalls-1),%eax 376 cmpq $(IA32_NR_syscalls-1),%rax
371 ja int_ret_from_sys_call /* cstar_tracesys has set RAX(%rsp) */ 377 ja int_ret_from_sys_call /* cstar_tracesys has set RAX(%rsp) */
372 jmp cstar_do_call 378 jmp cstar_do_call
373END(ia32_cstar_target) 379END(ia32_cstar_target)
@@ -425,7 +431,7 @@ ENTRY(ia32_syscall)
425 orl $TS_COMPAT,TI_status(%r10) 431 orl $TS_COMPAT,TI_status(%r10)
426 testl $_TIF_WORK_SYSCALL_ENTRY,TI_flags(%r10) 432 testl $_TIF_WORK_SYSCALL_ENTRY,TI_flags(%r10)
427 jnz ia32_tracesys 433 jnz ia32_tracesys
428 cmpl $(IA32_NR_syscalls-1),%eax 434 cmpq $(IA32_NR_syscalls-1),%rax
429 ja ia32_badsys 435 ja ia32_badsys
430ia32_do_call: 436ia32_do_call:
431 IA32_ARG_FIXUP 437 IA32_ARG_FIXUP
@@ -444,7 +450,7 @@ ia32_tracesys:
444 call syscall_trace_enter 450 call syscall_trace_enter
445 LOAD_ARGS32 ARGOFFSET /* reload args from stack in case ptrace changed it */ 451 LOAD_ARGS32 ARGOFFSET /* reload args from stack in case ptrace changed it */
446 RESTORE_REST 452 RESTORE_REST
447 cmpl $(IA32_NR_syscalls-1),%eax 453 cmpq $(IA32_NR_syscalls-1),%rax
448 ja int_ret_from_sys_call /* ia32_tracesys has set RAX(%rsp) */ 454 ja int_ret_from_sys_call /* ia32_tracesys has set RAX(%rsp) */
449 jmp ia32_do_call 455 jmp ia32_do_call
450END(ia32_syscall) 456END(ia32_syscall)
diff --git a/arch/x86/include/asm/compat.h b/arch/x86/include/asm/compat.h
index 306160e58b4..1d9cd27c292 100644
--- a/arch/x86/include/asm/compat.h
+++ b/arch/x86/include/asm/compat.h
@@ -205,7 +205,7 @@ static inline compat_uptr_t ptr_to_compat(void __user *uptr)
205 return (u32)(unsigned long)uptr; 205 return (u32)(unsigned long)uptr;
206} 206}
207 207
208static inline void __user *compat_alloc_user_space(long len) 208static inline void __user *arch_compat_alloc_user_space(long len)
209{ 209{
210 struct pt_regs *regs = task_pt_regs(current); 210 struct pt_regs *regs = task_pt_regs(current);
211 return (void __user *)regs->sp - len; 211 return (void __user *)regs->sp - len;
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 781a50b29a4..c6fbb7b430d 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -296,6 +296,7 @@ extern const char * const x86_power_flags[32];
296 296
297#endif /* CONFIG_X86_64 */ 297#endif /* CONFIG_X86_64 */
298 298
299#if __GNUC__ >= 4
299/* 300/*
300 * Static testing of CPU features. Used the same as boot_cpu_has(). 301 * Static testing of CPU features. Used the same as boot_cpu_has().
301 * These are only valid after alternatives have run, but will statically 302 * These are only valid after alternatives have run, but will statically
@@ -304,7 +305,7 @@ extern const char * const x86_power_flags[32];
304 */ 305 */
305static __always_inline __pure bool __static_cpu_has(u16 bit) 306static __always_inline __pure bool __static_cpu_has(u16 bit)
306{ 307{
307#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) 308#if __GNUC__ > 4 || __GNUC_MINOR__ >= 5
308 asm goto("1: jmp %l[t_no]\n" 309 asm goto("1: jmp %l[t_no]\n"
309 "2:\n" 310 "2:\n"
310 ".section .altinstructions,\"a\"\n" 311 ".section .altinstructions,\"a\"\n"
@@ -345,7 +346,6 @@ static __always_inline __pure bool __static_cpu_has(u16 bit)
345#endif 346#endif
346} 347}
347 348
348#if __GNUC__ >= 4
349#define static_cpu_has(bit) \ 349#define static_cpu_has(bit) \
350( \ 350( \
351 __builtin_constant_p(boot_cpu_has(bit)) ? \ 351 __builtin_constant_p(boot_cpu_has(bit)) ? \
diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h
index 004e6e25e91..1d5c08a1bdf 100644
--- a/arch/x86/include/asm/hpet.h
+++ b/arch/x86/include/asm/hpet.h
@@ -68,7 +68,6 @@ extern unsigned long force_hpet_address;
68extern u8 hpet_blockid; 68extern u8 hpet_blockid;
69extern int hpet_force_user; 69extern int hpet_force_user;
70extern u8 hpet_msi_disable; 70extern u8 hpet_msi_disable;
71extern u8 hpet_readback_cmp;
72extern int is_hpet_enabled(void); 71extern int is_hpet_enabled(void);
73extern int hpet_enable(void); 72extern int hpet_enable(void);
74extern void hpet_disable(void); 73extern void hpet_disable(void);
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 7b598b84c90..f744f54cb24 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -698,9 +698,11 @@ void __init uv_system_init(void)
698 for (j = 0; j < 64; j++) { 698 for (j = 0; j < 64; j++) {
699 if (!test_bit(j, &present)) 699 if (!test_bit(j, &present))
700 continue; 700 continue;
701 uv_blade_info[blade].pnode = (i * 64 + j); 701 pnode = (i * 64 + j);
702 uv_blade_info[blade].pnode = pnode;
702 uv_blade_info[blade].nr_possible_cpus = 0; 703 uv_blade_info[blade].nr_possible_cpus = 0;
703 uv_blade_info[blade].nr_online_cpus = 0; 704 uv_blade_info[blade].nr_online_cpus = 0;
705 max_pnode = max(pnode, max_pnode);
704 blade++; 706 blade++;
705 } 707 }
706 } 708 }
@@ -738,7 +740,6 @@ void __init uv_system_init(void)
738 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid); 740 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
739 uv_node_to_blade[nid] = blade; 741 uv_node_to_blade[nid] = blade;
740 uv_cpu_to_blade[cpu] = blade; 742 uv_cpu_to_blade[cpu] = blade;
741 max_pnode = max(pnode, max_pnode);
742 } 743 }
743 744
744 /* Add blade/pnode info for nodes without cpus */ 745 /* Add blade/pnode info for nodes without cpus */
@@ -750,7 +751,6 @@ void __init uv_system_init(void)
750 pnode = (paddr >> m_val) & pnode_mask; 751 pnode = (paddr >> m_val) & pnode_mask;
751 blade = boot_pnode_to_blade(pnode); 752 blade = boot_pnode_to_blade(pnode);
752 uv_node_to_blade[nid] = blade; 753 uv_node_to_blade[nid] = blade;
753 max_pnode = max(pnode, max_pnode);
754 } 754 }
755 755
756 map_gru_high(max_pnode); 756 map_gru_high(max_pnode);
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index e5cc7e82e60..ebdb85cf268 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -18,7 +18,6 @@
18#include <asm/apic.h> 18#include <asm/apic.h>
19#include <asm/iommu.h> 19#include <asm/iommu.h>
20#include <asm/gart.h> 20#include <asm/gart.h>
21#include <asm/hpet.h>
22 21
23static void __init fix_hypertransport_config(int num, int slot, int func) 22static void __init fix_hypertransport_config(int num, int slot, int func)
24{ 23{
@@ -192,21 +191,6 @@ static void __init ati_bugs_contd(int num, int slot, int func)
192} 191}
193#endif 192#endif
194 193
195/*
196 * Force the read back of the CMP register in hpet_next_event()
197 * to work around the problem that the CMP register write seems to be
198 * delayed. See hpet_next_event() for details.
199 *
200 * We do this on all SMBUS incarnations for now until we have more
201 * information about the affected chipsets.
202 */
203static void __init ati_hpet_bugs(int num, int slot, int func)
204{
205#ifdef CONFIG_HPET_TIMER
206 hpet_readback_cmp = 1;
207#endif
208}
209
210#define QFLAG_APPLY_ONCE 0x1 194#define QFLAG_APPLY_ONCE 0x1
211#define QFLAG_APPLIED 0x2 195#define QFLAG_APPLIED 0x2
212#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED) 196#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
@@ -236,8 +220,6 @@ static struct chipset early_qrk[] __initdata = {
236 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs }, 220 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
238 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd }, 222 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
239 { PCI_VENDOR_ID_ATI, PCI_ANY_ID,
240 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_hpet_bugs },
241 {} 223 {}
242}; 224};
243 225
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 351f9c0fea1..410fdb3f193 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -35,7 +35,6 @@
35unsigned long hpet_address; 35unsigned long hpet_address;
36u8 hpet_blockid; /* OS timer block num */ 36u8 hpet_blockid; /* OS timer block num */
37u8 hpet_msi_disable; 37u8 hpet_msi_disable;
38u8 hpet_readback_cmp;
39 38
40#ifdef CONFIG_PCI_MSI 39#ifdef CONFIG_PCI_MSI
41static unsigned long hpet_num_timers; 40static unsigned long hpet_num_timers;
@@ -395,23 +394,27 @@ static int hpet_next_event(unsigned long delta,
395 * at that point and we would wait for the next hpet interrupt 394 * at that point and we would wait for the next hpet interrupt
396 * forever. We found out that reading the CMP register back 395 * forever. We found out that reading the CMP register back
397 * forces the transfer so we can rely on the comparison with 396 * forces the transfer so we can rely on the comparison with
398 * the counter register below. 397 * the counter register below. If the read back from the
398 * compare register does not match the value we programmed
399 * then we might have a real hardware problem. We can not do
400 * much about it here, but at least alert the user/admin with
401 * a prominent warning.
399 * 402 *
400 * That works fine on those ATI chipsets, but on newer Intel 403 * An erratum on some chipsets (ICH9,..), results in
401 * chipsets (ICH9...) this triggers due to an erratum: Reading 404 * comparator read immediately following a write returning old
402 * the comparator immediately following a write is returning 405 * value. Workaround for this is to read this value second
403 * the old value. 406 * time, when first read returns old value.
404 * 407 *
405 * We restrict the read back to the affected ATI chipsets (set 408 * In fact the write to the comparator register is delayed up
406 * by quirks) and also run it with hpet=verbose for debugging 409 * to two HPET cycles so the workaround we tried to restrict
407 * purposes. 410 * the readback to those known to be borked ATI chipsets
411 * failed miserably. So we give up on optimizations forever
412 * and penalize all HPET incarnations unconditionally.
408 */ 413 */
409 if (hpet_readback_cmp || hpet_verbose) { 414 if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) {
410 u32 cmp = hpet_readl(HPET_Tn_CMP(timer)); 415 if (hpet_readl(HPET_Tn_CMP(timer)) != cnt)
411
412 if (cmp != cnt)
413 printk_once(KERN_WARNING 416 printk_once(KERN_WARNING
414 "hpet: compare register read back failed.\n"); 417 "hpet: compare register read back failed.\n");
415 } 418 }
416 419
417 return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; 420 return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;