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-rw-r--r--arch/x86/kernel/apic_64.c1390
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diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c
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1/*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17#include <linux/init.h>
18
19#include <linux/mm.h>
20#include <linux/delay.h>
21#include <linux/bootmem.h>
22#include <linux/interrupt.h>
23#include <linux/mc146818rtc.h>
24#include <linux/kernel_stat.h>
25#include <linux/sysdev.h>
26#include <linux/ioport.h>
27#include <linux/clockchips.h>
28#include <linux/acpi_pmtmr.h>
29#include <linux/module.h>
30
31#include <asm/atomic.h>
32#include <asm/smp.h>
33#include <asm/mtrr.h>
34#include <asm/mpspec.h>
35#include <asm/hpet.h>
36#include <asm/pgalloc.h>
37#include <asm/nmi.h>
38#include <asm/idle.h>
39#include <asm/proto.h>
40#include <asm/timex.h>
41#include <asm/apic.h>
42
43#include <mach_ipi.h>
44#include <mach_apic.h>
45
46static int disable_apic_timer __cpuinitdata;
47static int apic_calibrate_pmtmr __initdata;
48int disable_apic;
49
50/* Local APIC timer works in C2 */
51int local_apic_timer_c2_ok;
52EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
53
54/*
55 * Debug level, exported for io_apic.c
56 */
57unsigned int apic_verbosity;
58
59/* Have we found an MP table */
60int smp_found_config;
61
62static struct resource lapic_resource = {
63 .name = "Local APIC",
64 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
65};
66
67static unsigned int calibration_result;
68
69static int lapic_next_event(unsigned long delta,
70 struct clock_event_device *evt);
71static void lapic_timer_setup(enum clock_event_mode mode,
72 struct clock_event_device *evt);
73static void lapic_timer_broadcast(cpumask_t mask);
74static void apic_pm_activate(void);
75
76static struct clock_event_device lapic_clockevent = {
77 .name = "lapic",
78 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
79 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
80 .shift = 32,
81 .set_mode = lapic_timer_setup,
82 .set_next_event = lapic_next_event,
83 .broadcast = lapic_timer_broadcast,
84 .rating = 100,
85 .irq = -1,
86};
87static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
88
89static unsigned long apic_phys;
90
91unsigned long mp_lapic_addr;
92
93/*
94 * Get the LAPIC version
95 */
96static inline int lapic_get_version(void)
97{
98 return GET_APIC_VERSION(apic_read(APIC_LVR));
99}
100
101/*
102 * Check, if the APIC is integrated or a seperate chip
103 */
104static inline int lapic_is_integrated(void)
105{
106 return 1;
107}
108
109/*
110 * Check, whether this is a modern or a first generation APIC
111 */
112static int modern_apic(void)
113{
114 /* AMD systems use old APIC versions, so check the CPU */
115 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
116 boot_cpu_data.x86 >= 0xf)
117 return 1;
118 return lapic_get_version() >= 0x14;
119}
120
121void apic_wait_icr_idle(void)
122{
123 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
124 cpu_relax();
125}
126
127u32 safe_apic_wait_icr_idle(void)
128{
129 u32 send_status;
130 int timeout;
131
132 timeout = 0;
133 do {
134 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
135 if (!send_status)
136 break;
137 udelay(100);
138 } while (timeout++ < 1000);
139
140 return send_status;
141}
142
143/**
144 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
145 */
146void __cpuinit enable_NMI_through_LVT0(void)
147{
148 unsigned int v;
149
150 /* unmask and set to NMI */
151 v = APIC_DM_NMI;
152 apic_write(APIC_LVT0, v);
153}
154
155/**
156 * lapic_get_maxlvt - get the maximum number of local vector table entries
157 */
158int lapic_get_maxlvt(void)
159{
160 unsigned int v, maxlvt;
161
162 v = apic_read(APIC_LVR);
163 maxlvt = GET_APIC_MAXLVT(v);
164 return maxlvt;
165}
166
167/*
168 * This function sets up the local APIC timer, with a timeout of
169 * 'clocks' APIC bus clock. During calibration we actually call
170 * this function twice on the boot CPU, once with a bogus timeout
171 * value, second time for real. The other (noncalibrating) CPUs
172 * call this function only once, with the real, calibrated value.
173 *
174 * We do reads before writes even if unnecessary, to get around the
175 * P5 APIC double write bug.
176 */
177
178static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
179{
180 unsigned int lvtt_value, tmp_value;
181
182 lvtt_value = LOCAL_TIMER_VECTOR;
183 if (!oneshot)
184 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
185 if (!irqen)
186 lvtt_value |= APIC_LVT_MASKED;
187
188 apic_write(APIC_LVTT, lvtt_value);
189
190 /*
191 * Divide PICLK by 16
192 */
193 tmp_value = apic_read(APIC_TDCR);
194 apic_write(APIC_TDCR, (tmp_value
195 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
196 | APIC_TDR_DIV_16);
197
198 if (!oneshot)
199 apic_write(APIC_TMICT, clocks);
200}
201
202/*
203 * Setup extended LVT, AMD specific (K8, family 10h)
204 *
205 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
206 * MCE interrupts are supported. Thus MCE offset must be set to 0.
207 */
208
209#define APIC_EILVT_LVTOFF_MCE 0
210#define APIC_EILVT_LVTOFF_IBS 1
211
212static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
213{
214 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
215 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
216
217 apic_write(reg, v);
218}
219
220u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
221{
222 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
223 return APIC_EILVT_LVTOFF_MCE;
224}
225
226u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
227{
228 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
229 return APIC_EILVT_LVTOFF_IBS;
230}
231
232/*
233 * Program the next event, relative to now
234 */
235static int lapic_next_event(unsigned long delta,
236 struct clock_event_device *evt)
237{
238 apic_write(APIC_TMICT, delta);
239 return 0;
240}
241
242/*
243 * Setup the lapic timer in periodic or oneshot mode
244 */
245static void lapic_timer_setup(enum clock_event_mode mode,
246 struct clock_event_device *evt)
247{
248 unsigned long flags;
249 unsigned int v;
250
251 /* Lapic used as dummy for broadcast ? */
252 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
253 return;
254
255 local_irq_save(flags);
256
257 switch (mode) {
258 case CLOCK_EVT_MODE_PERIODIC:
259 case CLOCK_EVT_MODE_ONESHOT:
260 __setup_APIC_LVTT(calibration_result,
261 mode != CLOCK_EVT_MODE_PERIODIC, 1);
262 break;
263 case CLOCK_EVT_MODE_UNUSED:
264 case CLOCK_EVT_MODE_SHUTDOWN:
265 v = apic_read(APIC_LVTT);
266 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
267 apic_write(APIC_LVTT, v);
268 break;
269 case CLOCK_EVT_MODE_RESUME:
270 /* Nothing to do here */
271 break;
272 }
273
274 local_irq_restore(flags);
275}
276
277/*
278 * Local APIC timer broadcast function
279 */
280static void lapic_timer_broadcast(cpumask_t mask)
281{
282#ifdef CONFIG_SMP
283 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
284#endif
285}
286
287/*
288 * Setup the local APIC timer for this CPU. Copy the initilized values
289 * of the boot CPU and register the clock event in the framework.
290 */
291static void setup_APIC_timer(void)
292{
293 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
294
295 memcpy(levt, &lapic_clockevent, sizeof(*levt));
296 levt->cpumask = cpumask_of_cpu(smp_processor_id());
297
298 clockevents_register_device(levt);
299}
300
301/*
302 * In this function we calibrate APIC bus clocks to the external
303 * timer. Unfortunately we cannot use jiffies and the timer irq
304 * to calibrate, since some later bootup code depends on getting
305 * the first irq? Ugh.
306 *
307 * We want to do the calibration only once since we
308 * want to have local timer irqs syncron. CPUs connected
309 * by the same APIC bus have the very same bus frequency.
310 * And we want to have irqs off anyways, no accidental
311 * APIC irq that way.
312 */
313
314#define TICK_COUNT 100000000
315
316static int __init calibrate_APIC_clock(void)
317{
318 unsigned apic, apic_start;
319 unsigned long tsc, tsc_start;
320 int result;
321
322 local_irq_disable();
323
324 /*
325 * Put whatever arbitrary (but long enough) timeout
326 * value into the APIC clock, we just want to get the
327 * counter running for calibration.
328 *
329 * No interrupt enable !
330 */
331 __setup_APIC_LVTT(250000000, 0, 0);
332
333 apic_start = apic_read(APIC_TMCCT);
334#ifdef CONFIG_X86_PM_TIMER
335 if (apic_calibrate_pmtmr && pmtmr_ioport) {
336 pmtimer_wait(5000); /* 5ms wait */
337 apic = apic_read(APIC_TMCCT);
338 result = (apic_start - apic) * 1000L / 5;
339 } else
340#endif
341 {
342 rdtscll(tsc_start);
343
344 do {
345 apic = apic_read(APIC_TMCCT);
346 rdtscll(tsc);
347 } while ((tsc - tsc_start) < TICK_COUNT &&
348 (apic_start - apic) < TICK_COUNT);
349
350 result = (apic_start - apic) * 1000L * tsc_khz /
351 (tsc - tsc_start);
352 }
353
354 local_irq_enable();
355
356 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
357
358 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
359 result / 1000 / 1000, result / 1000 % 1000);
360
361 /* Calculate the scaled math multiplication factor */
362 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC,
363 lapic_clockevent.shift);
364 lapic_clockevent.max_delta_ns =
365 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
366 lapic_clockevent.min_delta_ns =
367 clockevent_delta2ns(0xF, &lapic_clockevent);
368
369 calibration_result = result / HZ;
370
371 /*
372 * Do a sanity check on the APIC calibration result
373 */
374 if (calibration_result < (1000000 / HZ)) {
375 printk(KERN_WARNING
376 "APIC frequency too slow, disabling apic timer\n");
377 return -1;
378 }
379
380 return 0;
381}
382
383/*
384 * Setup the boot APIC
385 *
386 * Calibrate and verify the result.
387 */
388void __init setup_boot_APIC_clock(void)
389{
390 /*
391 * The local apic timer can be disabled via the kernel commandline.
392 * Register the lapic timer as a dummy clock event source on SMP
393 * systems, so the broadcast mechanism is used. On UP systems simply
394 * ignore it.
395 */
396 if (disable_apic_timer) {
397 printk(KERN_INFO "Disabling APIC timer\n");
398 /* No broadcast on UP ! */
399 if (num_possible_cpus() > 1) {
400 lapic_clockevent.mult = 1;
401 setup_APIC_timer();
402 }
403 return;
404 }
405
406 printk(KERN_INFO "Using local APIC timer interrupts.\n");
407 if (calibrate_APIC_clock()) {
408 /* No broadcast on UP ! */
409 if (num_possible_cpus() > 1)
410 setup_APIC_timer();
411 return;
412 }
413
414 /*
415 * If nmi_watchdog is set to IO_APIC, we need the
416 * PIT/HPET going. Otherwise register lapic as a dummy
417 * device.
418 */
419 if (nmi_watchdog != NMI_IO_APIC)
420 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
421 else
422 printk(KERN_WARNING "APIC timer registered as dummy,"
423 " due to nmi_watchdog=%d!\n", nmi_watchdog);
424
425 setup_APIC_timer();
426}
427
428void __cpuinit setup_secondary_APIC_clock(void)
429{
430 setup_APIC_timer();
431}
432
433/*
434 * The guts of the apic timer interrupt
435 */
436static void local_apic_timer_interrupt(void)
437{
438 int cpu = smp_processor_id();
439 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
440
441 /*
442 * Normally we should not be here till LAPIC has been initialized but
443 * in some cases like kdump, its possible that there is a pending LAPIC
444 * timer interrupt from previous kernel's context and is delivered in
445 * new kernel the moment interrupts are enabled.
446 *
447 * Interrupts are enabled early and LAPIC is setup much later, hence
448 * its possible that when we get here evt->event_handler is NULL.
449 * Check for event_handler being NULL and discard the interrupt as
450 * spurious.
451 */
452 if (!evt->event_handler) {
453 printk(KERN_WARNING
454 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
455 /* Switch it off */
456 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
457 return;
458 }
459
460 /*
461 * the NMI deadlock-detector uses this.
462 */
463 add_pda(apic_timer_irqs, 1);
464
465 evt->event_handler(evt);
466}
467
468/*
469 * Local APIC timer interrupt. This is the most natural way for doing
470 * local interrupts, but local timer interrupts can be emulated by
471 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
472 *
473 * [ if a single-CPU system runs an SMP kernel then we call the local
474 * interrupt as well. Thus we cannot inline the local irq ... ]
475 */
476void smp_apic_timer_interrupt(struct pt_regs *regs)
477{
478 struct pt_regs *old_regs = set_irq_regs(regs);
479
480 /*
481 * NOTE! We'd better ACK the irq immediately,
482 * because timer handling can be slow.
483 */
484 ack_APIC_irq();
485 /*
486 * update_process_times() expects us to have done irq_enter().
487 * Besides, if we don't timer interrupts ignore the global
488 * interrupt lock, which is the WrongThing (tm) to do.
489 */
490 exit_idle();
491 irq_enter();
492 local_apic_timer_interrupt();
493 irq_exit();
494 set_irq_regs(old_regs);
495}
496
497int setup_profiling_timer(unsigned int multiplier)
498{
499 return -EINVAL;
500}
501
502
503/*
504 * Local APIC start and shutdown
505 */
506
507/**
508 * clear_local_APIC - shutdown the local APIC
509 *
510 * This is called, when a CPU is disabled and before rebooting, so the state of
511 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
512 * leftovers during boot.
513 */
514void clear_local_APIC(void)
515{
516 int maxlvt;
517 u32 v;
518
519 /* APIC hasn't been mapped yet */
520 if (!apic_phys)
521 return;
522
523 maxlvt = lapic_get_maxlvt();
524 /*
525 * Masking an LVT entry can trigger a local APIC error
526 * if the vector is zero. Mask LVTERR first to prevent this.
527 */
528 if (maxlvt >= 3) {
529 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
530 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
531 }
532 /*
533 * Careful: we have to set masks only first to deassert
534 * any level-triggered sources.
535 */
536 v = apic_read(APIC_LVTT);
537 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
538 v = apic_read(APIC_LVT0);
539 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
540 v = apic_read(APIC_LVT1);
541 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
542 if (maxlvt >= 4) {
543 v = apic_read(APIC_LVTPC);
544 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
545 }
546
547 /*
548 * Clean APIC state for other OSs:
549 */
550 apic_write(APIC_LVTT, APIC_LVT_MASKED);
551 apic_write(APIC_LVT0, APIC_LVT_MASKED);
552 apic_write(APIC_LVT1, APIC_LVT_MASKED);
553 if (maxlvt >= 3)
554 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
555 if (maxlvt >= 4)
556 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
557 apic_write(APIC_ESR, 0);
558 apic_read(APIC_ESR);
559}
560
561/**
562 * disable_local_APIC - clear and disable the local APIC
563 */
564void disable_local_APIC(void)
565{
566 unsigned int value;
567
568 clear_local_APIC();
569
570 /*
571 * Disable APIC (implies clearing of registers
572 * for 82489DX!).
573 */
574 value = apic_read(APIC_SPIV);
575 value &= ~APIC_SPIV_APIC_ENABLED;
576 apic_write(APIC_SPIV, value);
577}
578
579void lapic_shutdown(void)
580{
581 unsigned long flags;
582
583 if (!cpu_has_apic)
584 return;
585
586 local_irq_save(flags);
587
588 disable_local_APIC();
589
590 local_irq_restore(flags);
591}
592
593/*
594 * This is to verify that we're looking at a real local APIC.
595 * Check these against your board if the CPUs aren't getting
596 * started for no apparent reason.
597 */
598int __init verify_local_APIC(void)
599{
600 unsigned int reg0, reg1;
601
602 /*
603 * The version register is read-only in a real APIC.
604 */
605 reg0 = apic_read(APIC_LVR);
606 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
607 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
608 reg1 = apic_read(APIC_LVR);
609 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
610
611 /*
612 * The two version reads above should print the same
613 * numbers. If the second one is different, then we
614 * poke at a non-APIC.
615 */
616 if (reg1 != reg0)
617 return 0;
618
619 /*
620 * Check if the version looks reasonably.
621 */
622 reg1 = GET_APIC_VERSION(reg0);
623 if (reg1 == 0x00 || reg1 == 0xff)
624 return 0;
625 reg1 = lapic_get_maxlvt();
626 if (reg1 < 0x02 || reg1 == 0xff)
627 return 0;
628
629 /*
630 * The ID register is read/write in a real APIC.
631 */
632 reg0 = read_apic_id();
633 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
634 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
635 reg1 = read_apic_id();
636 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
637 apic_write(APIC_ID, reg0);
638 if (reg1 != (reg0 ^ APIC_ID_MASK))
639 return 0;
640
641 /*
642 * The next two are just to see if we have sane values.
643 * They're only really relevant if we're in Virtual Wire
644 * compatibility mode, but most boxes are anymore.
645 */
646 reg0 = apic_read(APIC_LVT0);
647 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
648 reg1 = apic_read(APIC_LVT1);
649 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
650
651 return 1;
652}
653
654/**
655 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
656 */
657void __init sync_Arb_IDs(void)
658{
659 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
660 if (modern_apic())
661 return;
662
663 /*
664 * Wait for idle.
665 */
666 apic_wait_icr_idle();
667
668 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
669 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
670 | APIC_DM_INIT);
671}
672
673/*
674 * An initial setup of the virtual wire mode.
675 */
676void __init init_bsp_APIC(void)
677{
678 unsigned int value;
679
680 /*
681 * Don't do the setup now if we have a SMP BIOS as the
682 * through-I/O-APIC virtual wire mode might be active.
683 */
684 if (smp_found_config || !cpu_has_apic)
685 return;
686
687 value = apic_read(APIC_LVR);
688
689 /*
690 * Do not trust the local APIC being empty at bootup.
691 */
692 clear_local_APIC();
693
694 /*
695 * Enable APIC.
696 */
697 value = apic_read(APIC_SPIV);
698 value &= ~APIC_VECTOR_MASK;
699 value |= APIC_SPIV_APIC_ENABLED;
700 value |= APIC_SPIV_FOCUS_DISABLED;
701 value |= SPURIOUS_APIC_VECTOR;
702 apic_write(APIC_SPIV, value);
703
704 /*
705 * Set up the virtual wire mode.
706 */
707 apic_write(APIC_LVT0, APIC_DM_EXTINT);
708 value = APIC_DM_NMI;
709 apic_write(APIC_LVT1, value);
710}
711
712/**
713 * setup_local_APIC - setup the local APIC
714 */
715void __cpuinit setup_local_APIC(void)
716{
717 unsigned int value;
718 int i, j;
719
720 preempt_disable();
721 value = apic_read(APIC_LVR);
722
723 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
724
725 /*
726 * Double-check whether this APIC is really registered.
727 * This is meaningless in clustered apic mode, so we skip it.
728 */
729 if (!apic_id_registered())
730 BUG();
731
732 /*
733 * Intel recommends to set DFR, LDR and TPR before enabling
734 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
735 * document number 292116). So here it goes...
736 */
737 init_apic_ldr();
738
739 /*
740 * Set Task Priority to 'accept all'. We never change this
741 * later on.
742 */
743 value = apic_read(APIC_TASKPRI);
744 value &= ~APIC_TPRI_MASK;
745 apic_write(APIC_TASKPRI, value);
746
747 /*
748 * After a crash, we no longer service the interrupts and a pending
749 * interrupt from previous kernel might still have ISR bit set.
750 *
751 * Most probably by now CPU has serviced that pending interrupt and
752 * it might not have done the ack_APIC_irq() because it thought,
753 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
754 * does not clear the ISR bit and cpu thinks it has already serivced
755 * the interrupt. Hence a vector might get locked. It was noticed
756 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
757 */
758 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
759 value = apic_read(APIC_ISR + i*0x10);
760 for (j = 31; j >= 0; j--) {
761 if (value & (1<<j))
762 ack_APIC_irq();
763 }
764 }
765
766 /*
767 * Now that we are all set up, enable the APIC
768 */
769 value = apic_read(APIC_SPIV);
770 value &= ~APIC_VECTOR_MASK;
771 /*
772 * Enable APIC
773 */
774 value |= APIC_SPIV_APIC_ENABLED;
775
776 /* We always use processor focus */
777
778 /*
779 * Set spurious IRQ vector
780 */
781 value |= SPURIOUS_APIC_VECTOR;
782 apic_write(APIC_SPIV, value);
783
784 /*
785 * Set up LVT0, LVT1:
786 *
787 * set up through-local-APIC on the BP's LINT0. This is not
788 * strictly necessary in pure symmetric-IO mode, but sometimes
789 * we delegate interrupts to the 8259A.
790 */
791 /*
792 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
793 */
794 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
795 if (!smp_processor_id() && !value) {
796 value = APIC_DM_EXTINT;
797 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
798 smp_processor_id());
799 } else {
800 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
801 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
802 smp_processor_id());
803 }
804 apic_write(APIC_LVT0, value);
805
806 /*
807 * only the BP should see the LINT1 NMI signal, obviously.
808 */
809 if (!smp_processor_id())
810 value = APIC_DM_NMI;
811 else
812 value = APIC_DM_NMI | APIC_LVT_MASKED;
813 apic_write(APIC_LVT1, value);
814 preempt_enable();
815}
816
817static void __cpuinit lapic_setup_esr(void)
818{
819 unsigned maxlvt = lapic_get_maxlvt();
820
821 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR);
822 /*
823 * spec says clear errors after enabling vector.
824 */
825 if (maxlvt > 3)
826 apic_write(APIC_ESR, 0);
827}
828
829void __cpuinit end_local_APIC_setup(void)
830{
831 lapic_setup_esr();
832 setup_apic_nmi_watchdog(NULL);
833 apic_pm_activate();
834}
835
836/*
837 * Detect and enable local APICs on non-SMP boards.
838 * Original code written by Keir Fraser.
839 * On AMD64 we trust the BIOS - if it says no APIC it is likely
840 * not correctly set up (usually the APIC timer won't work etc.)
841 */
842static int __init detect_init_APIC(void)
843{
844 if (!cpu_has_apic) {
845 printk(KERN_INFO "No local APIC present\n");
846 return -1;
847 }
848
849 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
850 boot_cpu_physical_apicid = 0;
851 return 0;
852}
853
854void __init early_init_lapic_mapping(void)
855{
856 unsigned long phys_addr;
857
858 /*
859 * If no local APIC can be found then go out
860 * : it means there is no mpatable and MADT
861 */
862 if (!smp_found_config)
863 return;
864
865 phys_addr = mp_lapic_addr;
866
867 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
868 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
869 APIC_BASE, phys_addr);
870
871 /*
872 * Fetch the APIC ID of the BSP in case we have a
873 * default configuration (or the MP table is broken).
874 */
875 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
876}
877
878/**
879 * init_apic_mappings - initialize APIC mappings
880 */
881void __init init_apic_mappings(void)
882{
883 /*
884 * If no local APIC can be found then set up a fake all
885 * zeroes page to simulate the local APIC and another
886 * one for the IO-APIC.
887 */
888 if (!smp_found_config && detect_init_APIC()) {
889 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
890 apic_phys = __pa(apic_phys);
891 } else
892 apic_phys = mp_lapic_addr;
893
894 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
895 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
896 APIC_BASE, apic_phys);
897
898 /*
899 * Fetch the APIC ID of the BSP in case we have a
900 * default configuration (or the MP table is broken).
901 */
902 boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
903}
904
905/*
906 * This initializes the IO-APIC and APIC hardware if this is
907 * a UP kernel.
908 */
909int __init APIC_init_uniprocessor(void)
910{
911 if (disable_apic) {
912 printk(KERN_INFO "Apic disabled\n");
913 return -1;
914 }
915 if (!cpu_has_apic) {
916 disable_apic = 1;
917 printk(KERN_INFO "Apic disabled by BIOS\n");
918 return -1;
919 }
920
921 verify_local_APIC();
922
923 connect_bsp_APIC();
924
925 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
926 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
927
928 setup_local_APIC();
929
930 /*
931 * Now enable IO-APICs, actually call clear_IO_APIC
932 * We need clear_IO_APIC before enabling vector on BP
933 */
934 if (!skip_ioapic_setup && nr_ioapics)
935 enable_IO_APIC();
936
937 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
938 localise_nmi_watchdog();
939 end_local_APIC_setup();
940
941 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
942 setup_IO_APIC();
943 else
944 nr_ioapics = 0;
945 setup_boot_APIC_clock();
946 check_nmi_watchdog();
947 return 0;
948}
949
950/*
951 * Local APIC interrupts
952 */
953
954/*
955 * This interrupt should _never_ happen with our APIC/SMP architecture
956 */
957asmlinkage void smp_spurious_interrupt(void)
958{
959 unsigned int v;
960 exit_idle();
961 irq_enter();
962 /*
963 * Check if this really is a spurious interrupt and ACK it
964 * if it is a vectored one. Just in case...
965 * Spurious interrupts should not be ACKed.
966 */
967 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
968 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
969 ack_APIC_irq();
970
971 add_pda(irq_spurious_count, 1);
972 irq_exit();
973}
974
975/*
976 * This interrupt should never happen with our APIC/SMP architecture
977 */
978asmlinkage void smp_error_interrupt(void)
979{
980 unsigned int v, v1;
981
982 exit_idle();
983 irq_enter();
984 /* First tickle the hardware, only then report what went on. -- REW */
985 v = apic_read(APIC_ESR);
986 apic_write(APIC_ESR, 0);
987 v1 = apic_read(APIC_ESR);
988 ack_APIC_irq();
989 atomic_inc(&irq_err_count);
990
991 /* Here is what the APIC error bits mean:
992 0: Send CS error
993 1: Receive CS error
994 2: Send accept error
995 3: Receive accept error
996 4: Reserved
997 5: Send illegal vector
998 6: Received illegal vector
999 7: Illegal register address
1000 */
1001 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1002 smp_processor_id(), v , v1);
1003 irq_exit();
1004}
1005
1006/**
1007 * * connect_bsp_APIC - attach the APIC to the interrupt system
1008 * */
1009void __init connect_bsp_APIC(void)
1010{
1011 enable_apic_mode();
1012}
1013
1014void disconnect_bsp_APIC(int virt_wire_setup)
1015{
1016 /* Go back to Virtual Wire compatibility mode */
1017 unsigned long value;
1018
1019 /* For the spurious interrupt use vector F, and enable it */
1020 value = apic_read(APIC_SPIV);
1021 value &= ~APIC_VECTOR_MASK;
1022 value |= APIC_SPIV_APIC_ENABLED;
1023 value |= 0xf;
1024 apic_write(APIC_SPIV, value);
1025
1026 if (!virt_wire_setup) {
1027 /*
1028 * For LVT0 make it edge triggered, active high,
1029 * external and enabled
1030 */
1031 value = apic_read(APIC_LVT0);
1032 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1033 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1034 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1035 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1036 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1037 apic_write(APIC_LVT0, value);
1038 } else {
1039 /* Disable LVT0 */
1040 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1041 }
1042
1043 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1044 value = apic_read(APIC_LVT1);
1045 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1046 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1047 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1048 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1049 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1050 apic_write(APIC_LVT1, value);
1051}
1052
1053void __cpuinit generic_processor_info(int apicid, int version)
1054{
1055 int cpu;
1056 cpumask_t tmp_map;
1057
1058 if (num_processors >= NR_CPUS) {
1059 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1060 " Processor ignored.\n", NR_CPUS);
1061 return;
1062 }
1063
1064 num_processors++;
1065 cpus_complement(tmp_map, cpu_present_map);
1066 cpu = first_cpu(tmp_map);
1067
1068 physid_set(apicid, phys_cpu_present_map);
1069 if (apicid == boot_cpu_physical_apicid) {
1070 /*
1071 * x86_bios_cpu_apicid is required to have processors listed
1072 * in same order as logical cpu numbers. Hence the first
1073 * entry is BSP, and so on.
1074 */
1075 cpu = 0;
1076 }
1077 if (apicid > max_physical_apicid)
1078 max_physical_apicid = apicid;
1079
1080 /* are we being called early in kernel startup? */
1081 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1082 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1083 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1084
1085 cpu_to_apicid[cpu] = apicid;
1086 bios_cpu_apicid[cpu] = apicid;
1087 } else {
1088 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1089 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1090 }
1091
1092 cpu_set(cpu, cpu_possible_map);
1093 cpu_set(cpu, cpu_present_map);
1094}
1095
1096/*
1097 * Power management
1098 */
1099#ifdef CONFIG_PM
1100
1101static struct {
1102 /* 'active' is true if the local APIC was enabled by us and
1103 not the BIOS; this signifies that we are also responsible
1104 for disabling it before entering apm/acpi suspend */
1105 int active;
1106 /* r/w apic fields */
1107 unsigned int apic_id;
1108 unsigned int apic_taskpri;
1109 unsigned int apic_ldr;
1110 unsigned int apic_dfr;
1111 unsigned int apic_spiv;
1112 unsigned int apic_lvtt;
1113 unsigned int apic_lvtpc;
1114 unsigned int apic_lvt0;
1115 unsigned int apic_lvt1;
1116 unsigned int apic_lvterr;
1117 unsigned int apic_tmict;
1118 unsigned int apic_tdcr;
1119 unsigned int apic_thmr;
1120} apic_pm_state;
1121
1122static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1123{
1124 unsigned long flags;
1125 int maxlvt;
1126
1127 if (!apic_pm_state.active)
1128 return 0;
1129
1130 maxlvt = lapic_get_maxlvt();
1131
1132 apic_pm_state.apic_id = read_apic_id();
1133 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1134 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1135 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1136 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1137 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1138 if (maxlvt >= 4)
1139 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1140 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1141 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1142 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1143 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1144 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1145#ifdef CONFIG_X86_MCE_INTEL
1146 if (maxlvt >= 5)
1147 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1148#endif
1149 local_irq_save(flags);
1150 disable_local_APIC();
1151 local_irq_restore(flags);
1152 return 0;
1153}
1154
1155static int lapic_resume(struct sys_device *dev)
1156{
1157 unsigned int l, h;
1158 unsigned long flags;
1159 int maxlvt;
1160
1161 if (!apic_pm_state.active)
1162 return 0;
1163
1164 maxlvt = lapic_get_maxlvt();
1165
1166 local_irq_save(flags);
1167 rdmsr(MSR_IA32_APICBASE, l, h);
1168 l &= ~MSR_IA32_APICBASE_BASE;
1169 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1170 wrmsr(MSR_IA32_APICBASE, l, h);
1171 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1172 apic_write(APIC_ID, apic_pm_state.apic_id);
1173 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1174 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1175 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1176 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1177 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1178 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1179#ifdef CONFIG_X86_MCE_INTEL
1180 if (maxlvt >= 5)
1181 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1182#endif
1183 if (maxlvt >= 4)
1184 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1185 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1186 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1187 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1188 apic_write(APIC_ESR, 0);
1189 apic_read(APIC_ESR);
1190 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1191 apic_write(APIC_ESR, 0);
1192 apic_read(APIC_ESR);
1193 local_irq_restore(flags);
1194 return 0;
1195}
1196
1197static struct sysdev_class lapic_sysclass = {
1198 .name = "lapic",
1199 .resume = lapic_resume,
1200 .suspend = lapic_suspend,
1201};
1202
1203static struct sys_device device_lapic = {
1204 .id = 0,
1205 .cls = &lapic_sysclass,
1206};
1207
1208static void __cpuinit apic_pm_activate(void)
1209{
1210 apic_pm_state.active = 1;
1211}
1212
1213static int __init init_lapic_sysfs(void)
1214{
1215 int error;
1216
1217 if (!cpu_has_apic)
1218 return 0;
1219 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1220
1221 error = sysdev_class_register(&lapic_sysclass);
1222 if (!error)
1223 error = sysdev_register(&device_lapic);
1224 return error;
1225}
1226device_initcall(init_lapic_sysfs);
1227
1228#else /* CONFIG_PM */
1229
1230static void apic_pm_activate(void) { }
1231
1232#endif /* CONFIG_PM */
1233
1234/*
1235 * apic_is_clustered_box() -- Check if we can expect good TSC
1236 *
1237 * Thus far, the major user of this is IBM's Summit2 series:
1238 *
1239 * Clustered boxes may have unsynced TSC problems if they are
1240 * multi-chassis. Use available data to take a good guess.
1241 * If in doubt, go HPET.
1242 */
1243__cpuinit int apic_is_clustered_box(void)
1244{
1245 int i, clusters, zeros;
1246 unsigned id;
1247 u16 *bios_cpu_apicid;
1248 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1249
1250 /*
1251 * there is not this kind of box with AMD CPU yet.
1252 * Some AMD box with quadcore cpu and 8 sockets apicid
1253 * will be [4, 0x23] or [8, 0x27] could be thought to
1254 * vsmp box still need checking...
1255 */
1256 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1257 return 0;
1258
1259 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1260 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1261
1262 for (i = 0; i < NR_CPUS; i++) {
1263 /* are we being called early in kernel startup? */
1264 if (bios_cpu_apicid) {
1265 id = bios_cpu_apicid[i];
1266 }
1267 else if (i < nr_cpu_ids) {
1268 if (cpu_present(i))
1269 id = per_cpu(x86_bios_cpu_apicid, i);
1270 else
1271 continue;
1272 }
1273 else
1274 break;
1275
1276 if (id != BAD_APICID)
1277 __set_bit(APIC_CLUSTERID(id), clustermap);
1278 }
1279
1280 /* Problem: Partially populated chassis may not have CPUs in some of
1281 * the APIC clusters they have been allocated. Only present CPUs have
1282 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1283 * Since clusters are allocated sequentially, count zeros only if
1284 * they are bounded by ones.
1285 */
1286 clusters = 0;
1287 zeros = 0;
1288 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1289 if (test_bit(i, clustermap)) {
1290 clusters += 1 + zeros;
1291 zeros = 0;
1292 } else
1293 ++zeros;
1294 }
1295
1296 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1297 * not guaranteed to be synced between boards
1298 */
1299 if (is_vsmp_box() && clusters > 1)
1300 return 1;
1301
1302 /*
1303 * If clusters > 2, then should be multi-chassis.
1304 * May have to revisit this when multi-core + hyperthreaded CPUs come
1305 * out, but AFAIK this will work even for them.
1306 */
1307 return (clusters > 2);
1308}
1309
1310/*
1311 * APIC command line parameters
1312 */
1313static int __init apic_set_verbosity(char *str)
1314{
1315 if (str == NULL) {
1316 skip_ioapic_setup = 0;
1317 ioapic_force = 1;
1318 return 0;
1319 }
1320 if (strcmp("debug", str) == 0)
1321 apic_verbosity = APIC_DEBUG;
1322 else if (strcmp("verbose", str) == 0)
1323 apic_verbosity = APIC_VERBOSE;
1324 else {
1325 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1326 " use apic=verbose or apic=debug\n", str);
1327 return -EINVAL;
1328 }
1329
1330 return 0;
1331}
1332early_param("apic", apic_set_verbosity);
1333
1334static __init int setup_disableapic(char *str)
1335{
1336 disable_apic = 1;
1337 setup_clear_cpu_cap(X86_FEATURE_APIC);
1338 return 0;
1339}
1340early_param("disableapic", setup_disableapic);
1341
1342/* same as disableapic, for compatibility */
1343static __init int setup_nolapic(char *str)
1344{
1345 return setup_disableapic(str);
1346}
1347early_param("nolapic", setup_nolapic);
1348
1349static int __init parse_lapic_timer_c2_ok(char *arg)
1350{
1351 local_apic_timer_c2_ok = 1;
1352 return 0;
1353}
1354early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1355
1356static __init int setup_noapictimer(char *str)
1357{
1358 if (str[0] != ' ' && str[0] != 0)
1359 return 0;
1360 disable_apic_timer = 1;
1361 return 1;
1362}
1363__setup("noapictimer", setup_noapictimer);
1364
1365static __init int setup_apicpmtimer(char *s)
1366{
1367 apic_calibrate_pmtmr = 1;
1368 notsc_setup(NULL);
1369 return 0;
1370}
1371__setup("apicpmtimer", setup_apicpmtimer);
1372
1373static int __init lapic_insert_resource(void)
1374{
1375 if (!apic_phys)
1376 return -1;
1377
1378 /* Put local APIC into the resource map. */
1379 lapic_resource.start = apic_phys;
1380 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1381 insert_resource(&iomem_resource, &lapic_resource);
1382
1383 return 0;
1384}
1385
1386/*
1387 * need call insert after e820_reserve_resources()
1388 * that is using request_resource
1389 */
1390late_initcall(lapic_insert_resource);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 02:23:04 -0500