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Diffstat (limited to 'arch/x86/kernel/apic/apic.c')
-rw-r--r--arch/x86/kernel/apic/apic.c12
1 files changed, 2 insertions, 10 deletions
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index d1bf032ba26..4732768c534 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -35,7 +35,6 @@
35#include <linux/mm.h> 35#include <linux/mm.h>
36 36
37#include <asm/perf_counter.h> 37#include <asm/perf_counter.h>
38#include <asm/arch_hooks.h>
39#include <asm/pgalloc.h> 38#include <asm/pgalloc.h>
40#include <asm/atomic.h> 39#include <asm/atomic.h>
41#include <asm/mpspec.h> 40#include <asm/mpspec.h>
@@ -840,7 +839,7 @@ void clear_local_APIC(void)
840 } 839 }
841 840
842 /* lets not touch this if we didn't frob it */ 841 /* lets not touch this if we didn't frob it */
843#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) 842#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
844 if (maxlvt >= 5) { 843 if (maxlvt >= 5) {
845 v = apic_read(APIC_LVTTHMR); 844 v = apic_read(APIC_LVTTHMR);
846 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 845 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
@@ -1269,14 +1268,7 @@ void __cpuinit end_local_APIC_setup(void)
1269#ifdef CONFIG_X86_X2APIC 1268#ifdef CONFIG_X86_X2APIC
1270void check_x2apic(void) 1269void check_x2apic(void)
1271{ 1270{
1272 int msr, msr2; 1271 if (x2apic_enabled()) {
1273
1274 if (!cpu_has_x2apic)
1275 return;
1276
1277 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1278
1279 if (msr & X2APIC_ENABLE) {
1280 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1272 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1281 x2apic_preenabled = x2apic = 1; 1273 x2apic_preenabled = x2apic = 1;
1282 } 1274 }