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Diffstat (limited to 'arch/sh/kernel/cpu/sh4/probe.c')
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c178
1 files changed, 87 insertions, 91 deletions
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 98d28fb1ce1..21375d777e9 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * CPU Subtype Probing for SH-4. 4 * CPU Subtype Probing for SH-4.
5 * 5 *
6 * Copyright (C) 2001 - 2006 Paul Mundt 6 * Copyright (C) 2001 - 2007 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow 7 * Copyright (C) 2003 Richard Curnow
8 * 8 *
9 * This file is subject to the terms and conditions of the GNU General Public 9 * This file is subject to the terms and conditions of the GNU General Public
@@ -12,7 +12,6 @@
12 */ 12 */
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/smp.h>
16#include <asm/processor.h> 15#include <asm/processor.h>
17#include <asm/cache.h> 16#include <asm/cache.h>
18 17
@@ -36,37 +35,34 @@ int __init detect_cpu_and_cache_system(void)
36 /* 35 /*
37 * Setup some sane SH-4 defaults for the icache 36 * Setup some sane SH-4 defaults for the icache
38 */ 37 */
39 current_cpu_data.icache.way_incr = (1 << 13); 38 boot_cpu_data.icache.way_incr = (1 << 13);
40 current_cpu_data.icache.entry_shift = 5; 39 boot_cpu_data.icache.entry_shift = 5;
41 current_cpu_data.icache.sets = 256; 40 boot_cpu_data.icache.sets = 256;
42 current_cpu_data.icache.ways = 1; 41 boot_cpu_data.icache.ways = 1;
43 current_cpu_data.icache.linesz = L1_CACHE_BYTES; 42 boot_cpu_data.icache.linesz = L1_CACHE_BYTES;
44 43
45 /* 44 /*
46 * And again for the dcache .. 45 * And again for the dcache ..
47 */ 46 */
48 current_cpu_data.dcache.way_incr = (1 << 14); 47 boot_cpu_data.dcache.way_incr = (1 << 14);
49 current_cpu_data.dcache.entry_shift = 5; 48 boot_cpu_data.dcache.entry_shift = 5;
50 current_cpu_data.dcache.sets = 512; 49 boot_cpu_data.dcache.sets = 512;
51 current_cpu_data.dcache.ways = 1; 50 boot_cpu_data.dcache.ways = 1;
52 current_cpu_data.dcache.linesz = L1_CACHE_BYTES; 51 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
53 52
54 /* 53 /*
55 * Setup some generic flags we can probe 54 * Setup some generic flags we can probe on SH-4A parts
56 * (L2 and DSP detection only work on SH-4A)
57 */ 55 */
58 if (((pvr >> 16) & 0xff) == 0x10) { 56 if (((pvr >> 16) & 0xff) == 0x10) {
59 if ((cvr & 0x02000000) == 0)
60 current_cpu_data.flags |= CPU_HAS_L2_CACHE;
61 if ((cvr & 0x10000000) == 0) 57 if ((cvr & 0x10000000) == 0)
62 current_cpu_data.flags |= CPU_HAS_DSP; 58 boot_cpu_data.flags |= CPU_HAS_DSP;
63 59
64 current_cpu_data.flags |= CPU_HAS_LLSC; 60 boot_cpu_data.flags |= CPU_HAS_LLSC;
65 } 61 }
66 62
67 /* FPU detection works for everyone */ 63 /* FPU detection works for everyone */
68 if ((cvr & 0x20000000) == 1) 64 if ((cvr & 0x20000000) == 1)
69 current_cpu_data.flags |= CPU_HAS_FPU; 65 boot_cpu_data.flags |= CPU_HAS_FPU;
70 66
71 /* Mask off the upper chip ID */ 67 /* Mask off the upper chip ID */
72 pvr &= 0xffff; 68 pvr &= 0xffff;
@@ -77,140 +73,140 @@ int __init detect_cpu_and_cache_system(void)
77 */ 73 */
78 switch (pvr) { 74 switch (pvr) {
79 case 0x205: 75 case 0x205:
80 current_cpu_data.type = CPU_SH7750; 76 boot_cpu_data.type = CPU_SH7750;
81 current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | 77 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
82 CPU_HAS_PERF_COUNTER; 78 CPU_HAS_PERF_COUNTER;
83 break; 79 break;
84 case 0x206: 80 case 0x206:
85 current_cpu_data.type = CPU_SH7750S; 81 boot_cpu_data.type = CPU_SH7750S;
86 current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | 82 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
87 CPU_HAS_PERF_COUNTER; 83 CPU_HAS_PERF_COUNTER;
88 break; 84 break;
89 case 0x1100: 85 case 0x1100:
90 current_cpu_data.type = CPU_SH7751; 86 boot_cpu_data.type = CPU_SH7751;
91 current_cpu_data.flags |= CPU_HAS_FPU; 87 boot_cpu_data.flags |= CPU_HAS_FPU;
92 break; 88 break;
93 case 0x2001: 89 case 0x2001:
94 case 0x2004: 90 case 0x2004:
95 current_cpu_data.type = CPU_SH7770; 91 boot_cpu_data.type = CPU_SH7770;
96 current_cpu_data.icache.ways = 4; 92 boot_cpu_data.icache.ways = 4;
97 current_cpu_data.dcache.ways = 4; 93 boot_cpu_data.dcache.ways = 4;
98 94
99 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC; 95 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
100 break; 96 break;
101 case 0x2006: 97 case 0x2006:
102 case 0x200A: 98 case 0x200A:
103 if (prr == 0x61) 99 if (prr == 0x61)
104 current_cpu_data.type = CPU_SH7781; 100 boot_cpu_data.type = CPU_SH7781;
105 else 101 else
106 current_cpu_data.type = CPU_SH7780; 102 boot_cpu_data.type = CPU_SH7780;
107 103
108 current_cpu_data.icache.ways = 4; 104 boot_cpu_data.icache.ways = 4;
109 current_cpu_data.dcache.ways = 4; 105 boot_cpu_data.dcache.ways = 4;
110 106
111 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | 107 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
112 CPU_HAS_LLSC; 108 CPU_HAS_LLSC;
113 break; 109 break;
114 case 0x3000: 110 case 0x3000:
115 case 0x3003: 111 case 0x3003:
116 case 0x3009: 112 case 0x3009:
117 current_cpu_data.type = CPU_SH7343; 113 boot_cpu_data.type = CPU_SH7343;
118 current_cpu_data.icache.ways = 4; 114 boot_cpu_data.icache.ways = 4;
119 current_cpu_data.dcache.ways = 4; 115 boot_cpu_data.dcache.ways = 4;
120 current_cpu_data.flags |= CPU_HAS_LLSC; 116 boot_cpu_data.flags |= CPU_HAS_LLSC;
121 break; 117 break;
122 case 0x3004: 118 case 0x3004:
123 case 0x3007: 119 case 0x3007:
124 current_cpu_data.type = CPU_SH7785; 120 boot_cpu_data.type = CPU_SH7785;
125 current_cpu_data.icache.ways = 4; 121 boot_cpu_data.icache.ways = 4;
126 current_cpu_data.dcache.ways = 4; 122 boot_cpu_data.dcache.ways = 4;
127 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | 123 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
128 CPU_HAS_LLSC; 124 CPU_HAS_LLSC;
129 break; 125 break;
130 case 0x3008: 126 case 0x3008:
131 if (prr == 0xa0) { 127 if (prr == 0xa0) {
132 current_cpu_data.type = CPU_SH7722; 128 boot_cpu_data.type = CPU_SH7722;
133 current_cpu_data.icache.ways = 4; 129 boot_cpu_data.icache.ways = 4;
134 current_cpu_data.dcache.ways = 4; 130 boot_cpu_data.dcache.ways = 4;
135 current_cpu_data.flags |= CPU_HAS_LLSC; 131 boot_cpu_data.flags |= CPU_HAS_LLSC;
136 } 132 }
137 break; 133 break;
138 case 0x4000: /* 1st cut */ 134 case 0x4000: /* 1st cut */
139 case 0x4001: /* 2nd cut */ 135 case 0x4001: /* 2nd cut */
140 current_cpu_data.type = CPU_SHX3; 136 boot_cpu_data.type = CPU_SHX3;
141 current_cpu_data.icache.ways = 4; 137 boot_cpu_data.icache.ways = 4;
142 current_cpu_data.dcache.ways = 4; 138 boot_cpu_data.dcache.ways = 4;
143 current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | 139 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
144 CPU_HAS_LLSC; 140 CPU_HAS_LLSC;
145 break; 141 break;
146 case 0x8000: 142 case 0x8000:
147 current_cpu_data.type = CPU_ST40RA; 143 boot_cpu_data.type = CPU_ST40RA;
148 current_cpu_data.flags |= CPU_HAS_FPU; 144 boot_cpu_data.flags |= CPU_HAS_FPU;
149 break; 145 break;
150 case 0x8100: 146 case 0x8100:
151 current_cpu_data.type = CPU_ST40GX1; 147 boot_cpu_data.type = CPU_ST40GX1;
152 current_cpu_data.flags |= CPU_HAS_FPU; 148 boot_cpu_data.flags |= CPU_HAS_FPU;
153 break; 149 break;
154 case 0x700: 150 case 0x700:
155 current_cpu_data.type = CPU_SH4_501; 151 boot_cpu_data.type = CPU_SH4_501;
156 current_cpu_data.icache.ways = 2; 152 boot_cpu_data.icache.ways = 2;
157 current_cpu_data.dcache.ways = 2; 153 boot_cpu_data.dcache.ways = 2;
158 break; 154 break;
159 case 0x600: 155 case 0x600:
160 current_cpu_data.type = CPU_SH4_202; 156 boot_cpu_data.type = CPU_SH4_202;
161 current_cpu_data.icache.ways = 2; 157 boot_cpu_data.icache.ways = 2;
162 current_cpu_data.dcache.ways = 2; 158 boot_cpu_data.dcache.ways = 2;
163 current_cpu_data.flags |= CPU_HAS_FPU; 159 boot_cpu_data.flags |= CPU_HAS_FPU;
164 break; 160 break;
165 case 0x500 ... 0x501: 161 case 0x500 ... 0x501:
166 switch (prr) { 162 switch (prr) {
167 case 0x10: 163 case 0x10:
168 current_cpu_data.type = CPU_SH7750R; 164 boot_cpu_data.type = CPU_SH7750R;
169 break; 165 break;
170 case 0x11: 166 case 0x11:
171 current_cpu_data.type = CPU_SH7751R; 167 boot_cpu_data.type = CPU_SH7751R;
172 break; 168 break;
173 case 0x50 ... 0x5f: 169 case 0x50 ... 0x5f:
174 current_cpu_data.type = CPU_SH7760; 170 boot_cpu_data.type = CPU_SH7760;
175 break; 171 break;
176 } 172 }
177 173
178 current_cpu_data.icache.ways = 2; 174 boot_cpu_data.icache.ways = 2;
179 current_cpu_data.dcache.ways = 2; 175 boot_cpu_data.dcache.ways = 2;
180 176
181 current_cpu_data.flags |= CPU_HAS_FPU; 177 boot_cpu_data.flags |= CPU_HAS_FPU;
182 178
183 break; 179 break;
184 default: 180 default:
185 current_cpu_data.type = CPU_SH_NONE; 181 boot_cpu_data.type = CPU_SH_NONE;
186 break; 182 break;
187 } 183 }
188 184
189#ifdef CONFIG_SH_DIRECT_MAPPED 185#ifdef CONFIG_SH_DIRECT_MAPPED
190 current_cpu_data.icache.ways = 1; 186 boot_cpu_data.icache.ways = 1;
191 current_cpu_data.dcache.ways = 1; 187 boot_cpu_data.dcache.ways = 1;
192#endif 188#endif
193 189
194#ifdef CONFIG_CPU_HAS_PTEA 190#ifdef CONFIG_CPU_HAS_PTEA
195 current_cpu_data.flags |= CPU_HAS_PTEA; 191 boot_cpu_data.flags |= CPU_HAS_PTEA;
196#endif 192#endif
197 193
198 /* 194 /*
199 * On anything that's not a direct-mapped cache, look to the CVR 195 * On anything that's not a direct-mapped cache, look to the CVR
200 * for I/D-cache specifics. 196 * for I/D-cache specifics.
201 */ 197 */
202 if (current_cpu_data.icache.ways > 1) { 198 if (boot_cpu_data.icache.ways > 1) {
203 size = sizes[(cvr >> 20) & 0xf]; 199 size = sizes[(cvr >> 20) & 0xf];
204 current_cpu_data.icache.way_incr = (size >> 1); 200 boot_cpu_data.icache.way_incr = (size >> 1);
205 current_cpu_data.icache.sets = (size >> 6); 201 boot_cpu_data.icache.sets = (size >> 6);
206 202
207 } 203 }
208 204
209 /* And the rest of the D-cache */ 205 /* And the rest of the D-cache */
210 if (current_cpu_data.dcache.ways > 1) { 206 if (boot_cpu_data.dcache.ways > 1) {
211 size = sizes[(cvr >> 16) & 0xf]; 207 size = sizes[(cvr >> 16) & 0xf];
212 current_cpu_data.dcache.way_incr = (size >> 1); 208 boot_cpu_data.dcache.way_incr = (size >> 1);
213 current_cpu_data.dcache.sets = (size >> 6); 209 boot_cpu_data.dcache.sets = (size >> 6);
214 } 210 }
215 211
216 /* 212 /*
@@ -218,7 +214,7 @@ int __init detect_cpu_and_cache_system(void)
218 * 214 *
219 * SH-4A's have an optional PIPT L2. 215 * SH-4A's have an optional PIPT L2.
220 */ 216 */
221 if (current_cpu_data.flags & CPU_HAS_L2_CACHE) { 217 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
222 /* 218 /*
223 * Size calculation is much more sensible 219 * Size calculation is much more sensible
224 * than it is for the L1. 220 * than it is for the L1.
@@ -229,22 +225,22 @@ int __init detect_cpu_and_cache_system(void)
229 225
230 BUG_ON(!size); 226 BUG_ON(!size);
231 227
232 current_cpu_data.scache.way_incr = (1 << 16); 228 boot_cpu_data.scache.way_incr = (1 << 16);
233 current_cpu_data.scache.entry_shift = 5; 229 boot_cpu_data.scache.entry_shift = 5;
234 current_cpu_data.scache.ways = 4; 230 boot_cpu_data.scache.ways = 4;
235 current_cpu_data.scache.linesz = L1_CACHE_BYTES; 231 boot_cpu_data.scache.linesz = L1_CACHE_BYTES;
236 232
237 current_cpu_data.scache.entry_mask = 233 boot_cpu_data.scache.entry_mask =
238 (current_cpu_data.scache.way_incr - 234 (boot_cpu_data.scache.way_incr -
239 current_cpu_data.scache.linesz); 235 boot_cpu_data.scache.linesz);
240 236
241 current_cpu_data.scache.sets = size / 237 boot_cpu_data.scache.sets = size /
242 (current_cpu_data.scache.linesz * 238 (boot_cpu_data.scache.linesz *
243 current_cpu_data.scache.ways); 239 boot_cpu_data.scache.ways);
244 240
245 current_cpu_data.scache.way_size = 241 boot_cpu_data.scache.way_size =
246 (current_cpu_data.scache.sets * 242 (boot_cpu_data.scache.sets *
247 current_cpu_data.scache.linesz); 243 boot_cpu_data.scache.linesz);
248 } 244 }
249 245
250 return 0; 246 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-09 16:39:00 -0400