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-rw-r--r--arch/powerpc/platforms/powermac/pmac_pci.c1341
1 files changed, 1341 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/powermac/pmac_pci.c b/arch/powerpc/platforms/powermac/pmac_pci.c
new file mode 100644
index 00000000000..40bcd3e55af
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+++ b/arch/powerpc/platforms/powermac/pmac_pci.c
@@ -0,0 +1,1341 @@
1/*
2 * Support for PCI bridges found on Power Macintoshes.
3 * At present the "bandit" and "chaos" bridges are supported.
4 * Fortunately you access configuration space in the same
5 * way with either bridge.
6 *
7 * Copyright (C) 2003 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
8 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/pci.h>
18#include <linux/delay.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/bootmem.h>
22
23#include <asm/sections.h>
24#include <asm/io.h>
25#include <asm/prom.h>
26#include <asm/pci-bridge.h>
27#include <asm/machdep.h>
28#include <asm/pmac_feature.h>
29
30#undef DEBUG
31
32#ifdef DEBUG
33#define DBG(x...) printk(x)
34#else
35#define DBG(x...)
36#endif
37
38static int add_bridge(struct device_node *dev);
39extern void pmac_check_ht_link(void);
40
41/* XXX Could be per-controller, but I don't think we risk anything by
42 * assuming we won't have both UniNorth and Bandit */
43static int has_uninorth;
44#ifdef CONFIG_POWER4
45static struct pci_controller *u3_agp;
46#endif /* CONFIG_POWER4 */
47
48extern u8 pci_cache_line_size;
49extern int pcibios_assign_bus_offset;
50
51struct device_node *k2_skiplist[2];
52
53/*
54 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
55 */
56#define BANDIT_DEVID_2 8
57#define BANDIT_REVID 3
58
59#define BANDIT_DEVNUM 11
60#define BANDIT_MAGIC 0x50
61#define BANDIT_COHERENT 0x40
62
63static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
64{
65 for (; node != 0;node = node->sibling) {
66 int * bus_range;
67 unsigned int *class_code;
68 int len;
69
70 /* For PCI<->PCI bridges or CardBus bridges, we go down */
71 class_code = (unsigned int *) get_property(node, "class-code", NULL);
72 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
73 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
74 continue;
75 bus_range = (int *) get_property(node, "bus-range", &len);
76 if (bus_range != NULL && len > 2 * sizeof(int)) {
77 if (bus_range[1] > higher)
78 higher = bus_range[1];
79 }
80 higher = fixup_one_level_bus_range(node->child, higher);
81 }
82 return higher;
83}
84
85/* This routine fixes the "bus-range" property of all bridges in the
86 * system since they tend to have their "last" member wrong on macs
87 *
88 * Note that the bus numbers manipulated here are OF bus numbers, they
89 * are not Linux bus numbers.
90 */
91static void __init fixup_bus_range(struct device_node *bridge)
92{
93 int * bus_range;
94 int len;
95
96 /* Lookup the "bus-range" property for the hose */
97 bus_range = (int *) get_property(bridge, "bus-range", &len);
98 if (bus_range == NULL || len < 2 * sizeof(int)) {
99 printk(KERN_WARNING "Can't get bus-range for %s\n",
100 bridge->full_name);
101 return;
102 }
103 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
104}
105
106/*
107 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
108 *
109 * The "Bandit" version is present in all early PCI PowerMacs,
110 * and up to the first ones using Grackle. Some machines may
111 * have 2 bandit controllers (2 PCI busses).
112 *
113 * "Chaos" is used in some "Bandit"-type machines as a bridge
114 * for the separate display bus. It is accessed the same
115 * way as bandit, but cannot be probed for devices. It therefore
116 * has its own config access functions.
117 *
118 * The "UniNorth" version is present in all Core99 machines
119 * (iBook, G4, new IMacs, and all the recent Apple machines).
120 * It contains 3 controllers in one ASIC.
121 *
122 * The U3 is the bridge used on G5 machines. It contains an
123 * AGP bus which is dealt with the old UniNorth access routines
124 * and a HyperTransport bus which uses its own set of access
125 * functions.
126 */
127
128#define MACRISC_CFA0(devfn, off) \
129 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
130 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
131 | (((unsigned long)(off)) & 0xFCUL))
132
133#define MACRISC_CFA1(bus, devfn, off) \
134 ((((unsigned long)(bus)) << 16) \
135 |(((unsigned long)(devfn)) << 8) \
136 |(((unsigned long)(off)) & 0xFCUL) \
137 |1UL)
138
139static unsigned long macrisc_cfg_access(struct pci_controller* hose,
140 u8 bus, u8 dev_fn, u8 offset)
141{
142 unsigned int caddr;
143
144 if (bus == hose->first_busno) {
145 if (dev_fn < (11 << 3))
146 return 0;
147 caddr = MACRISC_CFA0(dev_fn, offset);
148 } else
149 caddr = MACRISC_CFA1(bus, dev_fn, offset);
150
151 /* Uninorth will return garbage if we don't read back the value ! */
152 do {
153 out_le32(hose->cfg_addr, caddr);
154 } while (in_le32(hose->cfg_addr) != caddr);
155
156 offset &= has_uninorth ? 0x07 : 0x03;
157 return ((unsigned long)hose->cfg_data) + offset;
158}
159
160static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
161 int offset, int len, u32 *val)
162{
163 struct pci_controller *hose = bus->sysdata;
164 unsigned long addr;
165
166 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
167 if (!addr)
168 return PCIBIOS_DEVICE_NOT_FOUND;
169 /*
170 * Note: the caller has already checked that offset is
171 * suitably aligned and that len is 1, 2 or 4.
172 */
173 switch (len) {
174 case 1:
175 *val = in_8((u8 *)addr);
176 break;
177 case 2:
178 *val = in_le16((u16 *)addr);
179 break;
180 default:
181 *val = in_le32((u32 *)addr);
182 break;
183 }
184 return PCIBIOS_SUCCESSFUL;
185}
186
187static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
188 int offset, int len, u32 val)
189{
190 struct pci_controller *hose = bus->sysdata;
191 unsigned long addr;
192
193 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
194 if (!addr)
195 return PCIBIOS_DEVICE_NOT_FOUND;
196 /*
197 * Note: the caller has already checked that offset is
198 * suitably aligned and that len is 1, 2 or 4.
199 */
200 switch (len) {
201 case 1:
202 out_8((u8 *)addr, val);
203 (void) in_8((u8 *)addr);
204 break;
205 case 2:
206 out_le16((u16 *)addr, val);
207 (void) in_le16((u16 *)addr);
208 break;
209 default:
210 out_le32((u32 *)addr, val);
211 (void) in_le32((u32 *)addr);
212 break;
213 }
214 return PCIBIOS_SUCCESSFUL;
215}
216
217static struct pci_ops macrisc_pci_ops =
218{
219 macrisc_read_config,
220 macrisc_write_config
221};
222
223/*
224 * Verifiy that a specific (bus, dev_fn) exists on chaos
225 */
226static int
227chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
228{
229 struct device_node *np;
230 u32 *vendor, *device;
231
232 np = pci_busdev_to_OF_node(bus, devfn);
233 if (np == NULL)
234 return PCIBIOS_DEVICE_NOT_FOUND;
235
236 vendor = (u32 *)get_property(np, "vendor-id", NULL);
237 device = (u32 *)get_property(np, "device-id", NULL);
238 if (vendor == NULL || device == NULL)
239 return PCIBIOS_DEVICE_NOT_FOUND;
240
241 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
242 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
243 return PCIBIOS_BAD_REGISTER_NUMBER;
244
245 return PCIBIOS_SUCCESSFUL;
246}
247
248static int
249chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
250 int len, u32 *val)
251{
252 int result = chaos_validate_dev(bus, devfn, offset);
253 if (result == PCIBIOS_BAD_REGISTER_NUMBER)
254 *val = ~0U;
255 if (result != PCIBIOS_SUCCESSFUL)
256 return result;
257 return macrisc_read_config(bus, devfn, offset, len, val);
258}
259
260static int
261chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
262 int len, u32 val)
263{
264 int result = chaos_validate_dev(bus, devfn, offset);
265 if (result != PCIBIOS_SUCCESSFUL)
266 return result;
267 return macrisc_write_config(bus, devfn, offset, len, val);
268}
269
270static struct pci_ops chaos_pci_ops =
271{
272 chaos_read_config,
273 chaos_write_config
274};
275
276#ifdef CONFIG_POWER4
277
278/*
279 * These versions of U3 HyperTransport config space access ops do not
280 * implement self-view of the HT host yet
281 */
282
283/*
284 * This function deals with some "special cases" devices.
285 *
286 * 0 -> No special case
287 * 1 -> Skip the device but act as if the access was successfull
288 * (return 0xff's on reads, eventually, cache config space
289 * accesses in a later version)
290 * -1 -> Hide the device (unsuccessful acess)
291 */
292static int u3_ht_skip_device(struct pci_controller *hose,
293 struct pci_bus *bus, unsigned int devfn)
294{
295 struct device_node *busdn, *dn;
296 int i;
297
298 /* We only allow config cycles to devices that are in OF device-tree
299 * as we are apparently having some weird things going on with some
300 * revs of K2 on recent G5s
301 */
302 if (bus->self)
303 busdn = pci_device_to_OF_node(bus->self);
304 else
305 busdn = hose->arch_data;
306 for (dn = busdn->child; dn; dn = dn->sibling)
307 if (dn->data && PCI_DN(dn)->devfn == devfn)
308 break;
309 if (dn == NULL)
310 return -1;
311
312 /*
313 * When a device in K2 is powered down, we die on config
314 * cycle accesses. Fix that here.
315 */
316 for (i=0; i<2; i++)
317 if (k2_skiplist[i] == dn)
318 return 1;
319
320 return 0;
321}
322
323#define U3_HT_CFA0(devfn, off) \
324 ((((unsigned long)devfn) << 8) | offset)
325#define U3_HT_CFA1(bus, devfn, off) \
326 (U3_HT_CFA0(devfn, off) \
327 + (((unsigned long)bus) << 16) \
328 + 0x01000000UL)
329
330static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
331 u8 bus, u8 devfn, u8 offset)
332{
333 if (bus == hose->first_busno) {
334 /* For now, we don't self probe U3 HT bridge */
335 if (PCI_SLOT(devfn) == 0)
336 return 0;
337 return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset);
338 } else
339 return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset);
340}
341
342static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
343 int offset, int len, u32 *val)
344{
345 struct pci_controller *hose = bus->sysdata;
346 unsigned long addr;
347
348 struct device_node *np = pci_busdev_to_OF_node(bus, devfn);
349 if (np == NULL)
350 return PCIBIOS_DEVICE_NOT_FOUND;
351
352 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
353 if (!addr)
354 return PCIBIOS_DEVICE_NOT_FOUND;
355
356 switch (u3_ht_skip_device(hose, bus, devfn)) {
357 case 0:
358 break;
359 case 1:
360 switch (len) {
361 case 1:
362 *val = 0xff; break;
363 case 2:
364 *val = 0xffff; break;
365 default:
366 *val = 0xfffffffful; break;
367 }
368 return PCIBIOS_SUCCESSFUL;
369 default:
370 return PCIBIOS_DEVICE_NOT_FOUND;
371 }
372
373 /*
374 * Note: the caller has already checked that offset is
375 * suitably aligned and that len is 1, 2 or 4.
376 */
377 switch (len) {
378 case 1:
379 *val = in_8((u8 *)addr);
380 break;
381 case 2:
382 *val = in_le16((u16 *)addr);
383 break;
384 default:
385 *val = in_le32((u32 *)addr);
386 break;
387 }
388 return PCIBIOS_SUCCESSFUL;
389}
390
391static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
392 int offset, int len, u32 val)
393{
394 struct pci_controller *hose = bus->sysdata;
395 unsigned long addr;
396
397 struct device_node *np = pci_busdev_to_OF_node(bus, devfn);
398 if (np == NULL)
399 return PCIBIOS_DEVICE_NOT_FOUND;
400
401 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
402 if (!addr)
403 return PCIBIOS_DEVICE_NOT_FOUND;
404
405 switch (u3_ht_skip_device(hose, bus, devfn)) {
406 case 0:
407 break;
408 case 1:
409 return PCIBIOS_SUCCESSFUL;
410 default:
411 return PCIBIOS_DEVICE_NOT_FOUND;
412 }
413
414 /*
415 * Note: the caller has already checked that offset is
416 * suitably aligned and that len is 1, 2 or 4.
417 */
418 switch (len) {
419 case 1:
420 out_8((u8 *)addr, val);
421 (void) in_8((u8 *)addr);
422 break;
423 case 2:
424 out_le16((u16 *)addr, val);
425 (void) in_le16((u16 *)addr);
426 break;
427 default:
428 out_le32((u32 *)addr, val);
429 (void) in_le32((u32 *)addr);
430 break;
431 }
432 return PCIBIOS_SUCCESSFUL;
433}
434
435static struct pci_ops u3_ht_pci_ops =
436{
437 u3_ht_read_config,
438 u3_ht_write_config
439};
440
441#endif /* CONFIG_POWER4 */
442
443/*
444 * For a bandit bridge, turn on cache coherency if necessary.
445 * N.B. we could clean this up using the hose ops directly.
446 */
447static void __init
448init_bandit(struct pci_controller *bp)
449{
450 unsigned int vendev, magic;
451 int rev;
452
453 /* read the word at offset 0 in config space for device 11 */
454 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
455 udelay(2);
456 vendev = in_le32(bp->cfg_data);
457 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
458 PCI_VENDOR_ID_APPLE) {
459 /* read the revision id */
460 out_le32(bp->cfg_addr,
461 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
462 udelay(2);
463 rev = in_8(bp->cfg_data);
464 if (rev != BANDIT_REVID)
465 printk(KERN_WARNING
466 "Unknown revision %d for bandit\n", rev);
467 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
468 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
469 return;
470 }
471
472 /* read the word at offset 0x50 */
473 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
474 udelay(2);
475 magic = in_le32(bp->cfg_data);
476 if ((magic & BANDIT_COHERENT) != 0)
477 return;
478 magic |= BANDIT_COHERENT;
479 udelay(2);
480 out_le32(bp->cfg_data, magic);
481 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
482}
483
484
485/*
486 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
487 */
488static void __init
489init_p2pbridge(void)
490{
491 struct device_node *p2pbridge;
492 struct pci_controller* hose;
493 u8 bus, devfn;
494 u16 val;
495
496 /* XXX it would be better here to identify the specific
497 PCI-PCI bridge chip we have. */
498 if ((p2pbridge = find_devices("pci-bridge")) == 0
499 || p2pbridge->parent == NULL
500 || strcmp(p2pbridge->parent->name, "pci") != 0)
501 return;
502 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
503 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
504 return;
505 }
506 /* Warning: At this point, we have not yet renumbered all busses.
507 * So we must use OF walking to find out hose
508 */
509 hose = pci_find_hose_for_OF_device(p2pbridge);
510 if (!hose) {
511 DBG("Can't find hose for PCI<->PCI bridge\n");
512 return;
513 }
514 if (early_read_config_word(hose, bus, devfn,
515 PCI_BRIDGE_CONTROL, &val) < 0) {
516 printk(KERN_ERR "init_p2pbridge: couldn't read bridge control\n");
517 return;
518 }
519 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
520 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
521}
522
523/*
524 * Some Apple desktop machines have a NEC PD720100A USB2 controller
525 * on the motherboard. Open Firmware, on these, will disable the
526 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
527 * code re-enables it ;)
528 */
529static void __init
530fixup_nec_usb2(void)
531{
532 struct device_node *nec;
533
534 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
535 struct pci_controller *hose;
536 u32 data, *prop;
537 u8 bus, devfn;
538
539 prop = (u32 *)get_property(nec, "vendor-id", NULL);
540 if (prop == NULL)
541 continue;
542 if (0x1033 != *prop)
543 continue;
544 prop = (u32 *)get_property(nec, "device-id", NULL);
545 if (prop == NULL)
546 continue;
547 if (0x0035 != *prop)
548 continue;
549 prop = (u32 *)get_property(nec, "reg", NULL);
550 if (prop == NULL)
551 continue;
552 devfn = (prop[0] >> 8) & 0xff;
553 bus = (prop[0] >> 16) & 0xff;
554 if (PCI_FUNC(devfn) != 0)
555 continue;
556 hose = pci_find_hose_for_OF_device(nec);
557 if (!hose)
558 continue;
559 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
560 if (data & 1UL) {
561 printk("Found NEC PD720100A USB2 chip with disabled EHCI, fixing up...\n");
562 data &= ~1UL;
563 early_write_config_dword(hose, bus, devfn, 0xe4, data);
564 early_write_config_byte(hose, bus, devfn | 2, PCI_INTERRUPT_LINE,
565 nec->intrs[0].line);
566 }
567 }
568}
569
570void __init
571pmac_find_bridges(void)
572{
573 struct device_node *np, *root;
574 struct device_node *ht = NULL;
575
576 root = of_find_node_by_path("/");
577 if (root == NULL) {
578 printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
579 return;
580 }
581 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
582 if (np->name == NULL)
583 continue;
584 if (strcmp(np->name, "bandit") == 0
585 || strcmp(np->name, "chaos") == 0
586 || strcmp(np->name, "pci") == 0) {
587 if (add_bridge(np) == 0)
588 of_node_get(np);
589 }
590 if (strcmp(np->name, "ht") == 0) {
591 of_node_get(np);
592 ht = np;
593 }
594 }
595 of_node_put(root);
596
597 /* Probe HT last as it relies on the agp resources to be already
598 * setup
599 */
600 if (ht && add_bridge(ht) != 0)
601 of_node_put(ht);
602
603 init_p2pbridge();
604 fixup_nec_usb2();
605
606 /* We are still having some issues with the Xserve G4, enabling
607 * some offset between bus number and domains for now when we
608 * assign all busses should help for now
609 */
610 if (pci_assign_all_busses)
611 pcibios_assign_bus_offset = 0x10;
612
613#ifdef CONFIG_POWER4
614 /* There is something wrong with DMA on U3/HT. I haven't figured out
615 * the details yet, but if I set the cache line size to 128 bytes like
616 * it should, I'm getting memory corruption caused by devices like
617 * sungem (even without the MWI bit set, but maybe sungem doesn't
618 * care). Right now, it appears that setting up a 64 bytes line size
619 * works properly, 64 bytes beeing the max transfer size of HT, I
620 * suppose this is related the way HT/PCI are hooked together. I still
621 * need to dive into more specs though to be really sure of what's
622 * going on. --BenH.
623 *
624 * Ok, apparently, it's just that HT can't do more than 64 bytes
625 * transactions. MWI seem to be meaningless there as well, it may
626 * be worth nop'ing out pci_set_mwi too though I haven't done that
627 * yet.
628 *
629 * Note that it's a bit different for whatever is in the AGP slot.
630 * For now, I don't care, but this can become a real issue, we
631 * should probably hook pci_set_mwi anyway to make sure it sets
632 * the real cache line size in there.
633 */
634 if (machine_is_compatible("MacRISC4"))
635 pci_cache_line_size = 16; /* 64 bytes */
636
637 pmac_check_ht_link();
638#endif /* CONFIG_POWER4 */
639}
640
641#define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
642 | (((o) & ~3) << 24))
643
644#define GRACKLE_PICR1_STG 0x00000040
645#define GRACKLE_PICR1_LOOPSNOOP 0x00000010
646
647/* N.B. this is called before bridges is initialized, so we can't
648 use grackle_pcibios_{read,write}_config_dword. */
649static inline void grackle_set_stg(struct pci_controller* bp, int enable)
650{
651 unsigned int val;
652
653 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
654 val = in_le32(bp->cfg_data);
655 val = enable? (val | GRACKLE_PICR1_STG) :
656 (val & ~GRACKLE_PICR1_STG);
657 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
658 out_le32(bp->cfg_data, val);
659 (void)in_le32(bp->cfg_data);
660}
661
662static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
663{
664 unsigned int val;
665
666 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
667 val = in_le32(bp->cfg_data);
668 val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) :
669 (val & ~GRACKLE_PICR1_LOOPSNOOP);
670 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
671 out_le32(bp->cfg_data, val);
672 (void)in_le32(bp->cfg_data);
673}
674
675static int __init
676setup_uninorth(struct pci_controller* hose, struct reg_property* addr)
677{
678 pci_assign_all_busses = 1;
679 has_uninorth = 1;
680 hose->ops = &macrisc_pci_ops;
681 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
682 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
683 /* We "know" that the bridge at f2000000 has the PCI slots. */
684 return addr->address == 0xf2000000;
685}
686
687static void __init
688setup_bandit(struct pci_controller* hose, struct reg_property* addr)
689{
690 hose->ops = &macrisc_pci_ops;
691 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
692 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
693 init_bandit(hose);
694}
695
696static void __init
697setup_chaos(struct pci_controller* hose, struct reg_property* addr)
698{
699 /* assume a `chaos' bridge */
700 hose->ops = &chaos_pci_ops;
701 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
702 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
703}
704
705#ifdef CONFIG_POWER4
706
707static void __init setup_u3_agp(struct pci_controller* hose)
708{
709 /* On G5, we move AGP up to high bus number so we don't need
710 * to reassign bus numbers for HT. If we ever have P2P bridges
711 * on AGP, we'll have to move pci_assign_all_busses to the
712 * pci_controller structure so we enable it for AGP and not for
713 * HT childs.
714 * We hard code the address because of the different size of
715 * the reg address cell, we shall fix that by killing struct
716 * reg_property and using some accessor functions instead
717 */
718 hose->first_busno = 0xf0;
719 hose->last_busno = 0xff;
720 has_uninorth = 1;
721 hose->ops = &macrisc_pci_ops;
722 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
723 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
724
725 u3_agp = hose;
726}
727
728static void __init setup_u3_ht(struct pci_controller* hose)
729{
730 struct device_node *np = (struct device_node *)hose->arch_data;
731 int i, cur;
732
733 hose->ops = &u3_ht_pci_ops;
734
735 /* We hard code the address because of the different size of
736 * the reg address cell, we shall fix that by killing struct
737 * reg_property and using some accessor functions instead
738 */
739 hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
740
741 /*
742 * /ht node doesn't expose a "ranges" property, so we "remove" regions that
743 * have been allocated to AGP. So far, this version of the code doesn't assign
744 * any of the 0xfxxxxxxx "fine" memory regions to /ht.
745 * We need to fix that sooner or later by either parsing all child "ranges"
746 * properties or figuring out the U3 address space decoding logic and
747 * then read its configuration register (if any).
748 */
749 hose->io_base_phys = 0xf4000000;
750 hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
751 isa_io_base = (unsigned long) hose->io_base_virt;
752 hose->io_resource.name = np->full_name;
753 hose->io_resource.start = 0;
754 hose->io_resource.end = 0x003fffff;
755 hose->io_resource.flags = IORESOURCE_IO;
756 hose->pci_mem_offset = 0;
757 hose->first_busno = 0;
758 hose->last_busno = 0xef;
759 hose->mem_resources[0].name = np->full_name;
760 hose->mem_resources[0].start = 0x80000000;
761 hose->mem_resources[0].end = 0xefffffff;
762 hose->mem_resources[0].flags = IORESOURCE_MEM;
763
764 if (u3_agp == NULL) {
765 DBG("U3 has no AGP, using full resource range\n");
766 return;
767 }
768
769 /* We "remove" the AGP resources from the resources allocated to HT, that
770 * is we create "holes". However, that code does assumptions that so far
771 * happen to be true (cross fingers...), typically that resources in the
772 * AGP node are properly ordered
773 */
774 cur = 0;
775 for (i=0; i<3; i++) {
776 struct resource *res = &u3_agp->mem_resources[i];
777 if (res->flags != IORESOURCE_MEM)
778 continue;
779 /* We don't care about "fine" resources */
780 if (res->start >= 0xf0000000)
781 continue;
782 /* Check if it's just a matter of "shrinking" us in one direction */
783 if (hose->mem_resources[cur].start == res->start) {
784 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
785 cur, hose->mem_resources[cur].start, res->end + 1);
786 hose->mem_resources[cur].start = res->end + 1;
787 continue;
788 }
789 if (hose->mem_resources[cur].end == res->end) {
790 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
791 cur, hose->mem_resources[cur].end, res->start - 1);
792 hose->mem_resources[cur].end = res->start - 1;
793 continue;
794 }
795 /* No, it's not the case, we need a hole */
796 if (cur == 2) {
797 /* not enough resources to make a hole, we drop part of the range */
798 printk(KERN_WARNING "Running out of resources for /ht host !\n");
799 hose->mem_resources[cur].end = res->start - 1;
800 continue;
801 }
802 cur++;
803 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
804 cur-1, res->start - 1, cur, res->end + 1);
805 hose->mem_resources[cur].name = np->full_name;
806 hose->mem_resources[cur].flags = IORESOURCE_MEM;
807 hose->mem_resources[cur].start = res->end + 1;
808 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
809 hose->mem_resources[cur-1].end = res->start - 1;
810 }
811}
812
813#endif /* CONFIG_POWER4 */
814
815void __init
816setup_grackle(struct pci_controller *hose)
817{
818 setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
819 if (machine_is_compatible("AAPL,PowerBook1998"))
820 grackle_set_loop_snoop(hose, 1);
821#if 0 /* Disabled for now, HW problems ??? */
822 grackle_set_stg(hose, 1);
823#endif
824}
825
826static void __init pmac_process_bridge_OF_ranges(struct pci_controller *hose,
827 struct device_node *dev, int primary)
828{
829 static unsigned int static_lc_ranges[2024];
830 unsigned int *dt_ranges, *lc_ranges, *ranges, *prev;
831 unsigned int size;
832 int rlen = 0, orig_rlen;
833 int memno = 0;
834 struct resource *res;
835 int np, na = prom_n_addr_cells(dev);
836
837 np = na + 5;
838
839 /* First we try to merge ranges to fix a problem with some pmacs
840 * that can have more than 3 ranges, fortunately using contiguous
841 * addresses -- BenH
842 */
843 dt_ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
844 if (!dt_ranges)
845 return;
846 /* lc_ranges = alloc_bootmem(rlen);*/
847 lc_ranges = static_lc_ranges;
848 if (!lc_ranges)
849 return; /* what can we do here ? */
850 memcpy(lc_ranges, dt_ranges, rlen);
851 orig_rlen = rlen;
852
853 /* Let's work on a copy of the "ranges" property instead of damaging
854 * the device-tree image in memory
855 */
856 ranges = lc_ranges;
857 prev = NULL;
858 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
859 if (prev) {
860 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
861 (prev[2] + prev[na+4]) == ranges[2] &&
862 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
863 prev[na+4] += ranges[na+4];
864 ranges[0] = 0;
865 ranges += np;
866 continue;
867 }
868 }
869 prev = ranges;
870 ranges += np;
871 }
872
873 /*
874 * The ranges property is laid out as an array of elements,
875 * each of which comprises:
876 * cells 0 - 2: a PCI address
877 * cells 3 or 3+4: a CPU physical address
878 * (size depending on dev->n_addr_cells)
879 * cells 4+5 or 5+6: the size of the range
880 */
881 ranges = lc_ranges;
882 rlen = orig_rlen;
883 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
884 res = NULL;
885 size = ranges[na+4];
886 switch (ranges[0] >> 24) {
887 case 1: /* I/O space */
888 if (ranges[2] != 0)
889 break;
890 hose->io_base_phys = ranges[na+2];
891 /* limit I/O space to 16MB */
892 if (size > 0x01000000)
893 size = 0x01000000;
894 hose->io_base_virt = ioremap(ranges[na+2], size);
895 if (primary)
896 isa_io_base = (unsigned long) hose->io_base_virt;
897 res = &hose->io_resource;
898 res->flags = IORESOURCE_IO;
899 res->start = ranges[2];
900 break;
901 case 2: /* memory space */
902 memno = 0;
903 if (ranges[1] == 0 && ranges[2] == 0
904 && ranges[na+4] <= (16 << 20)) {
905 /* 1st 16MB, i.e. ISA memory area */
906#if 0
907 if (primary)
908 isa_mem_base = ranges[na+2];
909#endif
910 memno = 1;
911 }
912 while (memno < 3 && hose->mem_resources[memno].flags)
913 ++memno;
914 if (memno == 0)
915 hose->pci_mem_offset = ranges[na+2] - ranges[2];
916 if (memno < 3) {
917 res = &hose->mem_resources[memno];
918 res->flags = IORESOURCE_MEM;
919 res->start = ranges[na+2];
920 }
921 break;
922 }
923 if (res != NULL) {
924 res->name = dev->full_name;
925 res->end = res->start + size - 1;
926 res->parent = NULL;
927 res->sibling = NULL;
928 res->child = NULL;
929 }
930 ranges += np;
931 }
932}
933
934/*
935 * We assume that if we have a G3 powermac, we have one bridge called
936 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
937 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
938 */
939static int __init add_bridge(struct device_node *dev)
940{
941 int len;
942 struct pci_controller *hose;
943 struct reg_property *addr;
944 char* disp_name;
945 int *bus_range;
946 int primary = 1;
947
948 DBG("Adding PCI host bridge %s\n", dev->full_name);
949
950 addr = (struct reg_property *) get_property(dev, "reg", &len);
951 if (addr == NULL || len < sizeof(*addr)) {
952 printk(KERN_WARNING "Can't use %s: no address\n",
953 dev->full_name);
954 return -ENODEV;
955 }
956 bus_range = (int *) get_property(dev, "bus-range", &len);
957 if (bus_range == NULL || len < 2 * sizeof(int)) {
958 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
959 dev->full_name);
960 }
961
962 hose = pcibios_alloc_controller();
963 if (!hose)
964 return -ENOMEM;
965 hose->arch_data = dev;
966 hose->first_busno = bus_range ? bus_range[0] : 0;
967 hose->last_busno = bus_range ? bus_range[1] : 0xff;
968
969 disp_name = NULL;
970#ifdef CONFIG_POWER4
971 if (device_is_compatible(dev, "u3-agp")) {
972 setup_u3_agp(hose, addr);
973 disp_name = "U3-AGP";
974 primary = 0;
975 } else if (device_is_compatible(dev, "u3-ht")) {
976 setup_u3_ht(hose, addr);
977 disp_name = "U3-HT";
978 primary = 1;
979 } else
980#endif /* CONFIG_POWER4 */
981 if (device_is_compatible(dev, "uni-north")) {
982 primary = setup_uninorth(hose, addr);
983 disp_name = "UniNorth";
984 } else if (strcmp(dev->name, "pci") == 0) {
985 /* XXX assume this is a mpc106 (grackle) */
986 setup_grackle(hose);
987 disp_name = "Grackle (MPC106)";
988 } else if (strcmp(dev->name, "bandit") == 0) {
989 setup_bandit(hose, addr);
990 disp_name = "Bandit";
991 } else if (strcmp(dev->name, "chaos") == 0) {
992 setup_chaos(hose, addr);
993 disp_name = "Chaos";
994 primary = 0;
995 }
996 printk(KERN_INFO "Found %s PCI host bridge at 0x%08x. Firmware bus number: %d->%d\n",
997 disp_name, addr->address, hose->first_busno, hose->last_busno);
998 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
999 hose, hose->cfg_addr, hose->cfg_data);
1000
1001 /* Interpret the "ranges" property */
1002 /* This also maps the I/O region and sets isa_io/mem_base */
1003 pci_process_bridge_OF_ranges(hose, dev, primary);
1004
1005 /* Fixup "bus-range" OF property */
1006 fixup_bus_range(dev);
1007
1008 return 0;
1009}
1010
1011static void __init
1012pcibios_fixup_OF_interrupts(void)
1013{
1014 struct pci_dev* dev = NULL;
1015
1016 /*
1017 * Open Firmware often doesn't initialize the
1018 * PCI_INTERRUPT_LINE config register properly, so we
1019 * should find the device node and apply the interrupt
1020 * obtained from the OF device-tree
1021 */
1022 for_each_pci_dev(dev) {
1023 struct device_node *node;
1024 node = pci_device_to_OF_node(dev);
1025 /* this is the node, see if it has interrupts */
1026 if (node && node->n_intrs > 0)
1027 dev->irq = node->intrs[0].line;
1028 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1029 }
1030}
1031
1032void __init
1033pmac_pcibios_fixup(void)
1034{
1035 /* Fixup interrupts according to OF tree */
1036 pcibios_fixup_OF_interrupts();
1037}
1038
1039int
1040pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
1041{
1042 struct device_node* node;
1043 int updatecfg = 0;
1044 int uninorth_child;
1045
1046 node = pci_device_to_OF_node(dev);
1047
1048 /* We don't want to enable USB controllers absent from the OF tree
1049 * (iBook second controller)
1050 */
1051 if (dev->vendor == PCI_VENDOR_ID_APPLE
1052 && (dev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10))
1053 && !node) {
1054 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
1055 pci_name(dev));
1056 return -EINVAL;
1057 }
1058
1059 if (!node)
1060 return 0;
1061
1062 uninorth_child = node->parent &&
1063 device_is_compatible(node->parent, "uni-north");
1064
1065 /* Firewire & GMAC were disabled after PCI probe, the driver is
1066 * claiming them, we must re-enable them now.
1067 */
1068 if (uninorth_child && !strcmp(node->name, "firewire") &&
1069 (device_is_compatible(node, "pci106b,18") ||
1070 device_is_compatible(node, "pci106b,30") ||
1071 device_is_compatible(node, "pci11c1,5811"))) {
1072 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
1073 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
1074 updatecfg = 1;
1075 }
1076 if (uninorth_child && !strcmp(node->name, "ethernet") &&
1077 device_is_compatible(node, "gmac")) {
1078 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
1079 updatecfg = 1;
1080 }
1081
1082 if (updatecfg) {
1083 u16 cmd;
1084
1085 /*
1086 * Make sure PCI is correctly configured
1087 *
1088 * We use old pci_bios versions of the function since, by
1089 * default, gmac is not powered up, and so will be absent
1090 * from the kernel initial PCI lookup.
1091 *
1092 * Should be replaced by 2.4 new PCI mechanisms and really
1093 * register the device.
1094 */
1095 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1096 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
1097 pci_write_config_word(dev, PCI_COMMAND, cmd);
1098 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
1099 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1100 }
1101
1102 return 0;
1103}
1104
1105/* We power down some devices after they have been probed. They'll
1106 * be powered back on later on
1107 */
1108void __init
1109pmac_pcibios_after_init(void)
1110{
1111 struct device_node* nd;
1112
1113#ifdef CONFIG_BLK_DEV_IDE
1114 struct pci_dev *dev = NULL;
1115
1116 /* OF fails to initialize IDE controllers on macs
1117 * (and maybe other machines)
1118 *
1119 * Ideally, this should be moved to the IDE layer, but we need
1120 * to check specifically with Andre Hedrick how to do it cleanly
1121 * since the common IDE code seem to care about the fact that the
1122 * BIOS may have disabled a controller.
1123 *
1124 * -- BenH
1125 */
1126 for_each_pci_dev(dev) {
1127 if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE)
1128 pci_enable_device(dev);
1129 }
1130#endif /* CONFIG_BLK_DEV_IDE */
1131
1132 nd = find_devices("firewire");
1133 while (nd) {
1134 if (nd->parent && (device_is_compatible(nd, "pci106b,18") ||
1135 device_is_compatible(nd, "pci106b,30") ||
1136 device_is_compatible(nd, "pci11c1,5811"))
1137 && device_is_compatible(nd->parent, "uni-north")) {
1138 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1139 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1140 }
1141 nd = nd->next;
1142 }
1143 nd = find_devices("ethernet");
1144 while (nd) {
1145 if (nd->parent && device_is_compatible(nd, "gmac")
1146 && device_is_compatible(nd->parent, "uni-north"))
1147 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1148 nd = nd->next;
1149 }
1150}
1151
1152#ifdef CONFIG_PPC64
1153static void __init pmac_fixup_phb_resources(void)
1154{
1155 struct pci_controller *hose, *tmp;
1156
1157 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1158 unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
1159 hose->io_resource.start += offset;
1160 hose->io_resource.end += offset;
1161 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
1162 hose->global_number,
1163 hose->io_resource.start, hose->io_resource.end);
1164 }
1165}
1166
1167void __init pmac_pci_init(void)
1168{
1169 struct device_node *np, *root;
1170 struct device_node *ht = NULL;
1171
1172 /* Probe root PCI hosts, that is on U3 the AGP host and the
1173 * HyperTransport host. That one is actually "kept" around
1174 * and actually added last as it's resource management relies
1175 * on the AGP resources to have been setup first
1176 */
1177 root = of_find_node_by_path("/");
1178 if (root == NULL) {
1179 printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
1180 return;
1181 }
1182 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
1183 if (np->name == NULL)
1184 continue;
1185 if (strcmp(np->name, "pci") == 0) {
1186 if (add_bridge(np) == 0)
1187 of_node_get(np);
1188 }
1189 if (strcmp(np->name, "ht") == 0) {
1190 of_node_get(np);
1191 ht = np;
1192 }
1193 }
1194 of_node_put(root);
1195
1196 /* Now setup the HyperTransport host if we found any
1197 */
1198 if (ht && add_bridge(ht) != 0)
1199 of_node_put(ht);
1200
1201 /* Fixup the IO resources on our host bridges as the common code
1202 * does it only for childs of the host bridges
1203 */
1204 pmac_fixup_phb_resources();
1205
1206 /* Setup the linkage between OF nodes and PHBs */
1207 pci_devs_phb_init();
1208
1209 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
1210 * assume there is no P2P bridge on the AGP bus, which should be a
1211 * safe assumptions hopefully.
1212 */
1213 if (u3_agp) {
1214 struct device_node *np = u3_agp->arch_data;
1215 PCI_DN(np)->busno = 0xf0;
1216 for (np = np->child; np; np = np->sibling)
1217 PCI_DN(np)->busno = 0xf0;
1218 }
1219
1220 pmac_check_ht_link();
1221
1222 /* Tell pci.c to not use the common resource allocation mecanism */
1223 pci_probe_only = 1;
1224
1225 /* Allow all IO */
1226 io_page_mask = -1;
1227}
1228#endif
1229
1230#ifdef CONFIG_PPC32
1231void pmac_pci_fixup_cardbus(struct pci_dev* dev)
1232{
1233 if (_machine != _MACH_Pmac)
1234 return;
1235 /*
1236 * Fix the interrupt routing on the various cardbus bridges
1237 * used on powerbooks
1238 */
1239 if (dev->vendor != PCI_VENDOR_ID_TI)
1240 return;
1241 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1242 dev->device == PCI_DEVICE_ID_TI_1131) {
1243 u8 val;
1244 /* Enable PCI interrupt */
1245 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1246 pci_write_config_byte(dev, 0x91, val | 0x30);
1247 /* Disable ISA interrupt mode */
1248 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1249 pci_write_config_byte(dev, 0x92, val & ~0x06);
1250 }
1251 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1252 dev->device == PCI_DEVICE_ID_TI_1211 ||
1253 dev->device == PCI_DEVICE_ID_TI_1410 ||
1254 dev->device == PCI_DEVICE_ID_TI_1510) {
1255 u8 val;
1256 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1257 signal out the MFUNC0 pin */
1258 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1259 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1260 /* Disable ISA interrupt mode */
1261 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1262 pci_write_config_byte(dev, 0x92, val & ~0x06);
1263 }
1264}
1265
1266DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1267
1268void pmac_pci_fixup_pciata(struct pci_dev* dev)
1269{
1270 u8 progif = 0;
1271
1272 /*
1273 * On PowerMacs, we try to switch any PCI ATA controller to
1274 * fully native mode
1275 */
1276 if (_machine != _MACH_Pmac)
1277 return;
1278 /* Some controllers don't have the class IDE */
1279 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1280 switch(dev->device) {
1281 case PCI_DEVICE_ID_PROMISE_20246:
1282 case PCI_DEVICE_ID_PROMISE_20262:
1283 case PCI_DEVICE_ID_PROMISE_20263:
1284 case PCI_DEVICE_ID_PROMISE_20265:
1285 case PCI_DEVICE_ID_PROMISE_20267:
1286 case PCI_DEVICE_ID_PROMISE_20268:
1287 case PCI_DEVICE_ID_PROMISE_20269:
1288 case PCI_DEVICE_ID_PROMISE_20270:
1289 case PCI_DEVICE_ID_PROMISE_20271:
1290 case PCI_DEVICE_ID_PROMISE_20275:
1291 case PCI_DEVICE_ID_PROMISE_20276:
1292 case PCI_DEVICE_ID_PROMISE_20277:
1293 goto good;
1294 }
1295 /* Others, check PCI class */
1296 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1297 return;
1298 good:
1299 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1300 if ((progif & 5) != 5) {
1301 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", pci_name(dev));
1302 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1303 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1304 (progif & 5) != 5)
1305 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1306 }
1307}
1308DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1309#endif
1310
1311/*
1312 * Disable second function on K2-SATA, it's broken
1313 * and disable IO BARs on first one
1314 */
1315static void fixup_k2_sata(struct pci_dev* dev)
1316{
1317 int i;
1318 u16 cmd;
1319
1320 if (PCI_FUNC(dev->devfn) > 0) {
1321 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1322 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1323 pci_write_config_word(dev, PCI_COMMAND, cmd);
1324 for (i = 0; i < 6; i++) {
1325 dev->resource[i].start = dev->resource[i].end = 0;
1326 dev->resource[i].flags = 0;
1327 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1328 }
1329 } else {
1330 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1331 cmd &= ~PCI_COMMAND_IO;
1332 pci_write_config_word(dev, PCI_COMMAND, cmd);
1333 for (i = 0; i < 5; i++) {
1334 dev->resource[i].start = dev->resource[i].end = 0;
1335 dev->resource[i].flags = 0;
1336 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1337 }
1338 }
1339}
1340DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
1341
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 19:42:20 -0500