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Diffstat (limited to 'arch/powerpc/platforms/86xx/mpc86xx_hpcn.c')
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_hpcn.c26
1 files changed, 15 insertions, 11 deletions
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index 146da3001c6..0b1b52168bb 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -52,6 +52,7 @@ unsigned long pci_dram_offset = 0;
52#endif 52#endif
53 53
54 54
55#ifdef CONFIG_PCI
55static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc, 56static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc,
56 struct pt_regs *regs) 57 struct pt_regs *regs)
57{ 58{
@@ -60,40 +61,43 @@ static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc,
60 generic_handle_irq(cascade_irq, regs); 61 generic_handle_irq(cascade_irq, regs);
61 desc->chip->eoi(irq); 62 desc->chip->eoi(irq);
62} 63}
64#endif /* CONFIG_PCI */
63 65
64void __init 66void __init
65mpc86xx_hpcn_init_irq(void) 67mpc86xx_hpcn_init_irq(void)
66{ 68{
67 struct mpic *mpic1; 69 struct mpic *mpic1;
68 struct device_node *np, *cascade_node = NULL; 70 struct device_node *np;
71 struct resource res;
72#ifdef CONFIG_PCI
73 struct device_node *cascade_node = NULL;
69 int cascade_irq; 74 int cascade_irq;
70 phys_addr_t openpic_paddr; 75#endif
71 76
77 /* Determine PIC address. */
72 np = of_find_node_by_type(NULL, "open-pic"); 78 np = of_find_node_by_type(NULL, "open-pic");
73 if (np == NULL) 79 if (np == NULL)
74 return; 80 return;
75 81 of_address_to_resource(np, 0, &res);
76 /* Determine the Physical Address of the OpenPIC regs */
77 openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
78 82
79 /* Alloc mpic structure and per isu has 16 INT entries. */ 83 /* Alloc mpic structure and per isu has 16 INT entries. */
80 mpic1 = mpic_alloc(np, openpic_paddr, 84 mpic1 = mpic_alloc(np, res.start,
81 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, 85 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
82 16, NR_IRQS - 4, 86 16, NR_IRQS - 4,
83 " MPIC "); 87 " MPIC ");
84 BUG_ON(mpic1 == NULL); 88 BUG_ON(mpic1 == NULL);
85 89
86 mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10000); 90 mpic_assign_isu(mpic1, 0, res.start + 0x10000);
87 91
88 /* 48 Internal Interrupts */ 92 /* 48 Internal Interrupts */
89 mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10200); 93 mpic_assign_isu(mpic1, 1, res.start + 0x10200);
90 mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10400); 94 mpic_assign_isu(mpic1, 2, res.start + 0x10400);
91 mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10600); 95 mpic_assign_isu(mpic1, 3, res.start + 0x10600);
92 96
93 /* 16 External interrupts 97 /* 16 External interrupts
94 * Moving them from [0 - 15] to [64 - 79] 98 * Moving them from [0 - 15] to [64 - 79]
95 */ 99 */
96 mpic_assign_isu(mpic1, 4, openpic_paddr + 0x10000); 100 mpic_assign_isu(mpic1, 4, res.start + 0x10000);
97 101
98 mpic_init(mpic1); 102 mpic_init(mpic1);
99 103