diff options
Diffstat (limited to 'arch/powerpc/include/asm/system.h')
-rw-r--r-- | arch/powerpc/include/asm/system.h | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h index d6648c14332..2a4be19a92c 100644 --- a/arch/powerpc/include/asm/system.h +++ b/arch/powerpc/include/asm/system.h | |||
@@ -23,15 +23,17 @@ | |||
23 | * read_barrier_depends() prevents data-dependent loads being reordered | 23 | * read_barrier_depends() prevents data-dependent loads being reordered |
24 | * across this point (nop on PPC). | 24 | * across this point (nop on PPC). |
25 | * | 25 | * |
26 | * We have to use the sync instructions for mb(), since lwsync doesn't | 26 | * *mb() variants without smp_ prefix must order all types of memory |
27 | * order loads with respect to previous stores. Lwsync is fine for | 27 | * operations with one another. sync is the only instruction sufficient |
28 | * rmb(), though. Note that rmb() actually uses a sync on 32-bit | 28 | * to do this. |
29 | * architectures. | ||
30 | * | 29 | * |
31 | * For wmb(), we use sync since wmb is used in drivers to order | 30 | * For the smp_ barriers, ordering is for cacheable memory operations |
32 | * stores to system memory with respect to writes to the device. | 31 | * only. We have to use the sync instruction for smp_mb(), since lwsync |
33 | * However, smp_wmb() can be a lighter-weight lwsync or eieio barrier | 32 | * doesn't order loads with respect to previous stores. Lwsync can be |
34 | * on SMP since it is only used to order updates to system memory. | 33 | * used for smp_rmb() and smp_wmb(). |
34 | * | ||
35 | * However, on CPUs that don't support lwsync, lwsync actually maps to a | ||
36 | * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio. | ||
35 | */ | 37 | */ |
36 | #define mb() __asm__ __volatile__ ("sync" : : : "memory") | 38 | #define mb() __asm__ __volatile__ ("sync" : : : "memory") |
37 | #define rmb() __asm__ __volatile__ ("sync" : : : "memory") | 39 | #define rmb() __asm__ __volatile__ ("sync" : : : "memory") |
@@ -45,14 +47,14 @@ | |||
45 | #ifdef CONFIG_SMP | 47 | #ifdef CONFIG_SMP |
46 | 48 | ||
47 | #ifdef __SUBARCH_HAS_LWSYNC | 49 | #ifdef __SUBARCH_HAS_LWSYNC |
48 | # define SMPWMB lwsync | 50 | # define SMPWMB LWSYNC |
49 | #else | 51 | #else |
50 | # define SMPWMB eieio | 52 | # define SMPWMB eieio |
51 | #endif | 53 | #endif |
52 | 54 | ||
53 | #define smp_mb() mb() | 55 | #define smp_mb() mb() |
54 | #define smp_rmb() rmb() | 56 | #define smp_rmb() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory") |
55 | #define smp_wmb() __asm__ __volatile__ (__stringify(SMPWMB) : : :"memory") | 57 | #define smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory") |
56 | #define smp_read_barrier_depends() read_barrier_depends() | 58 | #define smp_read_barrier_depends() read_barrier_depends() |
57 | #else | 59 | #else |
58 | #define smp_mb() barrier() | 60 | #define smp_mb() barrier() |