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-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts289
1 files changed, 145 insertions, 144 deletions
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 1f470c6a1c6..fa298a8c81c 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8548 CDS Device Tree Source 2 * MPC8548 CDS Device Tree Source
3 * 3 *
4 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8548CDS"; 15 model = "MPC8548CDS";
@@ -36,11 +37,11 @@
36 37
37 PowerPC,8548@0 { 38 PowerPC,8548@0 {
38 device_type = "cpu"; 39 device_type = "cpu";
39 reg = <0>; 40 reg = <0x0>;
40 d-cache-line-size = <20>; // 32 bytes 41 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <20>; // 32 bytes 42 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <8000>; // L1, 32K 43 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <8000>; // L1, 32K 44 i-cache-size = <0x8000>; // L1, 32K
44 timebase-frequency = <0>; // 33 MHz, from uboot 45 timebase-frequency = <0>; // 33 MHz, from uboot
45 bus-frequency = <0>; // 166 MHz 46 bus-frequency = <0>; // 166 MHz
46 clock-frequency = <0>; // 825 MHz, from uboot 47 clock-frequency = <0>; // 825 MHz, from uboot
@@ -49,31 +50,31 @@
49 50
50 memory { 51 memory {
51 device_type = "memory"; 52 device_type = "memory";
52 reg = <00000000 08000000>; // 128M at 0x0 53 reg = <0x0 0x8000000>; // 128M at 0x0
53 }; 54 };
54 55
55 soc8548@e0000000 { 56 soc8548@e0000000 {
56 #address-cells = <1>; 57 #address-cells = <1>;
57 #size-cells = <1>; 58 #size-cells = <1>;
58 device_type = "soc"; 59 device_type = "soc";
59 ranges = <00000000 e0000000 00100000>; 60 ranges = <0x0 0xe0000000 0x100000>;
60 reg = <e0000000 00001000>; // CCSRBAR 61 reg = <0xe0000000 0x1000>; // CCSRBAR
61 bus-frequency = <0>; 62 bus-frequency = <0>;
62 63
63 memory-controller@2000 { 64 memory-controller@2000 {
64 compatible = "fsl,8548-memory-controller"; 65 compatible = "fsl,8548-memory-controller";
65 reg = <2000 1000>; 66 reg = <0x2000 0x1000>;
66 interrupt-parent = <&mpic>; 67 interrupt-parent = <&mpic>;
67 interrupts = <12 2>; 68 interrupts = <18 2>;
68 }; 69 };
69 70
70 l2-cache-controller@20000 { 71 l2-cache-controller@20000 {
71 compatible = "fsl,8548-l2-cache-controller"; 72 compatible = "fsl,8548-l2-cache-controller";
72 reg = <20000 1000>; 73 reg = <0x20000 0x1000>;
73 cache-line-size = <20>; // 32 bytes 74 cache-line-size = <32>; // 32 bytes
74 cache-size = <80000>; // L2, 512K 75 cache-size = <0x80000>; // L2, 512K
75 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
76 interrupts = <10 2>; 77 interrupts = <16 2>;
77 }; 78 };
78 79
79 i2c@3000 { 80 i2c@3000 {
@@ -81,8 +82,8 @@
81 #size-cells = <0>; 82 #size-cells = <0>;
82 cell-index = <0>; 83 cell-index = <0>;
83 compatible = "fsl-i2c"; 84 compatible = "fsl-i2c";
84 reg = <3000 100>; 85 reg = <0x3000 0x100>;
85 interrupts = <2b 2>; 86 interrupts = <43 2>;
86 interrupt-parent = <&mpic>; 87 interrupt-parent = <&mpic>;
87 dfsrr; 88 dfsrr;
88 }; 89 };
@@ -92,8 +93,8 @@
92 #size-cells = <0>; 93 #size-cells = <0>;
93 cell-index = <1>; 94 cell-index = <1>;
94 compatible = "fsl-i2c"; 95 compatible = "fsl-i2c";
95 reg = <3100 100>; 96 reg = <0x3100 0x100>;
96 interrupts = <2b 2>; 97 interrupts = <43 2>;
97 interrupt-parent = <&mpic>; 98 interrupt-parent = <&mpic>;
98 dfsrr; 99 dfsrr;
99 }; 100 };
@@ -102,30 +103,30 @@
102 #address-cells = <1>; 103 #address-cells = <1>;
103 #size-cells = <0>; 104 #size-cells = <0>;
104 compatible = "fsl,gianfar-mdio"; 105 compatible = "fsl,gianfar-mdio";
105 reg = <24520 20>; 106 reg = <0x24520 0x20>;
106 107
107 phy0: ethernet-phy@0 { 108 phy0: ethernet-phy@0 {
108 interrupt-parent = <&mpic>; 109 interrupt-parent = <&mpic>;
109 interrupts = <5 1>; 110 interrupts = <5 1>;
110 reg = <0>; 111 reg = <0x0>;
111 device_type = "ethernet-phy"; 112 device_type = "ethernet-phy";
112 }; 113 };
113 phy1: ethernet-phy@1 { 114 phy1: ethernet-phy@1 {
114 interrupt-parent = <&mpic>; 115 interrupt-parent = <&mpic>;
115 interrupts = <5 1>; 116 interrupts = <5 1>;
116 reg = <1>; 117 reg = <0x1>;
117 device_type = "ethernet-phy"; 118 device_type = "ethernet-phy";
118 }; 119 };
119 phy2: ethernet-phy@2 { 120 phy2: ethernet-phy@2 {
120 interrupt-parent = <&mpic>; 121 interrupt-parent = <&mpic>;
121 interrupts = <5 1>; 122 interrupts = <5 1>;
122 reg = <2>; 123 reg = <0x2>;
123 device_type = "ethernet-phy"; 124 device_type = "ethernet-phy";
124 }; 125 };
125 phy3: ethernet-phy@3 { 126 phy3: ethernet-phy@3 {
126 interrupt-parent = <&mpic>; 127 interrupt-parent = <&mpic>;
127 interrupts = <5 1>; 128 interrupts = <5 1>;
128 reg = <3>; 129 reg = <0x3>;
129 device_type = "ethernet-phy"; 130 device_type = "ethernet-phy";
130 }; 131 };
131 }; 132 };
@@ -135,9 +136,9 @@
135 device_type = "network"; 136 device_type = "network";
136 model = "eTSEC"; 137 model = "eTSEC";
137 compatible = "gianfar"; 138 compatible = "gianfar";
138 reg = <24000 1000>; 139 reg = <0x24000 0x1000>;
139 local-mac-address = [ 00 00 00 00 00 00 ]; 140 local-mac-address = [ 00 00 00 00 00 00 ];
140 interrupts = <1d 2 1e 2 22 2>; 141 interrupts = <29 2 30 2 34 2>;
141 interrupt-parent = <&mpic>; 142 interrupt-parent = <&mpic>;
142 phy-handle = <&phy0>; 143 phy-handle = <&phy0>;
143 }; 144 };
@@ -147,9 +148,9 @@
147 device_type = "network"; 148 device_type = "network";
148 model = "eTSEC"; 149 model = "eTSEC";
149 compatible = "gianfar"; 150 compatible = "gianfar";
150 reg = <25000 1000>; 151 reg = <0x25000 0x1000>;
151 local-mac-address = [ 00 00 00 00 00 00 ]; 152 local-mac-address = [ 00 00 00 00 00 00 ];
152 interrupts = <23 2 24 2 28 2>; 153 interrupts = <35 2 36 2 40 2>;
153 interrupt-parent = <&mpic>; 154 interrupt-parent = <&mpic>;
154 phy-handle = <&phy1>; 155 phy-handle = <&phy1>;
155 }; 156 };
@@ -160,9 +161,9 @@
160 device_type = "network"; 161 device_type = "network";
161 model = "eTSEC"; 162 model = "eTSEC";
162 compatible = "gianfar"; 163 compatible = "gianfar";
163 reg = <26000 1000>; 164 reg = <0x26000 0x1000>;
164 local-mac-address = [ 00 00 00 00 00 00 ]; 165 local-mac-address = [ 00 00 00 00 00 00 ];
165 interrupts = <1f 2 20 2 21 2>; 166 interrupts = <31 2 32 2 33 2>;
166 interrupt-parent = <&mpic>; 167 interrupt-parent = <&mpic>;
167 phy-handle = <&phy2>; 168 phy-handle = <&phy2>;
168 }; 169 };
@@ -172,9 +173,9 @@
172 device_type = "network"; 173 device_type = "network";
173 model = "eTSEC"; 174 model = "eTSEC";
174 compatible = "gianfar"; 175 compatible = "gianfar";
175 reg = <27000 1000>; 176 reg = <0x27000 0x1000>;
176 local-mac-address = [ 00 00 00 00 00 00 ]; 177 local-mac-address = [ 00 00 00 00 00 00 ];
177 interrupts = <25 2 26 2 27 2>; 178 interrupts = <37 2 38 2 39 2>;
178 interrupt-parent = <&mpic>; 179 interrupt-parent = <&mpic>;
179 phy-handle = <&phy3>; 180 phy-handle = <&phy3>;
180 }; 181 };
@@ -184,9 +185,9 @@
184 cell-index = <0>; 185 cell-index = <0>;
185 device_type = "serial"; 186 device_type = "serial";
186 compatible = "ns16550"; 187 compatible = "ns16550";
187 reg = <4500 100>; // reg base, size 188 reg = <0x4500 0x100>; // reg base, size
188 clock-frequency = <0>; // should we fill in in uboot? 189 clock-frequency = <0>; // should we fill in in uboot?
189 interrupts = <2a 2>; 190 interrupts = <42 2>;
190 interrupt-parent = <&mpic>; 191 interrupt-parent = <&mpic>;
191 }; 192 };
192 193
@@ -194,15 +195,15 @@
194 cell-index = <1>; 195 cell-index = <1>;
195 device_type = "serial"; 196 device_type = "serial";
196 compatible = "ns16550"; 197 compatible = "ns16550";
197 reg = <4600 100>; // reg base, size 198 reg = <0x4600 0x100>; // reg base, size
198 clock-frequency = <0>; // should we fill in in uboot? 199 clock-frequency = <0>; // should we fill in in uboot?
199 interrupts = <2a 2>; 200 interrupts = <42 2>;
200 interrupt-parent = <&mpic>; 201 interrupt-parent = <&mpic>;
201 }; 202 };
202 203
203 global-utilities@e0000 { //global utilities reg 204 global-utilities@e0000 { //global utilities reg
204 compatible = "fsl,mpc8548-guts"; 205 compatible = "fsl,mpc8548-guts";
205 reg = <e0000 1000>; 206 reg = <0xe0000 0x1000>;
206 fsl,has-rstcr; 207 fsl,has-rstcr;
207 }; 208 };
208 209
@@ -211,7 +212,7 @@
211 interrupt-controller; 212 interrupt-controller;
212 #address-cells = <0>; 213 #address-cells = <0>;
213 #interrupt-cells = <2>; 214 #interrupt-cells = <2>;
214 reg = <40000 40000>; 215 reg = <0x40000 0x40000>;
215 compatible = "chrp,open-pic"; 216 compatible = "chrp,open-pic";
216 device_type = "open-pic"; 217 device_type = "open-pic";
217 big-endian; 218 big-endian;
@@ -220,139 +221,139 @@
220 221
221 pci0: pci@e0008000 { 222 pci0: pci@e0008000 {
222 cell-index = <0>; 223 cell-index = <0>;
223 interrupt-map-mask = <f800 0 0 7>; 224 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
224 interrupt-map = < 225 interrupt-map = <
225 /* IDSEL 0x4 (PCIX Slot 2) */ 226 /* IDSEL 0x4 (PCIX Slot 2) */
226 02000 0 0 1 &mpic 0 1 227 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
227 02000 0 0 2 &mpic 1 1 228 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
228 02000 0 0 3 &mpic 2 1 229 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
229 02000 0 0 4 &mpic 3 1 230 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
230 231
231 /* IDSEL 0x5 (PCIX Slot 3) */ 232 /* IDSEL 0x5 (PCIX Slot 3) */
232 02800 0 0 1 &mpic 1 1 233 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
233 02800 0 0 2 &mpic 2 1 234 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
234 02800 0 0 3 &mpic 3 1 235 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
235 02800 0 0 4 &mpic 0 1 236 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
236 237
237 /* IDSEL 0x6 (PCIX Slot 4) */ 238 /* IDSEL 0x6 (PCIX Slot 4) */
238 03000 0 0 1 &mpic 2 1 239 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
239 03000 0 0 2 &mpic 3 1 240 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
240 03000 0 0 3 &mpic 0 1 241 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
241 03000 0 0 4 &mpic 1 1 242 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
242 243
243 /* IDSEL 0x8 (PCIX Slot 5) */ 244 /* IDSEL 0x8 (PCIX Slot 5) */
244 04000 0 0 1 &mpic 0 1 245 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
245 04000 0 0 2 &mpic 1 1 246 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
246 04000 0 0 3 &mpic 2 1 247 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
247 04000 0 0 4 &mpic 3 1 248 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
248 249
249 /* IDSEL 0xC (Tsi310 bridge) */ 250 /* IDSEL 0xC (Tsi310 bridge) */
250 06000 0 0 1 &mpic 0 1 251 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
251 06000 0 0 2 &mpic 1 1 252 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
252 06000 0 0 3 &mpic 2 1 253 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
253 06000 0 0 4 &mpic 3 1 254 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
254 255
255 /* IDSEL 0x14 (Slot 2) */ 256 /* IDSEL 0x14 (Slot 2) */
256 0a000 0 0 1 &mpic 0 1 257 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
257 0a000 0 0 2 &mpic 1 1 258 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
258 0a000 0 0 3 &mpic 2 1 259 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
259 0a000 0 0 4 &mpic 3 1 260 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
260 261
261 /* IDSEL 0x15 (Slot 3) */ 262 /* IDSEL 0x15 (Slot 3) */
262 0a800 0 0 1 &mpic 1 1 263 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
263 0a800 0 0 2 &mpic 2 1 264 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
264 0a800 0 0 3 &mpic 3 1 265 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
265 0a800 0 0 4 &mpic 0 1 266 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
266 267
267 /* IDSEL 0x16 (Slot 4) */ 268 /* IDSEL 0x16 (Slot 4) */
268 0b000 0 0 1 &mpic 2 1 269 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
269 0b000 0 0 2 &mpic 3 1 270 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
270 0b000 0 0 3 &mpic 0 1 271 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
271 0b000 0 0 4 &mpic 1 1 272 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
272 273
273 /* IDSEL 0x18 (Slot 5) */ 274 /* IDSEL 0x18 (Slot 5) */
274 0c000 0 0 1 &mpic 0 1 275 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
275 0c000 0 0 2 &mpic 1 1 276 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
276 0c000 0 0 3 &mpic 2 1 277 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
277 0c000 0 0 4 &mpic 3 1 278 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
278 279
279 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ 280 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
280 0E000 0 0 1 &mpic 0 1 281 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
281 0E000 0 0 2 &mpic 1 1 282 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
282 0E000 0 0 3 &mpic 2 1 283 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
283 0E000 0 0 4 &mpic 3 1>; 284 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
284 285
285 interrupt-parent = <&mpic>; 286 interrupt-parent = <&mpic>;
286 interrupts = <18 2>; 287 interrupts = <24 2>;
287 bus-range = <0 0>; 288 bus-range = <0 0>;
288 ranges = <02000000 0 80000000 80000000 0 10000000 289 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
289 01000000 0 00000000 e2000000 0 00800000>; 290 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
290 clock-frequency = <3f940aa>; 291 clock-frequency = <66666666>;
291 #interrupt-cells = <1>; 292 #interrupt-cells = <1>;
292 #size-cells = <2>; 293 #size-cells = <2>;
293 #address-cells = <3>; 294 #address-cells = <3>;
294 reg = <e0008000 1000>; 295 reg = <0xe0008000 0x1000>;
295 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 296 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
296 device_type = "pci"; 297 device_type = "pci";
297 298
298 pci_bridge@1c { 299 pci_bridge@1c {
299 interrupt-map-mask = <f800 0 0 7>; 300 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
300 interrupt-map = < 301 interrupt-map = <
301 302
302 /* IDSEL 0x00 (PrPMC Site) */ 303 /* IDSEL 0x00 (PrPMC Site) */
303 0000 0 0 1 &mpic 0 1 304 0000 0x0 0x0 0x1 &mpic 0x0 0x1
304 0000 0 0 2 &mpic 1 1 305 0000 0x0 0x0 0x2 &mpic 0x1 0x1
305 0000 0 0 3 &mpic 2 1 306 0000 0x0 0x0 0x3 &mpic 0x2 0x1
306 0000 0 0 4 &mpic 3 1 307 0000 0x0 0x0 0x4 &mpic 0x3 0x1
307 308
308 /* IDSEL 0x04 (VIA chip) */ 309 /* IDSEL 0x04 (VIA chip) */
309 2000 0 0 1 &mpic 0 1 310 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
310 2000 0 0 2 &mpic 1 1 311 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
311 2000 0 0 3 &mpic 2 1 312 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
312 2000 0 0 4 &mpic 3 1 313 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
313 314
314 /* IDSEL 0x05 (8139) */ 315 /* IDSEL 0x05 (8139) */
315 2800 0 0 1 &mpic 1 1 316 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
316 317
317 /* IDSEL 0x06 (Slot 6) */ 318 /* IDSEL 0x06 (Slot 6) */
318 3000 0 0 1 &mpic 2 1 319 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
319 3000 0 0 2 &mpic 3 1 320 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
320 3000 0 0 3 &mpic 0 1 321 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
321 3000 0 0 4 &mpic 1 1 322 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
322 323
323 /* IDESL 0x07 (Slot 7) */ 324 /* IDESL 0x07 (Slot 7) */
324 3800 0 0 1 &mpic 3 1 325 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
325 3800 0 0 2 &mpic 0 1 326 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
326 3800 0 0 3 &mpic 1 1 327 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
327 3800 0 0 4 &mpic 2 1>; 328 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
328 329
329 reg = <e000 0 0 0 0>; 330 reg = <0xe000 0x0 0x0 0x0 0x0>;
330 #interrupt-cells = <1>; 331 #interrupt-cells = <1>;
331 #size-cells = <2>; 332 #size-cells = <2>;
332 #address-cells = <3>; 333 #address-cells = <3>;
333 ranges = <02000000 0 80000000 334 ranges = <0x2000000 0x0 0x80000000
334 02000000 0 80000000 335 0x2000000 0x0 0x80000000
335 0 20000000 336 0x0 0x20000000
336 01000000 0 00000000 337 0x1000000 0x0 0x0
337 01000000 0 00000000 338 0x1000000 0x0 0x0
338 0 00080000>; 339 0x0 0x80000>;
339 clock-frequency = <1fca055>; 340 clock-frequency = <33333333>;
340 341
341 isa@4 { 342 isa@4 {
342 device_type = "isa"; 343 device_type = "isa";
343 #interrupt-cells = <2>; 344 #interrupt-cells = <2>;
344 #size-cells = <1>; 345 #size-cells = <1>;
345 #address-cells = <2>; 346 #address-cells = <2>;
346 reg = <2000 0 0 0 0>; 347 reg = <0x2000 0x0 0x0 0x0 0x0>;
347 ranges = <1 0 01000000 0 0 00001000>; 348 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
348 interrupt-parent = <&i8259>; 349 interrupt-parent = <&i8259>;
349 350
350 i8259: interrupt-controller@20 { 351 i8259: interrupt-controller@20 {
351 interrupt-controller; 352 interrupt-controller;
352 device_type = "interrupt-controller"; 353 device_type = "interrupt-controller";
353 reg = <1 20 2 354 reg = <0x1 0x20 0x2
354 1 a0 2 355 0x1 0xa0 0x2
355 1 4d0 2>; 356 0x1 0x4d0 0x2>;
356 #address-cells = <0>; 357 #address-cells = <0>;
357 #interrupt-cells = <2>; 358 #interrupt-cells = <2>;
358 compatible = "chrp,iic"; 359 compatible = "chrp,iic";
@@ -362,7 +363,7 @@
362 363
363 rtc@70 { 364 rtc@70 {
364 compatible = "pnpPNP,b00"; 365 compatible = "pnpPNP,b00";
365 reg = <1 70 2>; 366 reg = <0x1 0x70 0x2>;
366 }; 367 };
367 }; 368 };
368 }; 369 };
@@ -370,64 +371,64 @@
370 371
371 pci1: pci@e0009000 { 372 pci1: pci@e0009000 {
372 cell-index = <1>; 373 cell-index = <1>;
373 interrupt-map-mask = <f800 0 0 7>; 374 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
374 interrupt-map = < 375 interrupt-map = <
375 376
376 /* IDSEL 0x15 */ 377 /* IDSEL 0x15 */
377 a800 0 0 1 &mpic b 1 378 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
378 a800 0 0 2 &mpic 1 1 379 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
379 a800 0 0 3 &mpic 2 1 380 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
380 a800 0 0 4 &mpic 3 1>; 381 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
381 382
382 interrupt-parent = <&mpic>; 383 interrupt-parent = <&mpic>;
383 interrupts = <19 2>; 384 interrupts = <25 2>;
384 bus-range = <0 0>; 385 bus-range = <0 0>;
385 ranges = <02000000 0 90000000 90000000 0 10000000 386 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
386 01000000 0 00000000 e2800000 0 00800000>; 387 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
387 clock-frequency = <3f940aa>; 388 clock-frequency = <66666666>;
388 #interrupt-cells = <1>; 389 #interrupt-cells = <1>;
389 #size-cells = <2>; 390 #size-cells = <2>;
390 #address-cells = <3>; 391 #address-cells = <3>;
391 reg = <e0009000 1000>; 392 reg = <0xe0009000 0x1000>;
392 compatible = "fsl,mpc8540-pci"; 393 compatible = "fsl,mpc8540-pci";
393 device_type = "pci"; 394 device_type = "pci";
394 }; 395 };
395 396
396 pci2: pcie@e000a000 { 397 pci2: pcie@e000a000 {
397 cell-index = <2>; 398 cell-index = <2>;
398 interrupt-map-mask = <f800 0 0 7>; 399 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
399 interrupt-map = < 400 interrupt-map = <
400 401
401 /* IDSEL 0x0 (PEX) */ 402 /* IDSEL 0x0 (PEX) */
402 00000 0 0 1 &mpic 0 1 403 00000 0x0 0x0 0x1 &mpic 0x0 0x1
403 00000 0 0 2 &mpic 1 1 404 00000 0x0 0x0 0x2 &mpic 0x1 0x1
404 00000 0 0 3 &mpic 2 1 405 00000 0x0 0x0 0x3 &mpic 0x2 0x1
405 00000 0 0 4 &mpic 3 1>; 406 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
406 407
407 interrupt-parent = <&mpic>; 408 interrupt-parent = <&mpic>;
408 interrupts = <1a 2>; 409 interrupts = <26 2>;
409 bus-range = <0 ff>; 410 bus-range = <0 255>;
410 ranges = <02000000 0 a0000000 a0000000 0 20000000 411 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
411 01000000 0 00000000 e3000000 0 08000000>; 412 0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>;
412 clock-frequency = <1fca055>; 413 clock-frequency = <33333333>;
413 #interrupt-cells = <1>; 414 #interrupt-cells = <1>;
414 #size-cells = <2>; 415 #size-cells = <2>;
415 #address-cells = <3>; 416 #address-cells = <3>;
416 reg = <e000a000 1000>; 417 reg = <0xe000a000 0x1000>;
417 compatible = "fsl,mpc8548-pcie"; 418 compatible = "fsl,mpc8548-pcie";
418 device_type = "pci"; 419 device_type = "pci";
419 pcie@0 { 420 pcie@0 {
420 reg = <0 0 0 0 0>; 421 reg = <0x0 0x0 0x0 0x0 0x0>;
421 #size-cells = <2>; 422 #size-cells = <2>;
422 #address-cells = <3>; 423 #address-cells = <3>;
423 device_type = "pci"; 424 device_type = "pci";
424 ranges = <02000000 0 a0000000 425 ranges = <0x2000000 0x0 0xa0000000
425 02000000 0 a0000000 426 0x2000000 0x0 0xa0000000
426 0 20000000 427 0x0 0x20000000
427 428
428 01000000 0 00000000 429 0x1000000 0x0 0x0
429 01000000 0 00000000 430 0x1000000 0x0 0x0
430 0 08000000>; 431 0x0 0x8000000>;
431 }; 432 };
432 }; 433 };
433}; 434};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 13:13:44 -0500