aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/boot/dts/haleakala.dts
diff options
context:
space:
mode:
Diffstat (limited to 'arch/powerpc/boot/dts/haleakala.dts')
-rw-r--r--arch/powerpc/boot/dts/haleakala.dts138
1 files changed, 70 insertions, 68 deletions
diff --git a/arch/powerpc/boot/dts/haleakala.dts b/arch/powerpc/boot/dts/haleakala.dts
index b5d95ac24db..513bc43a71a 100644
--- a/arch/powerpc/boot/dts/haleakala.dts
+++ b/arch/powerpc/boot/dts/haleakala.dts
@@ -8,12 +8,14 @@
8 * any warranty of any kind, whether express or implied. 8 * any warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11/dts-v1/;
12
11/ { 13/ {
12 #address-cells = <1>; 14 #address-cells = <1>;
13 #size-cells = <1>; 15 #size-cells = <1>;
14 model = "amcc,haleakala"; 16 model = "amcc,haleakala";
15 compatible = "amcc,haleakala", "amcc,kilauea"; 17 compatible = "amcc,haleakala", "amcc,kilauea";
16 dcr-parent = <&/cpus/cpu@0>; 18 dcr-parent = <&{/cpus/cpu@0}>;
17 19
18 aliases { 20 aliases {
19 ethernet0 = &EMAC0; 21 ethernet0 = &EMAC0;
@@ -28,13 +30,13 @@
28 cpu@0 { 30 cpu@0 {
29 device_type = "cpu"; 31 device_type = "cpu";
30 model = "PowerPC,405EXr"; 32 model = "PowerPC,405EXr";
31 reg = <0>; 33 reg = <0x00000000>;
32 clock-frequency = <0>; /* Filled in by U-Boot */ 34 clock-frequency = <0>; /* Filled in by U-Boot */
33 timebase-frequency = <0>; /* Filled in by U-Boot */ 35 timebase-frequency = <0>; /* Filled in by U-Boot */
34 i-cache-line-size = <20>; 36 i-cache-line-size = <32>;
35 d-cache-line-size = <20>; 37 d-cache-line-size = <32>;
36 i-cache-size = <4000>; /* 16 kB */ 38 i-cache-size = <16384>; /* 16 kB */
37 d-cache-size = <4000>; /* 16 kB */ 39 d-cache-size = <16384>; /* 16 kB */
38 dcr-controller; 40 dcr-controller;
39 dcr-access-method = "native"; 41 dcr-access-method = "native";
40 }; 42 };
@@ -42,14 +44,14 @@
42 44
43 memory { 45 memory {
44 device_type = "memory"; 46 device_type = "memory";
45 reg = <0 0>; /* Filled in by U-Boot */ 47 reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
46 }; 48 };
47 49
48 UIC0: interrupt-controller { 50 UIC0: interrupt-controller {
49 compatible = "ibm,uic-405exr", "ibm,uic"; 51 compatible = "ibm,uic-405exr", "ibm,uic";
50 interrupt-controller; 52 interrupt-controller;
51 cell-index = <0>; 53 cell-index = <0>;
52 dcr-reg = <0c0 009>; 54 dcr-reg = <0x0c0 0x009>;
53 #address-cells = <0>; 55 #address-cells = <0>;
54 #size-cells = <0>; 56 #size-cells = <0>;
55 #interrupt-cells = <2>; 57 #interrupt-cells = <2>;
@@ -59,11 +61,11 @@
59 compatible = "ibm,uic-405exr","ibm,uic"; 61 compatible = "ibm,uic-405exr","ibm,uic";
60 interrupt-controller; 62 interrupt-controller;
61 cell-index = <1>; 63 cell-index = <1>;
62 dcr-reg = <0d0 009>; 64 dcr-reg = <0x0d0 0x009>;
63 #address-cells = <0>; 65 #address-cells = <0>;
64 #size-cells = <0>; 66 #size-cells = <0>;
65 #interrupt-cells = <2>; 67 #interrupt-cells = <2>;
66 interrupts = <1e 4 1f 4>; /* cascade */ 68 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
67 interrupt-parent = <&UIC0>; 69 interrupt-parent = <&UIC0>;
68 }; 70 };
69 71
@@ -71,11 +73,11 @@
71 compatible = "ibm,uic-405exr","ibm,uic"; 73 compatible = "ibm,uic-405exr","ibm,uic";
72 interrupt-controller; 74 interrupt-controller;
73 cell-index = <2>; 75 cell-index = <2>;
74 dcr-reg = <0e0 009>; 76 dcr-reg = <0x0e0 0x009>;
75 #address-cells = <0>; 77 #address-cells = <0>;
76 #size-cells = <0>; 78 #size-cells = <0>;
77 #interrupt-cells = <2>; 79 #interrupt-cells = <2>;
78 interrupts = <1c 4 1d 4>; /* cascade */ 80 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
79 interrupt-parent = <&UIC0>; 81 interrupt-parent = <&UIC0>;
80 }; 82 };
81 83
@@ -88,72 +90,72 @@
88 90
89 SDRAM0: memory-controller { 91 SDRAM0: memory-controller {
90 compatible = "ibm,sdram-405exr"; 92 compatible = "ibm,sdram-405exr";
91 dcr-reg = <010 2>; 93 dcr-reg = <0x010 0x002>;
92 }; 94 };
93 95
94 MAL0: mcmal { 96 MAL0: mcmal {
95 compatible = "ibm,mcmal-405exr", "ibm,mcmal2"; 97 compatible = "ibm,mcmal-405exr", "ibm,mcmal2";
96 dcr-reg = <180 62>; 98 dcr-reg = <0x180 0x062>;
97 num-tx-chans = <2>; 99 num-tx-chans = <2>;
98 num-rx-chans = <2>; 100 num-rx-chans = <2>;
99 interrupt-parent = <&MAL0>; 101 interrupt-parent = <&MAL0>;
100 interrupts = <0 1 2 3 4>; 102 interrupts = <0x0 0x1 0x2 0x3 0x4>;
101 #interrupt-cells = <1>; 103 #interrupt-cells = <1>;
102 #address-cells = <0>; 104 #address-cells = <0>;
103 #size-cells = <0>; 105 #size-cells = <0>;
104 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 106 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
105 /*RXEOB*/ 1 &UIC0 b 4 107 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
106 /*SERR*/ 2 &UIC1 0 4 108 /*SERR*/ 0x2 &UIC1 0x0 0x4
107 /*TXDE*/ 3 &UIC1 1 4 109 /*TXDE*/ 0x3 &UIC1 0x1 0x4
108 /*RXDE*/ 4 &UIC1 2 4>; 110 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
109 interrupt-map-mask = <ffffffff>; 111 interrupt-map-mask = <0xffffffff>;
110 }; 112 };
111 113
112 POB0: opb { 114 POB0: opb {
113 compatible = "ibm,opb-405exr", "ibm,opb"; 115 compatible = "ibm,opb-405exr", "ibm,opb";
114 #address-cells = <1>; 116 #address-cells = <1>;
115 #size-cells = <1>; 117 #size-cells = <1>;
116 ranges = <80000000 80000000 10000000 118 ranges = <0x80000000 0x80000000 0x10000000
117 ef600000 ef600000 a00000 119 0xef600000 0xef600000 0x00a00000
118 f0000000 f0000000 10000000>; 120 0xf0000000 0xf0000000 0x10000000>;
119 dcr-reg = <0a0 5>; 121 dcr-reg = <0x0a0 0x005>;
120 clock-frequency = <0>; /* Filled in by U-Boot */ 122 clock-frequency = <0>; /* Filled in by U-Boot */
121 123
122 EBC0: ebc { 124 EBC0: ebc {
123 compatible = "ibm,ebc-405exr", "ibm,ebc"; 125 compatible = "ibm,ebc-405exr", "ibm,ebc";
124 dcr-reg = <012 2>; 126 dcr-reg = <0x012 0x002>;
125 #address-cells = <2>; 127 #address-cells = <2>;
126 #size-cells = <1>; 128 #size-cells = <1>;
127 clock-frequency = <0>; /* Filled in by U-Boot */ 129 clock-frequency = <0>; /* Filled in by U-Boot */
128 /* ranges property is supplied by U-Boot */ 130 /* ranges property is supplied by U-Boot */
129 interrupts = <5 1>; 131 interrupts = <0x5 0x1>;
130 interrupt-parent = <&UIC1>; 132 interrupt-parent = <&UIC1>;
131 133
132 nor_flash@0,0 { 134 nor_flash@0,0 {
133 compatible = "amd,s29gl512n", "cfi-flash"; 135 compatible = "amd,s29gl512n", "cfi-flash";
134 bank-width = <2>; 136 bank-width = <2>;
135 reg = <0 000000 4000000>; 137 reg = <0x00000000 0x00000000 0x04000000>;
136 #address-cells = <1>; 138 #address-cells = <1>;
137 #size-cells = <1>; 139 #size-cells = <1>;
138 partition@0 { 140 partition@0 {
139 label = "kernel"; 141 label = "kernel";
140 reg = <0 200000>; 142 reg = <0x00000000 0x00200000>;
141 }; 143 };
142 partition@200000 { 144 partition@200000 {
143 label = "root"; 145 label = "root";
144 reg = <200000 200000>; 146 reg = <0x00200000 0x00200000>;
145 }; 147 };
146 partition@400000 { 148 partition@400000 {
147 label = "user"; 149 label = "user";
148 reg = <400000 3b60000>; 150 reg = <0x00400000 0x03b60000>;
149 }; 151 };
150 partition@3f60000 { 152 partition@3f60000 {
151 label = "env"; 153 label = "env";
152 reg = <3f60000 40000>; 154 reg = <0x03f60000 0x00040000>;
153 }; 155 };
154 partition@3fa0000 { 156 partition@3fa0000 {
155 label = "u-boot"; 157 label = "u-boot";
156 reg = <3fa0000 60000>; 158 reg = <0x03fa0000 0x00060000>;
157 }; 159 };
158 }; 160 };
159 }; 161 };
@@ -161,68 +163,68 @@
161 UART0: serial@ef600200 { 163 UART0: serial@ef600200 {
162 device_type = "serial"; 164 device_type = "serial";
163 compatible = "ns16550"; 165 compatible = "ns16550";
164 reg = <ef600200 8>; 166 reg = <0xef600200 0x00000008>;
165 virtual-reg = <ef600200>; 167 virtual-reg = <0xef600200>;
166 clock-frequency = <0>; /* Filled in by U-Boot */ 168 clock-frequency = <0>; /* Filled in by U-Boot */
167 current-speed = <0>; 169 current-speed = <0>;
168 interrupt-parent = <&UIC0>; 170 interrupt-parent = <&UIC0>;
169 interrupts = <1a 4>; 171 interrupts = <0x1a 0x4>;
170 }; 172 };
171 173
172 UART1: serial@ef600300 { 174 UART1: serial@ef600300 {
173 device_type = "serial"; 175 device_type = "serial";
174 compatible = "ns16550"; 176 compatible = "ns16550";
175 reg = <ef600300 8>; 177 reg = <0xef600300 0x00000008>;
176 virtual-reg = <ef600300>; 178 virtual-reg = <0xef600300>;
177 clock-frequency = <0>; /* Filled in by U-Boot */ 179 clock-frequency = <0>; /* Filled in by U-Boot */
178 current-speed = <0>; 180 current-speed = <0>;
179 interrupt-parent = <&UIC0>; 181 interrupt-parent = <&UIC0>;
180 interrupts = <1 4>; 182 interrupts = <0x1 0x4>;
181 }; 183 };
182 184
183 IIC0: i2c@ef600400 { 185 IIC0: i2c@ef600400 {
184 compatible = "ibm,iic-405exr", "ibm,iic"; 186 compatible = "ibm,iic-405exr", "ibm,iic";
185 reg = <ef600400 14>; 187 reg = <0xef600400 0x00000014>;
186 interrupt-parent = <&UIC0>; 188 interrupt-parent = <&UIC0>;
187 interrupts = <2 4>; 189 interrupts = <0x2 0x4>;
188 }; 190 };
189 191
190 IIC1: i2c@ef600500 { 192 IIC1: i2c@ef600500 {
191 compatible = "ibm,iic-405exr", "ibm,iic"; 193 compatible = "ibm,iic-405exr", "ibm,iic";
192 reg = <ef600500 14>; 194 reg = <0xef600500 0x00000014>;
193 interrupt-parent = <&UIC0>; 195 interrupt-parent = <&UIC0>;
194 interrupts = <7 4>; 196 interrupts = <0x7 0x4>;
195 }; 197 };
196 198
197 199
198 RGMII0: emac-rgmii@ef600b00 { 200 RGMII0: emac-rgmii@ef600b00 {
199 compatible = "ibm,rgmii-405exr", "ibm,rgmii"; 201 compatible = "ibm,rgmii-405exr", "ibm,rgmii";
200 reg = <ef600b00 104>; 202 reg = <0xef600b00 0x00000104>;
201 has-mdio; 203 has-mdio;
202 }; 204 };
203 205
204 EMAC0: ethernet@ef600900 { 206 EMAC0: ethernet@ef600900 {
205 linux,network-index = <0>; 207 linux,network-index = <0x0>;
206 device_type = "network"; 208 device_type = "network";
207 compatible = "ibm,emac-405exr", "ibm,emac4"; 209 compatible = "ibm,emac-405exr", "ibm,emac4sync";
208 interrupt-parent = <&EMAC0>; 210 interrupt-parent = <&EMAC0>;
209 interrupts = <0 1>; 211 interrupts = <0x0 0x1>;
210 #interrupt-cells = <1>; 212 #interrupt-cells = <1>;
211 #address-cells = <0>; 213 #address-cells = <0>;
212 #size-cells = <0>; 214 #size-cells = <0>;
213 interrupt-map = </*Status*/ 0 &UIC0 18 4 215 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
214 /*Wake*/ 1 &UIC1 1d 4>; 216 /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
215 reg = <ef600900 70>; 217 reg = <0xef600900 0x000000c4>;
216 local-mac-address = [000000000000]; /* Filled in by U-Boot */ 218 local-mac-address = [000000000000]; /* Filled in by U-Boot */
217 mal-device = <&MAL0>; 219 mal-device = <&MAL0>;
218 mal-tx-channel = <0>; 220 mal-tx-channel = <0>;
219 mal-rx-channel = <0>; 221 mal-rx-channel = <0>;
220 cell-index = <0>; 222 cell-index = <0>;
221 max-frame-size = <2328>; 223 max-frame-size = <9000>;
222 rx-fifo-size = <1000>; 224 rx-fifo-size = <4096>;
223 tx-fifo-size = <800>; 225 tx-fifo-size = <2048>;
224 phy-mode = "rgmii"; 226 phy-mode = "rgmii";
225 phy-map = <00000000>; 227 phy-map = <0x00000000>;
226 rgmii-device = <&RGMII0>; 228 rgmii-device = <&RGMII0>;
227 rgmii-channel = <0>; 229 rgmii-channel = <0>;
228 has-inverted-stacr-oc; 230 has-inverted-stacr-oc;
@@ -237,23 +239,23 @@
237 #address-cells = <3>; 239 #address-cells = <3>;
238 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 240 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
239 primary; 241 primary;
240 port = <0>; /* port number */ 242 port = <0x0>; /* port number */
241 reg = <a0000000 20000000 /* Config space access */ 243 reg = <0xa0000000 0x20000000 /* Config space access */
242 ef000000 00001000>; /* Registers */ 244 0xef000000 0x00001000>; /* Registers */
243 dcr-reg = <040 020>; 245 dcr-reg = <0x040 0x020>;
244 sdr-base = <400>; 246 sdr-base = <0x400>;
245 247
246 /* Outbound ranges, one memory and one IO, 248 /* Outbound ranges, one memory and one IO,
247 * later cannot be changed 249 * later cannot be changed
248 */ 250 */
249 ranges = <02000000 0 80000000 90000000 0 08000000 251 ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
250 01000000 0 00000000 e0000000 0 00010000>; 252 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
251 253
252 /* Inbound 2GB range starting at 0 */ 254 /* Inbound 2GB range starting at 0 */
253 dma-ranges = <42000000 0 0 0 0 80000000>; 255 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
254 256
255 /* This drives busses 0x00 to 0x3f */ 257 /* This drives busses 0x00 to 0x3f */
256 bus-range = <00 3f>; 258 bus-range = <0x0 0x3f>;
257 259
258 /* Legacy interrupts (note the weird polarity, the bridge seems 260 /* Legacy interrupts (note the weird polarity, the bridge seems
259 * to invert PCIe legacy interrupts). 261 * to invert PCIe legacy interrupts).
@@ -263,12 +265,12 @@
263 * below are basically de-swizzled numbers. 265 * below are basically de-swizzled numbers.
264 * The real slot is on idsel 0, so the swizzling is 1:1 266 * The real slot is on idsel 0, so the swizzling is 1:1
265 */ 267 */
266 interrupt-map-mask = <0000 0 0 7>; 268 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
267 interrupt-map = < 269 interrupt-map = <
268 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ 270 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
269 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ 271 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
270 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ 272 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
271 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; 273 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
272 }; 274 };
273 }; 275 };
274}; 276};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 15:02:17 -0500