diff options
Diffstat (limited to 'arch/mips/loongson/common/cs5536/cs5536_ide.c')
-rw-r--r-- | arch/mips/loongson/common/cs5536/cs5536_ide.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ide.c b/arch/mips/loongson/common/cs5536/cs5536_ide.c index 9a96b5664c7..681d1291a2c 100644 --- a/arch/mips/loongson/common/cs5536/cs5536_ide.c +++ b/arch/mips/loongson/common/cs5536/cs5536_ide.c | |||
@@ -51,6 +51,7 @@ void pci_ide_write_reg(int reg, u32 value) | |||
51 | lo |= SOFT_BAR_IDE_FLAG; | 51 | lo |= SOFT_BAR_IDE_FLAG; |
52 | _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); | 52 | _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); |
53 | } else if (value & 0x01) { | 53 | } else if (value & 0x01) { |
54 | _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); | ||
54 | lo = (value & 0xfffffff0) | 0x1; | 55 | lo = (value & 0xfffffff0) | 0x1; |
55 | _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo); | 56 | _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo); |
56 | 57 | ||
@@ -65,19 +66,30 @@ void pci_ide_write_reg(int reg, u32 value) | |||
65 | _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo); | 66 | _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo); |
66 | lo |= 0x01; | 67 | lo |= 0x01; |
67 | _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo); | 68 | _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo); |
68 | } else | 69 | } else { |
70 | _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo); | ||
71 | lo = value; | ||
69 | _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo); | 72 | _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo); |
73 | } | ||
70 | break; | 74 | break; |
71 | case PCI_IDE_DTC_REG: | 75 | case PCI_IDE_DTC_REG: |
76 | _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo); | ||
77 | lo = value; | ||
72 | _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo); | 78 | _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo); |
73 | break; | 79 | break; |
74 | case PCI_IDE_CAST_REG: | 80 | case PCI_IDE_CAST_REG: |
81 | _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo); | ||
82 | lo = value; | ||
75 | _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo); | 83 | _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo); |
76 | break; | 84 | break; |
77 | case PCI_IDE_ETC_REG: | 85 | case PCI_IDE_ETC_REG: |
86 | _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo); | ||
87 | lo = value; | ||
78 | _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo); | 88 | _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo); |
79 | break; | 89 | break; |
80 | case PCI_IDE_PM_REG: | 90 | case PCI_IDE_PM_REG: |
91 | _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo); | ||
92 | lo = value; | ||
81 | _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo); | 93 | _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo); |
82 | break; | 94 | break; |
83 | default: | 95 | default: |
@@ -167,6 +179,7 @@ u32 pci_ide_read_reg(int reg) | |||
167 | case PCI_IDE_ETC_REG: | 179 | case PCI_IDE_ETC_REG: |
168 | _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo); | 180 | _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo); |
169 | conf_data = lo; | 181 | conf_data = lo; |
182 | break; | ||
170 | case PCI_IDE_PM_REG: | 183 | case PCI_IDE_PM_REG: |
171 | _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo); | 184 | _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo); |
172 | conf_data = lo; | 185 | conf_data = lo; |