1 files changed, 3 insertions, 10 deletions

diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 4cf0c06e241..8b7e0c17ac3 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -151,7 +151,7 @@ static void dec_timer_ack(void)
         CMOS_READ(RTC_REG_C);                   /* Ack the RTC interrupt.  */
 }
 
-static unsigned int dec_ioasic_hpt_read(void)
+static cycle_t dec_ioasic_hpt_read(void)
 {
         /*
          * The free-running counter is 32-bit which is good for about
@@ -160,11 +160,6 @@ static unsigned int dec_ioasic_hpt_read(void)
         return ioasic_read(IO_REG_FCTR);
 }
 
-static void dec_ioasic_hpt_init(unsigned int count)
-{
-        ioasic_write(IO_REG_FCTR, ioasic_read(IO_REG_FCTR) - count);
-}
-
 
 void __init dec_time_init(void)
 {
@@ -174,11 +169,9 @@ void __init dec_time_init(void)
         mips_timer_state = dec_timer_state;
         mips_timer_ack = dec_timer_ack;
 
-        if (!cpu_has_counter && IOASIC) {
+        if (!cpu_has_counter && IOASIC)
                 /* For pre-R4k systems we use the I/O ASIC's counter.  */
-                mips_hpt_read = dec_ioasic_hpt_read;
-                mips_hpt_init = dec_ioasic_hpt_init;
-        }
+                clocksource_mips.read = dec_ioasic_hpt_read;
 
         /* Set up the rate of periodic DS1287 interrupts.  */
         CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);