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Diffstat (limited to 'arch/mips/dec/kn02-irq.c')
-rw-r--r--arch/mips/dec/kn02-irq.c53
1 files changed, 7 insertions, 46 deletions
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index 04a367a60a5..5a9be4c9358 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -14,7 +14,6 @@
14 14
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/spinlock.h>
18#include <linux/types.h> 17#include <linux/types.h>
19 18
20#include <asm/dec/kn02.h> 19#include <asm/dec/kn02.h>
@@ -29,7 +28,6 @@
29 * There is no default value -- it has to be initialized. 28 * There is no default value -- it has to be initialized.
30 */ 29 */
31u32 cached_kn02_csr; 30u32 cached_kn02_csr;
32DEFINE_SPINLOCK(kn02_lock);
33 31
34 32
35static int kn02_irq_base; 33static int kn02_irq_base;
@@ -53,54 +51,24 @@ static inline void mask_kn02_irq(unsigned int irq)
53 *csr = cached_kn02_csr; 51 *csr = cached_kn02_csr;
54} 52}
55 53
56static inline void enable_kn02_irq(unsigned int irq)
57{
58 unsigned long flags;
59
60 spin_lock_irqsave(&kn02_lock, flags);
61 unmask_kn02_irq(irq);
62 spin_unlock_irqrestore(&kn02_lock, flags);
63}
64
65static inline void disable_kn02_irq(unsigned int irq)
66{
67 unsigned long flags;
68
69 spin_lock_irqsave(&kn02_lock, flags);
70 mask_kn02_irq(irq);
71 spin_unlock_irqrestore(&kn02_lock, flags);
72}
73
74
75static unsigned int startup_kn02_irq(unsigned int irq)
76{
77 enable_kn02_irq(irq);
78 return 0;
79}
80
81#define shutdown_kn02_irq disable_kn02_irq
82
83static void ack_kn02_irq(unsigned int irq) 54static void ack_kn02_irq(unsigned int irq)
84{ 55{
85 spin_lock(&kn02_lock);
86 mask_kn02_irq(irq); 56 mask_kn02_irq(irq);
87 spin_unlock(&kn02_lock);
88 iob(); 57 iob();
89} 58}
90 59
91static void end_kn02_irq(unsigned int irq) 60static void end_kn02_irq(unsigned int irq)
92{ 61{
93 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 62 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
94 enable_kn02_irq(irq); 63 unmask_kn02_irq(irq);
95} 64}
96 65
97static struct irq_chip kn02_irq_type = { 66static struct irq_chip kn02_irq_type = {
98 .typename = "KN02-CSR", 67 .typename = "KN02-CSR",
99 .startup = startup_kn02_irq,
100 .shutdown = shutdown_kn02_irq,
101 .enable = enable_kn02_irq,
102 .disable = disable_kn02_irq,
103 .ack = ack_kn02_irq, 68 .ack = ack_kn02_irq,
69 .mask = mask_kn02_irq,
70 .mask_ack = ack_kn02_irq,
71 .unmask = unmask_kn02_irq,
104 .end = end_kn02_irq, 72 .end = end_kn02_irq,
105}; 73};
106 74
@@ -109,22 +77,15 @@ void __init init_kn02_irqs(int base)
109{ 77{
110 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 78 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
111 KN02_CSR); 79 KN02_CSR);
112 unsigned long flags;
113 int i; 80 int i;
114 81
115 /* Mask interrupts. */ 82 /* Mask interrupts. */
116 spin_lock_irqsave(&kn02_lock, flags);
117 cached_kn02_csr &= ~KN02_CSR_IOINTEN; 83 cached_kn02_csr &= ~KN02_CSR_IOINTEN;
118 *csr = cached_kn02_csr; 84 *csr = cached_kn02_csr;
119 iob(); 85 iob();
120 spin_unlock_irqrestore(&kn02_lock, flags); 86
121 87 for (i = base; i < base + KN02_IRQ_LINES; i++)
122 for (i = base; i < base + KN02_IRQ_LINES; i++) { 88 set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
123 irq_desc[i].status = IRQ_DISABLED;
124 irq_desc[i].action = 0;
125 irq_desc[i].depth = 1;
126 irq_desc[i].chip = &kn02_irq_type;
127 }
128 89
129 kn02_irq_base = base; 90 kn02_irq_base = base;
130} 91}