diff options
Diffstat (limited to 'arch/microblaze/include/asm/cacheflush.h')
-rw-r--r-- | arch/microblaze/include/asm/cacheflush.h | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/arch/microblaze/include/asm/cacheflush.h b/arch/microblaze/include/asm/cacheflush.h index a6edd356cd0..7ebd955460d 100644 --- a/arch/microblaze/include/asm/cacheflush.h +++ b/arch/microblaze/include/asm/cacheflush.h | |||
@@ -17,6 +17,7 @@ | |||
17 | 17 | ||
18 | /* Somebody depends on this; sigh... */ | 18 | /* Somebody depends on this; sigh... */ |
19 | #include <linux/mm.h> | 19 | #include <linux/mm.h> |
20 | #include <linux/io.h> | ||
20 | 21 | ||
21 | /* Look at Documentation/cachetlb.txt */ | 22 | /* Look at Documentation/cachetlb.txt */ |
22 | 23 | ||
@@ -60,7 +61,6 @@ void microblaze_cache_init(void); | |||
60 | #define invalidate_icache() mbc->iin(); | 61 | #define invalidate_icache() mbc->iin(); |
61 | #define invalidate_icache_range(start, end) mbc->iinr(start, end); | 62 | #define invalidate_icache_range(start, end) mbc->iinr(start, end); |
62 | 63 | ||
63 | |||
64 | #define flush_icache_user_range(vma, pg, adr, len) flush_icache(); | 64 | #define flush_icache_user_range(vma, pg, adr, len) flush_icache(); |
65 | #define flush_icache_page(vma, pg) do { } while (0) | 65 | #define flush_icache_page(vma, pg) do { } while (0) |
66 | 66 | ||
@@ -72,9 +72,15 @@ void microblaze_cache_init(void); | |||
72 | #define flush_dcache() mbc->dfl(); | 72 | #define flush_dcache() mbc->dfl(); |
73 | #define flush_dcache_range(start, end) mbc->dflr(start, end); | 73 | #define flush_dcache_range(start, end) mbc->dflr(start, end); |
74 | 74 | ||
75 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 | 75 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 |
76 | /* D-cache aliasing problem can't happen - cache is between MMU and ram */ | 76 | /* MS: We have to implement it because of rootfs-jffs2 issue on WB */ |
77 | #define flush_dcache_page(page) do { } while (0) | 77 | #define flush_dcache_page(page) \ |
78 | do { \ | ||
79 | unsigned long addr = (unsigned long) page_address(page); /* virtual */ \ | ||
80 | addr = (u32)virt_to_phys((void *)addr); \ | ||
81 | flush_dcache_range((unsigned) (addr), (unsigned) (addr) + PAGE_SIZE); \ | ||
82 | } while (0); | ||
83 | |||
78 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | 84 | #define flush_dcache_mmap_lock(mapping) do { } while (0) |
79 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | 85 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) |
80 | 86 | ||
@@ -97,8 +103,10 @@ void microblaze_cache_init(void); | |||
97 | 103 | ||
98 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ | 104 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ |
99 | do { \ | 105 | do { \ |
106 | u32 addr = virt_to_phys(dst); \ | ||
107 | invalidate_icache_range((unsigned) (addr), (unsigned) (addr) + (len));\ | ||
100 | memcpy((dst), (src), (len)); \ | 108 | memcpy((dst), (src), (len)); \ |
101 | flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ | 109 | flush_dcache_range((unsigned) (addr), (unsigned) (addr) + (len));\ |
102 | } while (0) | 110 | } while (0) |
103 | 111 | ||
104 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ | 112 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ |