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Diffstat (limited to 'arch/m32r/platforms/mappi2/setup.c')
-rw-r--r--arch/m32r/platforms/mappi2/setup.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c
index 9117c30ea36..f3ed6b60a5f 100644
--- a/arch/m32r/platforms/mappi2/setup.c
+++ b/arch/m32r/platforms/mappi2/setup.c
@@ -76,38 +76,38 @@ void __init init_IRQ(void)
76{ 76{
77#if defined(CONFIG_SMC91X) 77#if defined(CONFIG_SMC91X)
78 /* INT0 : LAN controller (SMC91111) */ 78 /* INT0 : LAN controller (SMC91111) */
79 set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type, 79 irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
80 handle_level_irq); 80 handle_level_irq);
81 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 81 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
82 disable_mappi2_irq(M32R_IRQ_INT0); 82 disable_mappi2_irq(M32R_IRQ_INT0);
83#endif /* CONFIG_SMC91X */ 83#endif /* CONFIG_SMC91X */
84 84
85 /* MFT2 : system timer */ 85 /* MFT2 : system timer */
86 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type, 86 irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
87 handle_level_irq); 87 handle_level_irq);
88 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 88 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
89 disable_mappi2_irq(M32R_IRQ_MFT2); 89 disable_mappi2_irq(M32R_IRQ_MFT2);
90 90
91#ifdef CONFIG_SERIAL_M32R_SIO 91#ifdef CONFIG_SERIAL_M32R_SIO
92 /* SIO0_R : uart receive data */ 92 /* SIO0_R : uart receive data */
93 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type, 93 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
94 handle_level_irq); 94 handle_level_irq);
95 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 95 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
96 disable_mappi2_irq(M32R_IRQ_SIO0_R); 96 disable_mappi2_irq(M32R_IRQ_SIO0_R);
97 97
98 /* SIO0_S : uart send data */ 98 /* SIO0_S : uart send data */
99 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type, 99 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
100 handle_level_irq); 100 handle_level_irq);
101 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 101 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
102 disable_mappi2_irq(M32R_IRQ_SIO0_S); 102 disable_mappi2_irq(M32R_IRQ_SIO0_S);
103 /* SIO1_R : uart receive data */ 103 /* SIO1_R : uart receive data */
104 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type, 104 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
105 handle_level_irq); 105 handle_level_irq);
106 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 106 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
107 disable_mappi2_irq(M32R_IRQ_SIO1_R); 107 disable_mappi2_irq(M32R_IRQ_SIO1_R);
108 108
109 /* SIO1_S : uart send data */ 109 /* SIO1_S : uart send data */
110 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type, 110 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
111 handle_level_irq); 111 handle_level_irq);
112 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 112 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
113 disable_mappi2_irq(M32R_IRQ_SIO1_S); 113 disable_mappi2_irq(M32R_IRQ_SIO1_S);
@@ -115,27 +115,27 @@ void __init init_IRQ(void)
115 115
116#if defined(CONFIG_USB) 116#if defined(CONFIG_USB)
117 /* INT1 : USB Host controller interrupt */ 117 /* INT1 : USB Host controller interrupt */
118 set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type, 118 irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
119 handle_level_irq); 119 handle_level_irq);
120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
121 disable_mappi2_irq(M32R_IRQ_INT1); 121 disable_mappi2_irq(M32R_IRQ_INT1);
122#endif /* CONFIG_USB */ 122#endif /* CONFIG_USB */
123 123
124 /* ICUCR40: CFC IREQ */ 124 /* ICUCR40: CFC IREQ */
125 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type, 125 irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
126 handle_level_irq); 126 handle_level_irq);
127 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 127 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
128 disable_mappi2_irq(PLD_IRQ_CFIREQ); 128 disable_mappi2_irq(PLD_IRQ_CFIREQ);
129 129
130#if defined(CONFIG_M32R_CFC) 130#if defined(CONFIG_M32R_CFC)
131 /* ICUCR41: CFC Insert */ 131 /* ICUCR41: CFC Insert */
132 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type, 132 irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
133 handle_level_irq); 133 handle_level_irq);
134 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 134 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
135 disable_mappi2_irq(PLD_IRQ_CFC_INSERT); 135 disable_mappi2_irq(PLD_IRQ_CFC_INSERT);
136 136
137 /* ICUCR42: CFC Eject */ 137 /* ICUCR42: CFC Eject */
138 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type, 138 irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
139 handle_level_irq); 139 handle_level_irq);
140 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 140 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
141 disable_mappi2_irq(PLD_IRQ_CFC_EJECT); 141 disable_mappi2_irq(PLD_IRQ_CFC_EJECT);