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-rw-r--r--arch/blackfin/mach-common/cache.S36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index 3c98dacbf28..11875128743 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -97,3 +97,39 @@ ENTRY(_blackfin_dflush_page)
97 P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT); 97 P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
98 jump .Ldfr; 98 jump .Ldfr;
99ENDPROC(_blackfin_dflush_page) 99ENDPROC(_blackfin_dflush_page)
100
101/* Invalidate the Entire Data cache by
102 * clearing DMC[1:0] bits
103 */
104ENTRY(_blackfin_invalidate_entire_dcache)
105 [--SP] = ( R7:5);
106
107 P0.L = LO(DMEM_CONTROL);
108 P0.H = HI(DMEM_CONTROL);
109 R7 = [P0];
110 R5 = R7; /* Save DMEM_CNTR */
111
112 /* Clear the DMC[1:0] bits, All valid bits in the data
113 * cache are set to the invalid state
114 */
115 BITCLR(R7,DMC0_P);
116 BITCLR(R7,DMC1_P);
117 CLI R6;
118 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
119 .align 8;
120 [P0] = R7;
121 SSYNC;
122 STI R6;
123
124 /* Configures the data cache again */
125
126 CLI R6;
127 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
128 .align 8;
129 [P0] = R5;
130 SSYNC;
131 STI R6;
132
133 ( R7:5) = [SP++];
134 RTS;
135ENDPROC(_blackfin_invalidate_entire_dcache)