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Diffstat (limited to 'arch/blackfin/mach-bf527/include/mach/blackfin.h')
-rw-r--r--arch/blackfin/mach-bf527/include/mach/blackfin.h10
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
index 03665a8e16b..ea9cb0fef8b 100644
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h
@@ -56,11 +56,6 @@
56#endif 56#endif
57#endif 57#endif
58 58
59/* UART_IIR Register */
60#define STATUS(x) ((x << 1) & 0x06)
61#define STATUS_P1 0x02
62#define STATUS_P0 0x01
63
64#define BFIN_UART_NR_PORTS 2 59#define BFIN_UART_NR_PORTS 2
65 60
66#define OFFSET_THR 0x00 /* Transmit Holding register */ 61#define OFFSET_THR 0x00 /* Transmit Holding register */
@@ -76,11 +71,6 @@
76#define OFFSET_SCR 0x1C /* SCR Scratch Register */ 71#define OFFSET_SCR 0x1C /* SCR Scratch Register */
77#define OFFSET_GCTL 0x24 /* Global Control Register */ 72#define OFFSET_GCTL 0x24 /* Global Control Register */
78 73
79/* DPMC*/
80#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
81#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
82#define STOPCK_OFF STOPCK
83
84/* PLL_DIV Masks */ 74/* PLL_DIV Masks */
85#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ 75#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
86#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ 76#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */