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-rw-r--r--arch/arm/plat-s5pc1xx/Kconfig3
-rw-r--r--arch/arm/plat-s5pc1xx/clock.c31
-rw-r--r--arch/arm/plat-s5pc1xx/dev-uart.c29
-rw-r--r--arch/arm/plat-s5pc1xx/gpio-config.c2
-rw-r--r--arch/arm/plat-s5pc1xx/gpiolib.c2
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/irqs.h19
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/regs-clock.h119
-rw-r--r--arch/arm/plat-s5pc1xx/irq.c202
-rw-r--r--arch/arm/plat-s5pc1xx/s5pc100-clock.c770
9 files changed, 290 insertions, 887 deletions
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index b7b9e91c024..c7ccdf22eef 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -11,6 +11,9 @@ config PLAT_S5PC1XX
11 select ARM_VIC 11 select ARM_VIC
12 select NO_IOPORT 12 select NO_IOPORT
13 select ARCH_REQUIRE_GPIOLIB 13 select ARCH_REQUIRE_GPIOLIB
14 select SAMSUNG_CLKSRC
15 select SAMSUNG_IRQ_UART
16 select SAMSUNG_IRQ_VIC_TIMER
14 select S3C_GPIO_TRACK 17 select S3C_GPIO_TRACK
15 select S3C_GPIO_PULL_UPDOWN 18 select S3C_GPIO_PULL_UPDOWN
16 select S3C_GPIO_CFG_S3C24XX 19 select S3C_GPIO_CFG_S3C24XX
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
index 26c21d84979..387f23190c3 100644
--- a/arch/arm/plat-s5pc1xx/clock.c
+++ b/arch/arm/plat-s5pc1xx/clock.c
@@ -64,25 +64,13 @@ struct clk clk_54m = {
64 .rate = 54000000, 64 .rate = 54000000,
65}; 65};
66 66
67static int clk_default_setrate(struct clk *clk, unsigned long rate)
68{
69 clk->rate = rate;
70 return 0;
71}
72
73static int clk_dummy_enable(struct clk *clk, int enable)
74{
75 return 0;
76}
77
78struct clk clk_hd0 = { 67struct clk clk_hd0 = {
79 .name = "hclkd0", 68 .name = "hclkd0",
80 .id = -1, 69 .id = -1,
81 .rate = 0, 70 .rate = 0,
82 .parent = NULL, 71 .parent = NULL,
83 .ctrlbit = 0, 72 .ctrlbit = 0,
84 .set_rate = clk_default_setrate, 73 .ops = &clk_ops_def_setrate,
85 .enable = clk_dummy_enable,
86}; 74};
87 75
88struct clk clk_pd0 = { 76struct clk clk_pd0 = {
@@ -91,8 +79,7 @@ struct clk clk_pd0 = {
91 .rate = 0, 79 .rate = 0,
92 .parent = NULL, 80 .parent = NULL,
93 .ctrlbit = 0, 81 .ctrlbit = 0,
94 .set_rate = clk_default_setrate, 82 .ops = &clk_ops_def_setrate,
95 .enable = clk_dummy_enable,
96}; 83};
97 84
98static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable) 85static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
@@ -686,6 +673,8 @@ static struct clk s5pc100_init_clocks[] = {
686static struct clk *clks[] __initdata = { 673static struct clk *clks[] __initdata = {
687 &clk_ext, 674 &clk_ext,
688 &clk_epll, 675 &clk_epll,
676 &clk_pd0,
677 &clk_hd0,
689 &clk_27m, 678 &clk_27m,
690 &clk_48m, 679 &clk_48m,
691 &clk_54m, 680 &clk_54m,
@@ -700,16 +689,8 @@ void __init s5pc1xx_register_clocks(void)
700 689
701 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); 690 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
702 691
703 clkp = s5pc100_init_clocks; 692 s3c_register_clocks(s5pc100_init_clocks,
704 size = ARRAY_SIZE(s5pc100_init_clocks); 693 ARRAY_SIZE(s5pc100_init_clocks));
705
706 for (ptr = 0; ptr < size; ptr++, clkp++) {
707 ret = s3c24xx_register_clock(clkp);
708 if (ret < 0) {
709 printk(KERN_ERR "Failed to register clock %s (%d)\n",
710 clkp->name, ret);
711 }
712 }
713 694
714 clkp = s5pc100_init_clocks_disable; 695 clkp = s5pc100_init_clocks_disable;
715 size = ARRAY_SIZE(s5pc100_init_clocks_disable); 696 size = ARRAY_SIZE(s5pc100_init_clocks_disable);
diff --git a/arch/arm/plat-s5pc1xx/dev-uart.c b/arch/arm/plat-s5pc1xx/dev-uart.c
index f749bc5407b..586c95c60bf 100644
--- a/arch/arm/plat-s5pc1xx/dev-uart.c
+++ b/arch/arm/plat-s5pc1xx/dev-uart.c
@@ -143,32 +143,3 @@ struct s3c24xx_uart_resources s5pc1xx_uart_resources[] __initdata = {
143 .nr_resources = ARRAY_SIZE(s5pc1xx_uart3_resource), 143 .nr_resources = ARRAY_SIZE(s5pc1xx_uart3_resource),
144 }, 144 },
145}; 145};
146
147/* uart devices */
148
149static struct platform_device s3c24xx_uart_device0 = {
150 .id = 0,
151};
152
153static struct platform_device s3c24xx_uart_device1 = {
154 .id = 1,
155};
156
157static struct platform_device s3c24xx_uart_device2 = {
158 .id = 2,
159};
160
161static struct platform_device s3c24xx_uart_device3 = {
162 .id = 3,
163};
164
165struct platform_device *s3c24xx_uart_src[4] = {
166 &s3c24xx_uart_device0,
167 &s3c24xx_uart_device1,
168 &s3c24xx_uart_device2,
169 &s3c24xx_uart_device3,
170};
171
172struct platform_device *s3c24xx_uart_devs[4] = {
173};
174
diff --git a/arch/arm/plat-s5pc1xx/gpio-config.c b/arch/arm/plat-s5pc1xx/gpio-config.c
index bba675df9c7..a4f67e80a15 100644
--- a/arch/arm/plat-s5pc1xx/gpio-config.c
+++ b/arch/arm/plat-s5pc1xx/gpio-config.c
@@ -16,7 +16,7 @@
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/io.h> 17#include <linux/io.h>
18 18
19#include <mach/gpio-core.h> 19#include <plat/gpio-core.h>
20#include <plat/gpio-cfg-s5pc1xx.h> 20#include <plat/gpio-cfg-s5pc1xx.h>
21 21
22s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off) 22s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off)
diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c
index facb410e7a7..1ffc57ac293 100644
--- a/arch/arm/plat-s5pc1xx/gpiolib.c
+++ b/arch/arm/plat-s5pc1xx/gpiolib.c
@@ -17,8 +17,8 @@
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18 18
19#include <mach/map.h> 19#include <mach/map.h>
20#include <mach/gpio-core.h>
21 20
21#include <plat/gpio-core.h>
22#include <plat/gpio-cfg.h> 22#include <plat/gpio-cfg.h>
23#include <plat/gpio-cfg-helpers.h> 23#include <plat/gpio-cfg-helpers.h>
24#include <plat/regs-gpio.h> 24#include <plat/regs-gpio.h>
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
index ef8736366f0..409c804315e 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
@@ -88,11 +88,11 @@
88#define IRQ_MDMA S5PC1XX_IRQ_VIC0(18) 88#define IRQ_MDMA S5PC1XX_IRQ_VIC0(18)
89#define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19) 89#define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19)
90#define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20) 90#define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20)
91#define IRQ_TIMER0 S5PC1XX_IRQ_VIC0(21) 91#define IRQ_TIMER0_VIC S5PC1XX_IRQ_VIC0(21)
92#define IRQ_TIMER1 S5PC1XX_IRQ_VIC0(22) 92#define IRQ_TIMER1_VIC S5PC1XX_IRQ_VIC0(22)
93#define IRQ_TIMER2 S5PC1XX_IRQ_VIC0(23) 93#define IRQ_TIMER2_VIC S5PC1XX_IRQ_VIC0(23)
94#define IRQ_TIMER3 S5PC1XX_IRQ_VIC0(24) 94#define IRQ_TIMER3_VIC S5PC1XX_IRQ_VIC0(24)
95#define IRQ_TIMER4 S5PC1XX_IRQ_VIC0(25) 95#define IRQ_TIMER4_VIC S5PC1XX_IRQ_VIC0(25)
96#define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26) 96#define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26)
97#define IRQ_WDT S5PC1XX_IRQ_VIC0(27) 97#define IRQ_WDT S5PC1XX_IRQ_VIC0(27)
98#define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28) 98#define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28)
@@ -171,8 +171,15 @@
171#define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) 171#define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30)
172#define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) 172#define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31)
173 173
174#define IRQ_TIMER(x) (IRQ_SDMFIQ + 1 + (x))
175#define IRQ_TIMER0 IRQ_TIMER(0)
176#define IRQ_TIMER1 IRQ_TIMER(1)
177#define IRQ_TIMER2 IRQ_TIMER(2)
178#define IRQ_TIMER3 IRQ_TIMER(3)
179#define IRQ_TIMER4 IRQ_TIMER(4)
180
174/* External interrupt */ 181/* External interrupt */
175#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1) 182#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 6)
176 183
177#define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16)) 184#define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16))
178#define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x)) 185#define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x))
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
index c5cc86e92d6..24dec4e5253 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
@@ -61,73 +61,10 @@
61#define S5PC100_EPLL_MASK 0xffffffff 61#define S5PC100_EPLL_MASK 0xffffffff
62#define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) 62#define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
63 63
64/* CLKSRC0 */ 64/* CLKSRC0..CLKSRC3 -> mostly removed due to clksrc updates */
65#define S5PC100_CLKSRC0_APLL_MASK (0x1<<0) 65#define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24)
66#define S5PC100_CLKSRC0_APLL_SHIFT (0)
67#define S5PC100_CLKSRC0_MPLL_MASK (0x1<<4)
68#define S5PC100_CLKSRC0_MPLL_SHIFT (4)
69#define S5PC100_CLKSRC0_EPLL_MASK (0x1<<8)
70#define S5PC100_CLKSRC0_EPLL_SHIFT (8)
71#define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12)
72#define S5PC100_CLKSRC0_HPLL_SHIFT (12)
73#define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16)
74#define S5PC100_CLKSRC0_AMMUX_SHIFT (16)
75#define S5PC100_CLKSRC0_HREF_MASK (0x1<<20)
76#define S5PC100_CLKSRC0_HREF_SHIFT (20)
77#define S5PC100_CLKSRC0_ONENAND_MASK (0x1<<24)
78#define S5PC100_CLKSRC0_ONENAND_SHIFT (24)
79
80
81/* CLKSRC1 */
82#define S5PC100_CLKSRC1_UART_MASK (0x1<<0)
83#define S5PC100_CLKSRC1_UART_SHIFT (0)
84#define S5PC100_CLKSRC1_SPI0_MASK (0x3<<4)
85#define S5PC100_CLKSRC1_SPI0_SHIFT (4)
86#define S5PC100_CLKSRC1_SPI1_MASK (0x3<<8)
87#define S5PC100_CLKSRC1_SPI1_SHIFT (8)
88#define S5PC100_CLKSRC1_SPI2_MASK (0x3<<12)
89#define S5PC100_CLKSRC1_SPI2_SHIFT (12)
90#define S5PC100_CLKSRC1_IRDA_MASK (0x3<<16)
91#define S5PC100_CLKSRC1_IRDA_SHIFT (16)
92#define S5PC100_CLKSRC1_UHOST_MASK (0x3<<20)
93#define S5PC100_CLKSRC1_UHOST_SHIFT (20)
94#define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24)
95#define S5PC100_CLKSRC1_CLK48M_SHIFT (24) 66#define S5PC100_CLKSRC1_CLK48M_SHIFT (24)
96 67
97/* CLKSRC2 */
98#define S5PC100_CLKSRC2_MMC0_MASK (0x3<<0)
99#define S5PC100_CLKSRC2_MMC0_SHIFT (0)
100#define S5PC100_CLKSRC2_MMC1_MASK (0x3<<4)
101#define S5PC100_CLKSRC2_MMC1_SHIFT (4)
102#define S5PC100_CLKSRC2_MMC2_MASK (0x3<<8)
103#define S5PC100_CLKSRC2_MMC2_SHIFT (8)
104#define S5PC100_CLKSRC2_LCD_MASK (0x3<<12)
105#define S5PC100_CLKSRC2_LCD_SHIFT (12)
106#define S5PC100_CLKSRC2_FIMC0_MASK (0x3<<16)
107#define S5PC100_CLKSRC2_FIMC0_SHIFT (16)
108#define S5PC100_CLKSRC2_FIMC1_MASK (0x3<<20)
109#define S5PC100_CLKSRC2_FIMC1_SHIFT (20)
110#define S5PC100_CLKSRC2_FIMC2_MASK (0x3<<24)
111#define S5PC100_CLKSRC2_FIMC2_SHIFT (24)
112#define S5PC100_CLKSRC2_MIXER_MASK (0x3<<28)
113#define S5PC100_CLKSRC2_MIXER_SHIFT (28)
114
115/* CLKSRC3 */
116#define S5PC100_CLKSRC3_PWI_MASK (0x3<<0)
117#define S5PC100_CLKSRC3_PWI_SHIFT (0)
118#define S5PC100_CLKSRC3_HCLKD2_MASK (0x1<<4)
119#define S5PC100_CLKSRC3_HCLKD2_SHIFT (4)
120#define S5PC100_CLKSRC3_I2SD2_MASK (0x3<<8)
121#define S5PC100_CLKSRC3_I2SD2_SHIFT (8)
122#define S5PC100_CLKSRC3_AUDIO0_MASK (0x7<<12)
123#define S5PC100_CLKSRC3_AUDIO0_SHIFT (12)
124#define S5PC100_CLKSRC3_AUDIO1_MASK (0x7<<16)
125#define S5PC100_CLKSRC3_AUDIO1_SHIFT (16)
126#define S5PC100_CLKSRC3_AUDIO2_MASK (0x7<<20)
127#define S5PC100_CLKSRC3_AUDIO2_SHIFT (20)
128#define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24)
129#define S5PC100_CLKSRC3_SPDIF_SHIFT (24)
130
131/* CLKDIV0 */ 68/* CLKDIV0 */
132#define S5PC100_CLKDIV0_APLL_MASK (0x1<<0) 69#define S5PC100_CLKDIV0_APLL_MASK (0x1<<0)
133#define S5PC100_CLKDIV0_APLL_SHIFT (0) 70#define S5PC100_CLKDIV0_APLL_SHIFT (0)
@@ -140,7 +77,7 @@
140#define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16) 77#define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16)
141#define S5PC100_CLKDIV0_SECSS_SHIFT (16) 78#define S5PC100_CLKDIV0_SECSS_SHIFT (16)
142 79
143/* CLKDIV1 */ 80/* CLKDIV1 (OneNAND clock only used in one place, removed) */
144#define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0) 81#define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0)
145#define S5PC100_CLKDIV1_APLL2_SHIFT (0) 82#define S5PC100_CLKDIV1_APLL2_SHIFT (0)
146#define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) 83#define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4)
@@ -151,56 +88,12 @@
151#define S5PC100_CLKDIV1_D1_SHIFT (12) 88#define S5PC100_CLKDIV1_D1_SHIFT (12)
152#define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16) 89#define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16)
153#define S5PC100_CLKDIV1_PCLKD1_SHIFT (16) 90#define S5PC100_CLKDIV1_PCLKD1_SHIFT (16)
154#define S5PC100_CLKDIV1_ONENAND_MASK (0x3<<20)
155#define S5PC100_CLKDIV1_ONENAND_SHIFT (20)
156#define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24) 91#define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24)
157#define S5PC100_CLKDIV1_CAM_SHIFT (24) 92#define S5PC100_CLKDIV1_CAM_SHIFT (24)
158 93
159/* CLKDIV2 */ 94/* CLKDIV2 => removed in clksrc update */
160#define S5PC100_CLKDIV2_UART_MASK (0x7<<0) 95/* CLKDIV3 => removed in clksrc update, or not needed */
161#define S5PC100_CLKDIV2_UART_SHIFT (0) 96/* CLKDIV4 => removed in clksrc update, or not needed */
162#define S5PC100_CLKDIV2_SPI0_MASK (0xf<<4)
163#define S5PC100_CLKDIV2_SPI0_SHIFT (4)
164#define S5PC100_CLKDIV2_SPI1_MASK (0xf<<8)
165#define S5PC100_CLKDIV2_SPI1_SHIFT (8)
166#define S5PC100_CLKDIV2_SPI2_MASK (0xf<<12)
167#define S5PC100_CLKDIV2_SPI2_SHIFT (12)
168#define S5PC100_CLKDIV2_IRDA_MASK (0xf<<16)
169#define S5PC100_CLKDIV2_IRDA_SHIFT (16)
170#define S5PC100_CLKDIV2_UHOST_MASK (0xf<<20)
171#define S5PC100_CLKDIV2_UHOST_SHIFT (20)
172
173/* CLKDIV3 */
174#define S5PC100_CLKDIV3_MMC0_MASK (0xf<<0)
175#define S5PC100_CLKDIV3_MMC0_SHIFT (0)
176#define S5PC100_CLKDIV3_MMC1_MASK (0xf<<4)
177#define S5PC100_CLKDIV3_MMC1_SHIFT (4)
178#define S5PC100_CLKDIV3_MMC2_MASK (0xf<<8)
179#define S5PC100_CLKDIV3_MMC2_SHIFT (8)
180#define S5PC100_CLKDIV3_LCD_MASK (0xf<<12)
181#define S5PC100_CLKDIV3_LCD_SHIFT (12)
182#define S5PC100_CLKDIV3_FIMC0_MASK (0xf<<16)
183#define S5PC100_CLKDIV3_FIMC0_SHIFT (16)
184#define S5PC100_CLKDIV3_FIMC1_MASK (0xf<<20)
185#define S5PC100_CLKDIV3_FIMC1_SHIFT (20)
186#define S5PC100_CLKDIV3_FIMC2_MASK (0xf<<24)
187#define S5PC100_CLKDIV3_FIMC2_SHIFT (24)
188#define S5PC100_CLKDIV3_HDMI_MASK (0xf<<28)
189#define S5PC100_CLKDIV3_HDMI_SHIFT (28)
190
191/* CLKDIV4 */
192#define S5PC100_CLKDIV4_PWI_MASK (0x7<<0)
193#define S5PC100_CLKDIV4_PWI_SHIFT (0)
194#define S5PC100_CLKDIV4_HCLKD2_MASK (0x7<<4)
195#define S5PC100_CLKDIV4_HCLKD2_SHIFT (4)
196#define S5PC100_CLKDIV4_I2SD2_MASK (0xf<<8)
197#define S5PC100_CLKDIV4_I2SD2_SHIFT (8)
198#define S5PC100_CLKDIV4_AUDIO0_MASK (0xf<<12)
199#define S5PC100_CLKDIV4_AUDIO0_SHIFT (12)
200#define S5PC100_CLKDIV4_AUDIO1_MASK (0xf<<16)
201#define S5PC100_CLKDIV4_AUDIO1_SHIFT (16)
202#define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20)
203#define S5PC100_CLKDIV4_AUDIO2_SHIFT (20)
204 97
205/* HCLKD0/PCLKD0 Clock Gate 0 Registers */ 98/* HCLKD0/PCLKD0 Clock Gate 0 Registers */
206#define S5PC100_CLKGATE_D00_INTC (1<<0) 99#define S5PC100_CLKGATE_D00_INTC (1<<0)
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c
index e44fd04ef33..bfc52482781 100644
--- a/arch/arm/plat-s5pc1xx/irq.c
+++ b/arch/arm/plat-s5pc1xx/irq.c
@@ -20,87 +20,14 @@
20#include <asm/hardware/vic.h> 20#include <asm/hardware/vic.h>
21 21
22#include <mach/map.h> 22#include <mach/map.h>
23#include <plat/regs-timer.h> 23#include <plat/irq-vic-timer.h>
24#include <plat/irq-uart.h>
24#include <plat/cpu.h> 25#include <plat/cpu.h>
25 26
26/* Timer interrupt handling */
27
28static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
29{
30 generic_handle_irq(sub_irq);
31}
32
33static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
34{
35 s3c_irq_demux_timer(irq, IRQ_TIMER0);
36}
37
38static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
39{
40 s3c_irq_demux_timer(irq, IRQ_TIMER1);
41}
42
43static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
44{
45 s3c_irq_demux_timer(irq, IRQ_TIMER2);
46}
47
48static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
49{
50 s3c_irq_demux_timer(irq, IRQ_TIMER3);
51}
52
53static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
54{
55 s3c_irq_demux_timer(irq, IRQ_TIMER4);
56}
57
58/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
59
60static void s3c_irq_timer_mask(unsigned int irq)
61{
62 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
63
64 reg &= 0x1f; /* mask out pending interrupts */
65 reg &= ~(1 << (irq - IRQ_TIMER0));
66 __raw_writel(reg, S3C64XX_TINT_CSTAT);
67}
68
69static void s3c_irq_timer_unmask(unsigned int irq)
70{
71 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
72
73 reg &= 0x1f; /* mask out pending interrupts */
74 reg |= 1 << (irq - IRQ_TIMER0);
75 __raw_writel(reg, S3C64XX_TINT_CSTAT);
76}
77
78static void s3c_irq_timer_ack(unsigned int irq)
79{
80 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
81
82 reg &= 0x1f; /* mask out pending interrupts */
83 reg |= (1 << 5) << (irq - IRQ_TIMER0);
84 __raw_writel(reg, S3C64XX_TINT_CSTAT);
85}
86
87static struct irq_chip s3c_irq_timer = {
88 .name = "s3c-timer",
89 .mask = s3c_irq_timer_mask,
90 .unmask = s3c_irq_timer_unmask,
91 .ack = s3c_irq_timer_ack,
92};
93
94struct uart_irq {
95 void __iomem *regs;
96 unsigned int base_irq;
97 unsigned int parent_irq;
98};
99
100/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] 27/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
101 * are consecutive when looking up the interrupt in the demux routines. 28 * are consecutive when looking up the interrupt in the demux routines.
102 */ 29 */
103static struct uart_irq uart_irqs[] = { 30static struct s3c_uart_irq uart_irqs[] = {
104 [0] = { 31 [0] = {
105 .regs = (void *)S3C_VA_UART0, 32 .regs = (void *)S3C_VA_UART0,
106 .base_irq = IRQ_S3CUART_BASE0, 33 .base_irq = IRQ_S3CUART_BASE0,
@@ -123,113 +50,9 @@ static struct uart_irq uart_irqs[] = {
123 }, 50 },
124}; 51};
125 52
126static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
127{
128 struct uart_irq *uirq = get_irq_chip_data(irq);
129 return uirq->regs;
130}
131
132static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
133{
134 return irq & 3;
135}
136
137/* UART interrupt registers, not worth adding to seperate include header */
138#define S3C64XX_UINTP 0x30
139#define S3C64XX_UINTSP 0x34
140#define S3C64XX_UINTM 0x38
141
142static void s3c_irq_uart_mask(unsigned int irq)
143{
144 void __iomem *regs = s3c_irq_uart_base(irq);
145 unsigned int bit = s3c_irq_uart_bit(irq);
146 u32 reg;
147
148 reg = __raw_readl(regs + S3C64XX_UINTM);
149 reg |= (1 << bit);
150 __raw_writel(reg, regs + S3C64XX_UINTM);
151}
152
153static void s3c_irq_uart_maskack(unsigned int irq)
154{
155 void __iomem *regs = s3c_irq_uart_base(irq);
156 unsigned int bit = s3c_irq_uart_bit(irq);
157 u32 reg;
158
159 reg = __raw_readl(regs + S3C64XX_UINTM);
160 reg |= (1 << bit);
161 __raw_writel(reg, regs + S3C64XX_UINTM);
162 __raw_writel(1 << bit, regs + S3C64XX_UINTP);
163}
164
165static void s3c_irq_uart_unmask(unsigned int irq)
166{
167 void __iomem *regs = s3c_irq_uart_base(irq);
168 unsigned int bit = s3c_irq_uart_bit(irq);
169 u32 reg;
170
171 reg = __raw_readl(regs + S3C64XX_UINTM);
172 reg &= ~(1 << bit);
173 __raw_writel(reg, regs + S3C64XX_UINTM);
174}
175
176static void s3c_irq_uart_ack(unsigned int irq)
177{
178 void __iomem *regs = s3c_irq_uart_base(irq);
179 unsigned int bit = s3c_irq_uart_bit(irq);
180
181 __raw_writel(1 << bit, regs + S3C64XX_UINTP);
182}
183
184static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
185{
186 struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
187 u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
188 int base = uirq->base_irq;
189
190 if (pend & (1 << 0))
191 generic_handle_irq(base);
192 if (pend & (1 << 1))
193 generic_handle_irq(base + 1);
194 if (pend & (1 << 2))
195 generic_handle_irq(base + 2);
196 if (pend & (1 << 3))
197 generic_handle_irq(base + 3);
198}
199
200static struct irq_chip s3c_irq_uart = {
201 .name = "s3c-uart",
202 .mask = s3c_irq_uart_mask,
203 .unmask = s3c_irq_uart_unmask,
204 .mask_ack = s3c_irq_uart_maskack,
205 .ack = s3c_irq_uart_ack,
206};
207
208static void __init s5pc1xx_uart_irq(struct uart_irq *uirq)
209{
210 void __iomem *reg_base = uirq->regs;
211 unsigned int irq;
212 int offs;
213
214 /* mask all interrupts at the start. */
215 __raw_writel(0xf, reg_base + S3C64XX_UINTM);
216
217 for (offs = 0; offs < 3; offs++) {
218 irq = uirq->base_irq + offs;
219
220 set_irq_chip(irq, &s3c_irq_uart);
221 set_irq_chip_data(irq, uirq);
222 set_irq_handler(irq, handle_level_irq);
223 set_irq_flags(irq, IRQF_VALID);
224 }
225
226 set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
227}
228
229void __init s5pc1xx_init_irq(u32 *vic_valid, int num) 53void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
230{ 54{
231 int i; 55 int i;
232 int uart, irq;
233 56
234 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); 57 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
235 58
@@ -240,20 +63,13 @@ void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
240 63
241 /* add the timer sub-irqs */ 64 /* add the timer sub-irqs */
242 65
243 set_irq_chained_handler(IRQ_TIMER0, s3c_irq_demux_timer0); 66 s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
244 set_irq_chained_handler(IRQ_TIMER1, s3c_irq_demux_timer1); 67 s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
245 set_irq_chained_handler(IRQ_TIMER2, s3c_irq_demux_timer2); 68 s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
246 set_irq_chained_handler(IRQ_TIMER3, s3c_irq_demux_timer3); 69 s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
247 set_irq_chained_handler(IRQ_TIMER4, s3c_irq_demux_timer4); 70 s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
248
249 for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
250 set_irq_chip(irq, &s3c_irq_timer);
251 set_irq_handler(irq, handle_level_irq);
252 set_irq_flags(irq, IRQF_VALID);
253 }
254 71
255 for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) 72 s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
256 s5pc1xx_uart_irq(&uart_irqs[uart]);
257} 73}
258 74
259 75
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
index b436d44510c..2bf6c57a96a 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
@@ -29,6 +29,7 @@
29 29
30#include <plat/regs-clock.h> 30#include <plat/regs-clock.h>
31#include <plat/clock.h> 31#include <plat/clock.h>
32#include <plat/clock-clksrc.h>
32#include <plat/cpu.h> 33#include <plat/cpu.h>
33#include <plat/pll.h> 34#include <plat/pll.h>
34#include <plat/devs.h> 35#include <plat/devs.h>
@@ -51,23 +52,6 @@ static struct clk clk_ext_xtal_mux = {
51#define clk_fout_mpll clk_mpll 52#define clk_fout_mpll clk_mpll
52#define clk_vclk_54m clk_54m 53#define clk_vclk_54m clk_54m
53 54
54struct clk_sources {
55 unsigned int nr_sources;
56 struct clk **sources;
57};
58
59struct clksrc_clk {
60 struct clk clk;
61 unsigned int mask;
62 unsigned int shift;
63
64 struct clk_sources *sources;
65
66 unsigned int divider_shift;
67 void __iomem *reg_divider;
68 void __iomem *reg_source;
69};
70
71/* APLL */ 55/* APLL */
72static struct clk clk_fout_apll = { 56static struct clk clk_fout_apll = {
73 .name = "fout_apll", 57 .name = "fout_apll",
@@ -80,7 +64,7 @@ static struct clk *clk_src_apll_list[] = {
80 [1] = &clk_fout_apll, 64 [1] = &clk_fout_apll,
81}; 65};
82 66
83static struct clk_sources clk_src_apll = { 67static struct clksrc_sources clk_src_apll = {
84 .sources = clk_src_apll_list, 68 .sources = clk_src_apll_list,
85 .nr_sources = ARRAY_SIZE(clk_src_apll_list), 69 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
86}; 70};
@@ -90,10 +74,8 @@ static struct clksrc_clk clk_mout_apll = {
90 .name = "mout_apll", 74 .name = "mout_apll",
91 .id = -1, 75 .id = -1,
92 }, 76 },
93 .shift = S5PC100_CLKSRC0_APLL_SHIFT,
94 .mask = S5PC100_CLKSRC0_APLL_MASK,
95 .sources = &clk_src_apll, 77 .sources = &clk_src_apll,
96 .reg_source = S5PC100_CLKSRC0, 78 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 0, .size = 1, },
97}; 79};
98 80
99static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk) 81static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk)
@@ -111,7 +93,9 @@ static struct clk clk_dout_apll = {
111 .name = "dout_apll", 93 .name = "dout_apll",
112 .id = -1, 94 .id = -1,
113 .parent = &clk_mout_apll.clk, 95 .parent = &clk_mout_apll.clk,
114 .get_rate = s5pc100_clk_dout_apll_get_rate, 96 .ops = &(struct clk_ops) {
97 .get_rate = s5pc100_clk_dout_apll_get_rate,
98 },
115}; 99};
116 100
117static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk) 101static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk)
@@ -165,9 +149,11 @@ static struct clk clk_arm = {
165 .name = "armclk", 149 .name = "armclk",
166 .id = -1, 150 .id = -1,
167 .parent = &clk_dout_apll, 151 .parent = &clk_dout_apll,
168 .get_rate = s5pc100_clk_arm_get_rate, 152 .ops = &(struct clk_ops) {
169 .set_rate = s5pc100_clk_arm_set_rate, 153 .get_rate = s5pc100_clk_arm_get_rate,
170 .round_rate = s5pc100_clk_arm_round_rate, 154 .set_rate = s5pc100_clk_arm_set_rate,
155 .round_rate = s5pc100_clk_arm_round_rate,
156 },
171}; 157};
172 158
173static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk) 159static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk)
@@ -185,7 +171,9 @@ static struct clk clk_dout_d0_bus = {
185 .name = "dout_d0_bus", 171 .name = "dout_d0_bus",
186 .id = -1, 172 .id = -1,
187 .parent = &clk_arm, 173 .parent = &clk_arm,
188 .get_rate = s5pc100_clk_dout_d0_bus_get_rate, 174 .ops = &(struct clk_ops) {
175 .get_rate = s5pc100_clk_dout_d0_bus_get_rate,
176 },
189}; 177};
190 178
191static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk) 179static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk)
@@ -203,7 +191,9 @@ static struct clk clk_dout_pclkd0 = {
203 .name = "dout_pclkd0", 191 .name = "dout_pclkd0",
204 .id = -1, 192 .id = -1,
205 .parent = &clk_dout_d0_bus, 193 .parent = &clk_dout_d0_bus,
206 .get_rate = s5pc100_clk_dout_pclkd0_get_rate, 194 .ops = &(struct clk_ops) {
195 .get_rate = s5pc100_clk_dout_pclkd0_get_rate,
196 },
207}; 197};
208 198
209static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk) 199static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk)
@@ -221,7 +211,9 @@ static struct clk clk_dout_apll2 = {
221 .name = "dout_apll2", 211 .name = "dout_apll2",
222 .id = -1, 212 .id = -1,
223 .parent = &clk_mout_apll.clk, 213 .parent = &clk_mout_apll.clk,
224 .get_rate = s5pc100_clk_dout_apll2_get_rate, 214 .ops = &(struct clk_ops) {
215 .get_rate = s5pc100_clk_dout_apll2_get_rate,
216 },
225}; 217};
226 218
227/* MPLL */ 219/* MPLL */
@@ -230,7 +222,7 @@ static struct clk *clk_src_mpll_list[] = {
230 [1] = &clk_fout_mpll, 222 [1] = &clk_fout_mpll,
231}; 223};
232 224
233static struct clk_sources clk_src_mpll = { 225static struct clksrc_sources clk_src_mpll = {
234 .sources = clk_src_mpll_list, 226 .sources = clk_src_mpll_list,
235 .nr_sources = ARRAY_SIZE(clk_src_mpll_list), 227 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
236}; 228};
@@ -240,10 +232,8 @@ static struct clksrc_clk clk_mout_mpll = {
240 .name = "mout_mpll", 232 .name = "mout_mpll",
241 .id = -1, 233 .id = -1,
242 }, 234 },
243 .shift = S5PC100_CLKSRC0_MPLL_SHIFT,
244 .mask = S5PC100_CLKSRC0_MPLL_MASK,
245 .sources = &clk_src_mpll, 235 .sources = &clk_src_mpll,
246 .reg_source = S5PC100_CLKSRC0, 236 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 4, .size = 1, },
247}; 237};
248 238
249static struct clk *clkset_am_list[] = { 239static struct clk *clkset_am_list[] = {
@@ -251,7 +241,7 @@ static struct clk *clkset_am_list[] = {
251 [1] = &clk_dout_apll2, 241 [1] = &clk_dout_apll2,
252}; 242};
253 243
254static struct clk_sources clk_src_am = { 244static struct clksrc_sources clk_src_am = {
255 .sources = clkset_am_list, 245 .sources = clkset_am_list,
256 .nr_sources = ARRAY_SIZE(clkset_am_list), 246 .nr_sources = ARRAY_SIZE(clkset_am_list),
257}; 247};
@@ -261,10 +251,8 @@ static struct clksrc_clk clk_mout_am = {
261 .name = "mout_am", 251 .name = "mout_am",
262 .id = -1, 252 .id = -1,
263 }, 253 },
264 .shift = S5PC100_CLKSRC0_AMMUX_SHIFT,
265 .mask = S5PC100_CLKSRC0_AMMUX_MASK,
266 .sources = &clk_src_am, 254 .sources = &clk_src_am,
267 .reg_source = S5PC100_CLKSRC0, 255 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 16, .size = 1, },
268}; 256};
269 257
270static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk) 258static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk)
@@ -284,7 +272,9 @@ static struct clk clk_dout_d1_bus = {
284 .name = "dout_d1_bus", 272 .name = "dout_d1_bus",
285 .id = -1, 273 .id = -1,
286 .parent = &clk_mout_am.clk, 274 .parent = &clk_mout_am.clk,
287 .get_rate = s5pc100_clk_dout_d1_bus_get_rate, 275 .ops = &(struct clk_ops) {
276 .get_rate = s5pc100_clk_dout_d1_bus_get_rate,
277 },
288}; 278};
289 279
290static struct clk *clkset_onenand_list[] = { 280static struct clk *clkset_onenand_list[] = {
@@ -292,7 +282,7 @@ static struct clk *clkset_onenand_list[] = {
292 [1] = &clk_dout_d1_bus, 282 [1] = &clk_dout_d1_bus,
293}; 283};
294 284
295static struct clk_sources clk_src_onenand = { 285static struct clksrc_sources clk_src_onenand = {
296 .sources = clkset_onenand_list, 286 .sources = clkset_onenand_list,
297 .nr_sources = ARRAY_SIZE(clkset_onenand_list), 287 .nr_sources = ARRAY_SIZE(clkset_onenand_list),
298}; 288};
@@ -302,10 +292,8 @@ static struct clksrc_clk clk_mout_onenand = {
302 .name = "mout_onenand", 292 .name = "mout_onenand",
303 .id = -1, 293 .id = -1,
304 }, 294 },
305 .shift = S5PC100_CLKSRC0_ONENAND_SHIFT,
306 .mask = S5PC100_CLKSRC0_ONENAND_MASK,
307 .sources = &clk_src_onenand, 295 .sources = &clk_src_onenand,
308 .reg_source = S5PC100_CLKSRC0, 296 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 24, .size = 1, },
309}; 297};
310 298
311static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk) 299static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk)
@@ -325,7 +313,9 @@ static struct clk clk_dout_pclkd1 = {
325 .name = "dout_pclkd1", 313 .name = "dout_pclkd1",
326 .id = -1, 314 .id = -1,
327 .parent = &clk_dout_d1_bus, 315 .parent = &clk_dout_d1_bus,
328 .get_rate = s5pc100_clk_dout_pclkd1_get_rate, 316 .ops = &(struct clk_ops) {
317 .get_rate = s5pc100_clk_dout_pclkd1_get_rate,
318 },
329}; 319};
330 320
331static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk) 321static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk)
@@ -345,7 +335,9 @@ static struct clk clk_dout_mpll2 = {
345 .name = "dout_mpll2", 335 .name = "dout_mpll2",
346 .id = -1, 336 .id = -1,
347 .parent = &clk_mout_am.clk, 337 .parent = &clk_mout_am.clk,
348 .get_rate = s5pc100_clk_dout_mpll2_get_rate, 338 .ops = &(struct clk_ops) {
339 .get_rate = s5pc100_clk_dout_mpll2_get_rate,
340 },
349}; 341};
350 342
351static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk) 343static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk)
@@ -365,7 +357,9 @@ static struct clk clk_dout_cam = {
365 .name = "dout_cam", 357 .name = "dout_cam",
366 .id = -1, 358 .id = -1,
367 .parent = &clk_dout_mpll2, 359 .parent = &clk_dout_mpll2,
368 .get_rate = s5pc100_clk_dout_cam_get_rate, 360 .ops = &(struct clk_ops) {
361 .get_rate = s5pc100_clk_dout_cam_get_rate,
362 },
369}; 363};
370 364
371static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk) 365static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk)
@@ -385,7 +379,9 @@ static struct clk clk_dout_mpll = {
385 .name = "dout_mpll", 379 .name = "dout_mpll",
386 .id = -1, 380 .id = -1,
387 .parent = &clk_mout_am.clk, 381 .parent = &clk_mout_am.clk,
388 .get_rate = s5pc100_clk_dout_mpll_get_rate, 382 .ops = &(struct clk_ops) {
383 .get_rate = s5pc100_clk_dout_mpll_get_rate,
384 },
389}; 385};
390 386
391/* EPLL */ 387/* EPLL */
@@ -399,7 +395,7 @@ static struct clk *clk_src_epll_list[] = {
399 [1] = &clk_fout_epll, 395 [1] = &clk_fout_epll,
400}; 396};
401 397
402static struct clk_sources clk_src_epll = { 398static struct clksrc_sources clk_src_epll = {
403 .sources = clk_src_epll_list, 399 .sources = clk_src_epll_list,
404 .nr_sources = ARRAY_SIZE(clk_src_epll_list), 400 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
405}; 401};
@@ -409,10 +405,8 @@ static struct clksrc_clk clk_mout_epll = {
409 .name = "mout_epll", 405 .name = "mout_epll",
410 .id = -1, 406 .id = -1,
411 }, 407 },
412 .shift = S5PC100_CLKSRC0_EPLL_SHIFT, 408 .sources = &clk_src_epll,
413 .mask = S5PC100_CLKSRC0_EPLL_MASK, 409 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 8, .size = 1, },
414 .sources = &clk_src_epll,
415 .reg_source = S5PC100_CLKSRC0,
416}; 410};
417 411
418/* HPLL */ 412/* HPLL */
@@ -426,7 +420,7 @@ static struct clk *clk_src_hpll_list[] = {
426 [1] = &clk_fout_hpll, 420 [1] = &clk_fout_hpll,
427}; 421};
428 422
429static struct clk_sources clk_src_hpll = { 423static struct clksrc_sources clk_src_hpll = {
430 .sources = clk_src_hpll_list, 424 .sources = clk_src_hpll_list,
431 .nr_sources = ARRAY_SIZE(clk_src_hpll_list), 425 .nr_sources = ARRAY_SIZE(clk_src_hpll_list),
432}; 426};
@@ -436,10 +430,8 @@ static struct clksrc_clk clk_mout_hpll = {
436 .name = "mout_hpll", 430 .name = "mout_hpll",
437 .id = -1, 431 .id = -1,
438 }, 432 },
439 .shift = S5PC100_CLKSRC0_HPLL_SHIFT, 433 .sources = &clk_src_hpll,
440 .mask = S5PC100_CLKSRC0_HPLL_MASK, 434 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 12, .size = 1, },
441 .sources = &clk_src_hpll,
442 .reg_source = S5PC100_CLKSRC0,
443}; 435};
444 436
445/* Peripherals */ 437/* Peripherals */
@@ -454,190 +446,6 @@ static struct clksrc_clk clk_mout_hpll = {
454 * have a common parent divisor so are not included here. 446 * have a common parent divisor so are not included here.
455 */ 447 */
456 448
457static inline struct clksrc_clk *to_clksrc(struct clk *clk)
458{
459 return container_of(clk, struct clksrc_clk, clk);
460}
461
462static unsigned long s5pc100_getrate_clksrc(struct clk *clk)
463{
464 struct clksrc_clk *sclk = to_clksrc(clk);
465 unsigned long rate = clk_get_rate(clk->parent);
466 u32 clkdiv = __raw_readl(sclk->reg_divider);
467
468 clkdiv >>= sclk->divider_shift;
469 clkdiv &= 0xf;
470 clkdiv++;
471
472 rate /= clkdiv;
473 return rate;
474}
475
476static int s5pc100_setrate_clksrc(struct clk *clk, unsigned long rate)
477{
478 struct clksrc_clk *sclk = to_clksrc(clk);
479 void __iomem *reg = sclk->reg_divider;
480 unsigned int div;
481 u32 val;
482
483 rate = clk_round_rate(clk, rate);
484 div = clk_get_rate(clk->parent) / rate;
485 if (div > 16)
486 return -EINVAL;
487
488 val = __raw_readl(reg);
489 val &= ~(0xf << sclk->divider_shift);
490 val |= (div - 1) << sclk->divider_shift;
491 __raw_writel(val, reg);
492
493 return 0;
494}
495
496static int s5pc100_setparent_clksrc(struct clk *clk, struct clk *parent)
497{
498 struct clksrc_clk *sclk = to_clksrc(clk);
499 struct clk_sources *srcs = sclk->sources;
500 u32 clksrc = __raw_readl(sclk->reg_source);
501 int src_nr = -1;
502 int ptr;
503
504 for (ptr = 0; ptr < srcs->nr_sources; ptr++)
505 if (srcs->sources[ptr] == parent) {
506 src_nr = ptr;
507 break;
508 }
509
510 if (src_nr >= 0) {
511 clksrc &= ~sclk->mask;
512 clksrc |= src_nr << sclk->shift;
513
514 __raw_writel(clksrc, sclk->reg_source);
515 return 0;
516 }
517
518 return -EINVAL;
519}
520
521static unsigned long s5pc100_roundrate_clksrc(struct clk *clk,
522 unsigned long rate)
523{
524 unsigned long parent_rate = clk_get_rate(clk->parent);
525 int div;
526
527 if (rate > parent_rate)
528 rate = parent_rate;
529 else {
530 div = rate / parent_rate;
531
532 if (div == 0)
533 div = 1;
534 if (div > 16)
535 div = 16;
536
537 rate = parent_rate / div;
538 }
539
540 return rate;
541}
542
543static struct clk *clkset_spi_list[] = {
544 &clk_mout_epll.clk,
545 &clk_dout_mpll2,
546 &clk_fin_epll,
547 &clk_mout_hpll.clk,
548};
549
550static struct clk_sources clkset_spi = {
551 .sources = clkset_spi_list,
552 .nr_sources = ARRAY_SIZE(clkset_spi_list),
553};
554
555static struct clksrc_clk clk_spi0 = {
556 .clk = {
557 .name = "spi_bus",
558 .id = 0,
559 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0,
560 .enable = s5pc100_sclk0_ctrl,
561 .set_parent = s5pc100_setparent_clksrc,
562 .get_rate = s5pc100_getrate_clksrc,
563 .set_rate = s5pc100_setrate_clksrc,
564 .round_rate = s5pc100_roundrate_clksrc,
565 },
566 .shift = S5PC100_CLKSRC1_SPI0_SHIFT,
567 .mask = S5PC100_CLKSRC1_SPI0_MASK,
568 .sources = &clkset_spi,
569 .divider_shift = S5PC100_CLKDIV2_SPI0_SHIFT,
570 .reg_divider = S5PC100_CLKDIV2,
571 .reg_source = S5PC100_CLKSRC1,
572};
573
574static struct clksrc_clk clk_spi1 = {
575 .clk = {
576 .name = "spi_bus",
577 .id = 1,
578 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
579 .enable = s5pc100_sclk0_ctrl,
580 .set_parent = s5pc100_setparent_clksrc,
581 .get_rate = s5pc100_getrate_clksrc,
582 .set_rate = s5pc100_setrate_clksrc,
583 .round_rate = s5pc100_roundrate_clksrc,
584 },
585 .shift = S5PC100_CLKSRC1_SPI1_SHIFT,
586 .mask = S5PC100_CLKSRC1_SPI1_MASK,
587 .sources = &clkset_spi,
588 .divider_shift = S5PC100_CLKDIV2_SPI1_SHIFT,
589 .reg_divider = S5PC100_CLKDIV2,
590 .reg_source = S5PC100_CLKSRC1,
591};
592
593static struct clksrc_clk clk_spi2 = {
594 .clk = {
595 .name = "spi_bus",
596 .id = 2,
597 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
598 .enable = s5pc100_sclk0_ctrl,
599 .set_parent = s5pc100_setparent_clksrc,
600 .get_rate = s5pc100_getrate_clksrc,
601 .set_rate = s5pc100_setrate_clksrc,
602 .round_rate = s5pc100_roundrate_clksrc,
603 },
604 .shift = S5PC100_CLKSRC1_SPI2_SHIFT,
605 .mask = S5PC100_CLKSRC1_SPI2_MASK,
606 .sources = &clkset_spi,
607 .divider_shift = S5PC100_CLKDIV2_SPI2_SHIFT,
608 .reg_divider = S5PC100_CLKDIV2,
609 .reg_source = S5PC100_CLKSRC1,
610};
611
612static struct clk *clkset_uart_list[] = {
613 &clk_mout_epll.clk,
614 &clk_dout_mpll,
615};
616
617static struct clk_sources clkset_uart = {
618 .sources = clkset_uart_list,
619 .nr_sources = ARRAY_SIZE(clkset_uart_list),
620};
621
622static struct clksrc_clk clk_uart_uclk1 = {
623 .clk = {
624 .name = "uclk1",
625 .id = -1,
626 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
627 .enable = s5pc100_sclk0_ctrl,
628 .set_parent = s5pc100_setparent_clksrc,
629 .get_rate = s5pc100_getrate_clksrc,
630 .set_rate = s5pc100_setrate_clksrc,
631 .round_rate = s5pc100_roundrate_clksrc,
632 },
633 .shift = S5PC100_CLKSRC1_UART_SHIFT,
634 .mask = S5PC100_CLKSRC1_UART_MASK,
635 .sources = &clkset_uart,
636 .divider_shift = S5PC100_CLKDIV2_UART_SHIFT,
637 .reg_divider = S5PC100_CLKDIV2,
638 .reg_source = S5PC100_CLKSRC1,
639};
640
641static struct clk clk_iis_cd0 = { 449static struct clk clk_iis_cd0 = {
642 .name = "iis_cdclk0", 450 .name = "iis_cdclk0",
643 .id = -1, 451 .id = -1,
@@ -672,28 +480,31 @@ static struct clk *clkset_audio0_list[] = {
672 &clk_mout_hpll.clk, 480 &clk_mout_hpll.clk,
673}; 481};
674 482
675static struct clk_sources clkset_audio0 = { 483static struct clksrc_sources clkset_audio0 = {
676 .sources = clkset_audio0_list, 484 .sources = clkset_audio0_list,
677 .nr_sources = ARRAY_SIZE(clkset_audio0_list), 485 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
678}; 486};
679 487
680static struct clksrc_clk clk_audio0 = { 488static struct clk *clkset_spi_list[] = {
681 .clk = { 489 &clk_mout_epll.clk,
682 .name = "audio-bus", 490 &clk_dout_mpll2,
683 .id = 0, 491 &clk_fin_epll,
684 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, 492 &clk_mout_hpll.clk,
685 .enable = s5pc100_sclk1_ctrl, 493};
686 .set_parent = s5pc100_setparent_clksrc, 494
687 .get_rate = s5pc100_getrate_clksrc, 495static struct clksrc_sources clkset_spi = {
688 .set_rate = s5pc100_setrate_clksrc, 496 .sources = clkset_spi_list,
689 .round_rate = s5pc100_roundrate_clksrc, 497 .nr_sources = ARRAY_SIZE(clkset_spi_list),
690 }, 498};
691 .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT, 499
692 .mask = S5PC100_CLKSRC3_AUDIO0_MASK, 500static struct clk *clkset_uart_list[] = {
693 .sources = &clkset_audio0, 501 &clk_mout_epll.clk,
694 .divider_shift = S5PC100_CLKDIV4_AUDIO0_SHIFT, 502 &clk_dout_mpll,
695 .reg_divider = S5PC100_CLKDIV4, 503};
696 .reg_source = S5PC100_CLKSRC3, 504
505static struct clksrc_sources clkset_uart = {
506 .sources = clkset_uart_list,
507 .nr_sources = ARRAY_SIZE(clkset_uart_list),
697}; 508};
698 509
699static struct clk *clkset_audio1_list[] = { 510static struct clk *clkset_audio1_list[] = {
@@ -705,30 +516,11 @@ static struct clk *clkset_audio1_list[] = {
705 &clk_mout_hpll.clk, 516 &clk_mout_hpll.clk,
706}; 517};
707 518
708static struct clk_sources clkset_audio1 = { 519static struct clksrc_sources clkset_audio1 = {
709 .sources = clkset_audio1_list, 520 .sources = clkset_audio1_list,
710 .nr_sources = ARRAY_SIZE(clkset_audio1_list), 521 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
711}; 522};
712 523
713static struct clksrc_clk clk_audio1 = {
714 .clk = {
715 .name = "audio-bus",
716 .id = 1,
717 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
718 .enable = s5pc100_sclk1_ctrl,
719 .set_parent = s5pc100_setparent_clksrc,
720 .get_rate = s5pc100_getrate_clksrc,
721 .set_rate = s5pc100_setrate_clksrc,
722 .round_rate = s5pc100_roundrate_clksrc,
723 },
724 .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT,
725 .mask = S5PC100_CLKSRC3_AUDIO1_MASK,
726 .sources = &clkset_audio1,
727 .divider_shift = S5PC100_CLKDIV4_AUDIO1_SHIFT,
728 .reg_divider = S5PC100_CLKDIV4,
729 .reg_source = S5PC100_CLKSRC3,
730};
731
732static struct clk *clkset_audio2_list[] = { 524static struct clk *clkset_audio2_list[] = {
733 &clk_mout_epll.clk, 525 &clk_mout_epll.clk,
734 &clk_dout_mpll, 526 &clk_dout_mpll,
@@ -737,52 +529,56 @@ static struct clk *clkset_audio2_list[] = {
737 &clk_mout_hpll.clk, 529 &clk_mout_hpll.clk,
738}; 530};
739 531
740static struct clk_sources clkset_audio2 = { 532static struct clksrc_sources clkset_audio2 = {
741 .sources = clkset_audio2_list, 533 .sources = clkset_audio2_list,
742 .nr_sources = ARRAY_SIZE(clkset_audio2_list), 534 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
743}; 535};
744 536
745static struct clksrc_clk clk_audio2 = { 537static struct clksrc_clk clksrc_audio[] = {
746 .clk = { 538 {
747 .name = "audio-bus", 539 .clk = {
748 .id = 2, 540 .name = "audio-bus",
749 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, 541 .id = 0,
750 .enable = s5pc100_sclk1_ctrl, 542 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0,
751 .set_parent = s5pc100_setparent_clksrc, 543 .enable = s5pc100_sclk1_ctrl,
752 .get_rate = s5pc100_getrate_clksrc, 544 },
753 .set_rate = s5pc100_setrate_clksrc, 545 .sources = &clkset_audio0,
754 .round_rate = s5pc100_roundrate_clksrc, 546 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, },
547 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, },
548 }, {
549 .clk = {
550 .name = "audio-bus",
551 .id = 1,
552 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
553 .enable = s5pc100_sclk1_ctrl,
554 },
555 .sources = &clkset_audio1,
556 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, },
557 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, },
558 }, {
559 .clk = {
560 .name = "audio-bus",
561 .id = 2,
562 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2,
563 .enable = s5pc100_sclk1_ctrl,
564 },
565 .sources = &clkset_audio2,
566 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, },
567 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, },
755 }, 568 },
756 .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT,
757 .mask = S5PC100_CLKSRC3_AUDIO2_MASK,
758 .sources = &clkset_audio2,
759 .divider_shift = S5PC100_CLKDIV4_AUDIO2_SHIFT,
760 .reg_divider = S5PC100_CLKDIV4,
761 .reg_source = S5PC100_CLKSRC3,
762}; 569};
763 570
764static struct clk *clkset_spdif_list[] = { 571static struct clk *clkset_spdif_list[] = {
765 &clk_audio0.clk, 572 &clksrc_audio[0].clk,
766 &clk_audio1.clk, 573 &clksrc_audio[1].clk,
767 &clk_audio2.clk, 574 &clksrc_audio[2].clk,
768}; 575};
769 576
770static struct clk_sources clkset_spdif = { 577static struct clksrc_sources clkset_spdif = {
771 .sources = clkset_spdif_list, 578 .sources = clkset_spdif_list,
772 .nr_sources = ARRAY_SIZE(clkset_spdif_list), 579 .nr_sources = ARRAY_SIZE(clkset_spdif_list),
773}; 580};
774 581
775static struct clksrc_clk clk_spdif = {
776 .clk = {
777 .name = "spdif",
778 .id = -1,
779 },
780 .shift = S5PC100_CLKSRC3_SPDIF_SHIFT,
781 .mask = S5PC100_CLKSRC3_SPDIF_MASK,
782 .sources = &clkset_spdif,
783 .reg_source = S5PC100_CLKSRC3,
784};
785
786static struct clk *clkset_lcd_fimc_list[] = { 582static struct clk *clkset_lcd_fimc_list[] = {
787 &clk_mout_epll.clk, 583 &clk_mout_epll.clk,
788 &clk_dout_mpll, 584 &clk_dout_mpll,
@@ -790,87 +586,11 @@ static struct clk *clkset_lcd_fimc_list[] = {
790 &clk_vclk_54m, 586 &clk_vclk_54m,
791}; 587};
792 588
793static struct clk_sources clkset_lcd_fimc = { 589static struct clksrc_sources clkset_lcd_fimc = {
794 .sources = clkset_lcd_fimc_list, 590 .sources = clkset_lcd_fimc_list,
795 .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list), 591 .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list),
796}; 592};
797 593
798static struct clksrc_clk clk_lcd = {
799 .clk = {
800 .name = "lcd",
801 .id = -1,
802 .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
803 .enable = s5pc100_sclk1_ctrl,
804 .set_parent = s5pc100_setparent_clksrc,
805 .get_rate = s5pc100_getrate_clksrc,
806 .set_rate = s5pc100_setrate_clksrc,
807 .round_rate = s5pc100_roundrate_clksrc,
808 },
809 .shift = S5PC100_CLKSRC2_LCD_SHIFT,
810 .mask = S5PC100_CLKSRC2_LCD_MASK,
811 .sources = &clkset_lcd_fimc,
812 .divider_shift = S5PC100_CLKDIV3_LCD_SHIFT,
813 .reg_divider = S5PC100_CLKDIV3,
814 .reg_source = S5PC100_CLKSRC2,
815};
816
817static struct clksrc_clk clk_fimc0 = {
818 .clk = {
819 .name = "fimc",
820 .id = 0,
821 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
822 .enable = s5pc100_sclk1_ctrl,
823 .set_parent = s5pc100_setparent_clksrc,
824 .get_rate = s5pc100_getrate_clksrc,
825 .set_rate = s5pc100_setrate_clksrc,
826 .round_rate = s5pc100_roundrate_clksrc,
827 },
828 .shift = S5PC100_CLKSRC2_FIMC0_SHIFT,
829 .mask = S5PC100_CLKSRC2_FIMC0_MASK,
830 .sources = &clkset_lcd_fimc,
831 .divider_shift = S5PC100_CLKDIV3_FIMC0_SHIFT,
832 .reg_divider = S5PC100_CLKDIV3,
833 .reg_source = S5PC100_CLKSRC2,
834};
835
836static struct clksrc_clk clk_fimc1 = {
837 .clk = {
838 .name = "fimc",
839 .id = 1,
840 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
841 .enable = s5pc100_sclk1_ctrl,
842 .set_parent = s5pc100_setparent_clksrc,
843 .get_rate = s5pc100_getrate_clksrc,
844 .set_rate = s5pc100_setrate_clksrc,
845 .round_rate = s5pc100_roundrate_clksrc,
846 },
847 .shift = S5PC100_CLKSRC2_FIMC1_SHIFT,
848 .mask = S5PC100_CLKSRC2_FIMC1_MASK,
849 .sources = &clkset_lcd_fimc,
850 .divider_shift = S5PC100_CLKDIV3_FIMC1_SHIFT,
851 .reg_divider = S5PC100_CLKDIV3,
852 .reg_source = S5PC100_CLKSRC2,
853};
854
855static struct clksrc_clk clk_fimc2 = {
856 .clk = {
857 .name = "fimc",
858 .id = 2,
859 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
860 .enable = s5pc100_sclk1_ctrl,
861 .set_parent = s5pc100_setparent_clksrc,
862 .get_rate = s5pc100_getrate_clksrc,
863 .set_rate = s5pc100_setrate_clksrc,
864 .round_rate = s5pc100_roundrate_clksrc,
865 },
866 .shift = S5PC100_CLKSRC2_FIMC2_SHIFT,
867 .mask = S5PC100_CLKSRC2_FIMC2_MASK,
868 .sources = &clkset_lcd_fimc,
869 .divider_shift = S5PC100_CLKDIV3_FIMC2_SHIFT,
870 .reg_divider = S5PC100_CLKDIV3,
871 .reg_source = S5PC100_CLKSRC2,
872};
873
874static struct clk *clkset_mmc_list[] = { 594static struct clk *clkset_mmc_list[] = {
875 &clk_mout_epll.clk, 595 &clk_mout_epll.clk,
876 &clk_dout_mpll, 596 &clk_dout_mpll,
@@ -878,69 +598,11 @@ static struct clk *clkset_mmc_list[] = {
878 &clk_mout_hpll.clk , 598 &clk_mout_hpll.clk ,
879}; 599};
880 600
881static struct clk_sources clkset_mmc = { 601static struct clksrc_sources clkset_mmc = {
882 .sources = clkset_mmc_list, 602 .sources = clkset_mmc_list,
883 .nr_sources = ARRAY_SIZE(clkset_mmc_list), 603 .nr_sources = ARRAY_SIZE(clkset_mmc_list),
884}; 604};
885 605
886static struct clksrc_clk clk_mmc0 = {
887 .clk = {
888 .name = "mmc_bus",
889 .id = 0,
890 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
891 .enable = s5pc100_sclk0_ctrl,
892 .set_parent = s5pc100_setparent_clksrc,
893 .get_rate = s5pc100_getrate_clksrc,
894 .set_rate = s5pc100_setrate_clksrc,
895 .round_rate = s5pc100_roundrate_clksrc,
896 },
897 .shift = S5PC100_CLKSRC2_MMC0_SHIFT,
898 .mask = S5PC100_CLKSRC2_MMC0_MASK,
899 .sources = &clkset_mmc,
900 .divider_shift = S5PC100_CLKDIV3_MMC0_SHIFT,
901 .reg_divider = S5PC100_CLKDIV3,
902 .reg_source = S5PC100_CLKSRC2,
903};
904
905static struct clksrc_clk clk_mmc1 = {
906 .clk = {
907 .name = "mmc_bus",
908 .id = 1,
909 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
910 .enable = s5pc100_sclk0_ctrl,
911 .set_parent = s5pc100_setparent_clksrc,
912 .get_rate = s5pc100_getrate_clksrc,
913 .set_rate = s5pc100_setrate_clksrc,
914 .round_rate = s5pc100_roundrate_clksrc,
915 },
916 .shift = S5PC100_CLKSRC2_MMC1_SHIFT,
917 .mask = S5PC100_CLKSRC2_MMC1_MASK,
918 .sources = &clkset_mmc,
919 .divider_shift = S5PC100_CLKDIV3_MMC1_SHIFT,
920 .reg_divider = S5PC100_CLKDIV3,
921 .reg_source = S5PC100_CLKSRC2,
922};
923
924static struct clksrc_clk clk_mmc2 = {
925 .clk = {
926 .name = "mmc_bus",
927 .id = 2,
928 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
929 .enable = s5pc100_sclk0_ctrl,
930 .set_parent = s5pc100_setparent_clksrc,
931 .get_rate = s5pc100_getrate_clksrc,
932 .set_rate = s5pc100_setrate_clksrc,
933 .round_rate = s5pc100_roundrate_clksrc,
934 },
935 .shift = S5PC100_CLKSRC2_MMC2_SHIFT,
936 .mask = S5PC100_CLKSRC2_MMC2_MASK,
937 .sources = &clkset_mmc,
938 .divider_shift = S5PC100_CLKDIV3_MMC2_SHIFT,
939 .reg_divider = S5PC100_CLKDIV3,
940 .reg_source = S5PC100_CLKSRC2,
941};
942
943
944static struct clk *clkset_usbhost_list[] = { 606static struct clk *clkset_usbhost_list[] = {
945 &clk_mout_epll.clk, 607 &clk_mout_epll.clk,
946 &clk_dout_mpll, 608 &clk_dout_mpll,
@@ -948,28 +610,141 @@ static struct clk *clkset_usbhost_list[] = {
948 &clk_48m, 610 &clk_48m,
949}; 611};
950 612
951static struct clk_sources clkset_usbhost = { 613static struct clksrc_sources clkset_usbhost = {
952 .sources = clkset_usbhost_list, 614 .sources = clkset_usbhost_list,
953 .nr_sources = ARRAY_SIZE(clkset_usbhost_list), 615 .nr_sources = ARRAY_SIZE(clkset_usbhost_list),
954}; 616};
955 617
956static struct clksrc_clk clk_usbhost = { 618static struct clksrc_clk clksrc_clks[] = {
957 .clk = { 619 {
958 .name = "usbhost", 620 .clk = {
959 .id = -1, 621 .name = "spi_bus",
960 .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, 622 .id = 0,
961 .enable = s5pc100_sclk0_ctrl, 623 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0,
962 .set_parent = s5pc100_setparent_clksrc, 624 .enable = s5pc100_sclk0_ctrl,
963 .get_rate = s5pc100_getrate_clksrc, 625
964 .set_rate = s5pc100_setrate_clksrc, 626 },
965 .round_rate = s5pc100_roundrate_clksrc, 627 .sources = &clkset_spi,
966 }, 628 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, },
967 .shift = S5PC100_CLKSRC1_UHOST_SHIFT, 629 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, },
968 .mask = S5PC100_CLKSRC1_UHOST_MASK, 630 }, {
969 .sources = &clkset_usbhost, 631 .clk = {
970 .divider_shift = S5PC100_CLKDIV2_UHOST_SHIFT, 632 .name = "spi_bus",
971 .reg_divider = S5PC100_CLKDIV2, 633 .id = 1,
972 .reg_source = S5PC100_CLKSRC1, 634 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
635 .enable = s5pc100_sclk0_ctrl,
636 },
637 .sources = &clkset_spi,
638 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, },
639 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, },
640 }, {
641 .clk = {
642 .name = "spi_bus",
643 .id = 2,
644 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
645 .enable = s5pc100_sclk0_ctrl,
646 },
647 .sources = &clkset_spi,
648 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, },
649 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, },
650 }, {
651 .clk = {
652 .name = "uclk1",
653 .id = -1,
654 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
655 .enable = s5pc100_sclk0_ctrl,
656 },
657 .sources = &clkset_uart,
658 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, },
659 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, },
660 }, {
661 .clk = {
662 .name = "spdif",
663 .id = -1,
664 },
665 .sources = &clkset_spdif,
666 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, },
667 }, {
668 .clk = {
669 .name = "lcd",
670 .id = -1,
671 .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
672 .enable = s5pc100_sclk1_ctrl,
673 },
674 .sources = &clkset_lcd_fimc,
675 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, },
676 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, },
677 }, {
678 .clk = {
679 .name = "fimc",
680 .id = 0,
681 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
682 .enable = s5pc100_sclk1_ctrl,
683 },
684 .sources = &clkset_lcd_fimc,
685 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, },
686 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, },
687 }, {
688 .clk = {
689 .name = "fimc",
690 .id = 1,
691 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
692 .enable = s5pc100_sclk1_ctrl,
693 },
694 .sources = &clkset_lcd_fimc,
695 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, },
696 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, },
697 }, {
698 .clk = {
699 .name = "fimc",
700 .id = 2,
701 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
702 .enable = s5pc100_sclk1_ctrl,
703 },
704 .sources = &clkset_lcd_fimc,
705 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, },
706 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, },
707 }, {
708 .clk = {
709 .name = "mmc_bus",
710 .id = 0,
711 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
712 .enable = s5pc100_sclk0_ctrl,
713 },
714 .sources = &clkset_mmc,
715 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, },
716 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, },
717 }, {
718 .clk = {
719 .name = "mmc_bus",
720 .id = 1,
721 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
722 .enable = s5pc100_sclk0_ctrl,
723 },
724 .sources = &clkset_mmc,
725 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, },
726 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, },
727 }, {
728 .clk = {
729 .name = "mmc_bus",
730 .id = 2,
731 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
732 .enable = s5pc100_sclk0_ctrl,
733 },
734 .sources = &clkset_mmc,
735 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, },
736 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, },
737 }, {
738 .clk = {
739 .name = "usbhost",
740 .id = -1,
741 .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
742 .enable = s5pc100_sclk0_ctrl,
743 },
744 .sources = &clkset_usbhost,
745 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, },
746 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, },
747 }
973}; 748};
974 749
975/* Clock initialisation code */ 750/* Clock initialisation code */
@@ -981,45 +756,8 @@ static struct clksrc_clk *init_parents[] = {
981 &clk_mout_onenand, 756 &clk_mout_onenand,
982 &clk_mout_epll, 757 &clk_mout_epll,
983 &clk_mout_hpll, 758 &clk_mout_hpll,
984 &clk_spi0,
985 &clk_spi1,
986 &clk_spi2,
987 &clk_uart_uclk1,
988 &clk_audio0,
989 &clk_audio1,
990 &clk_audio2,
991 &clk_spdif,
992 &clk_lcd,
993 &clk_fimc0,
994 &clk_fimc1,
995 &clk_fimc2,
996 &clk_mmc0,
997 &clk_mmc1,
998 &clk_mmc2,
999 &clk_usbhost,
1000}; 759};
1001 760
1002static void __init_or_cpufreq s5pc100_set_clksrc(struct clksrc_clk *clk)
1003{
1004 struct clk_sources *srcs = clk->sources;
1005 u32 clksrc = __raw_readl(clk->reg_source);
1006
1007 clksrc &= clk->mask;
1008 clksrc >>= clk->shift;
1009
1010 if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
1011 printk(KERN_ERR "%s: bad source %d\n",
1012 clk->clk.name, clksrc);
1013 return;
1014 }
1015
1016 clk->clk.parent = srcs->sources[clksrc];
1017
1018 printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n",
1019 clk->clk.name, clk->clk.parent->name, clksrc,
1020 print_mhz(clk_get_rate(&clk->clk)));
1021}
1022
1023#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 761#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
1024 762
1025void __init_or_cpufreq s5pc100_setup_clocks(void) 763void __init_or_cpufreq s5pc100_setup_clocks(void)
@@ -1083,17 +821,25 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
1083 clk_f.rate = armclk; 821 clk_f.rate = armclk;
1084 822
1085 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) 823 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
1086 s5pc100_set_clksrc(init_parents[ptr]); 824 s3c_set_clksrc(init_parents[ptr], true);
825
826 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++)
827 s3c_set_clksrc(clksrc_audio + ptr, true);
828
829 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
830 s3c_set_clksrc(clksrc_clks + ptr, true);
1087} 831}
1088 832
1089static struct clk *clks[] __initdata = { 833static struct clk *clks[] __initdata = {
1090 &clk_ext_xtal_mux, 834 &clk_ext_xtal_mux,
1091 &clk_mout_apll.clk,
1092 &clk_dout_apll, 835 &clk_dout_apll,
1093 &clk_dout_d0_bus, 836 &clk_dout_d0_bus,
1094 &clk_dout_pclkd0, 837 &clk_dout_pclkd0,
1095 &clk_dout_apll2, 838 &clk_dout_apll2,
839 &clk_mout_apll.clk,
1096 &clk_mout_mpll.clk, 840 &clk_mout_mpll.clk,
841 &clk_mout_epll.clk,
842 &clk_mout_hpll.clk,
1097 &clk_mout_am.clk, 843 &clk_mout_am.clk,
1098 &clk_dout_d1_bus, 844 &clk_dout_d1_bus,
1099 &clk_mout_onenand.clk, 845 &clk_mout_onenand.clk,
@@ -1101,29 +847,12 @@ static struct clk *clks[] __initdata = {
1101 &clk_dout_mpll2, 847 &clk_dout_mpll2,
1102 &clk_dout_cam, 848 &clk_dout_cam,
1103 &clk_dout_mpll, 849 &clk_dout_mpll,
1104 &clk_mout_epll.clk,
1105 &clk_fout_epll, 850 &clk_fout_epll,
1106 &clk_iis_cd0, 851 &clk_iis_cd0,
1107 &clk_iis_cd1, 852 &clk_iis_cd1,
1108 &clk_iis_cd2, 853 &clk_iis_cd2,
1109 &clk_pcm_cd0, 854 &clk_pcm_cd0,
1110 &clk_pcm_cd1, 855 &clk_pcm_cd1,
1111 &clk_spi0.clk,
1112 &clk_spi1.clk,
1113 &clk_spi2.clk,
1114 &clk_uart_uclk1.clk,
1115 &clk_audio0.clk,
1116 &clk_audio1.clk,
1117 &clk_audio2.clk,
1118 &clk_spdif.clk,
1119 &clk_lcd.clk,
1120 &clk_fimc0.clk,
1121 &clk_fimc1.clk,
1122 &clk_fimc2.clk,
1123 &clk_mmc0.clk,
1124 &clk_mmc1.clk,
1125 &clk_mmc2.clk,
1126 &clk_usbhost.clk,
1127 &clk_arm, 856 &clk_arm,
1128}; 857};
1129 858
@@ -1141,4 +870,7 @@ void __init s5pc100_register_clocks(void)
1141 clkp->name, ret); 870 clkp->name, ret);
1142 } 871 }
1143 } 872 }
873
874 s3c_register_clksrc(clksrc_audio, ARRAY_SIZE(clksrc_audio));
875 s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
1144} 876}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 06:37:07 -0500