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-rw-r--r--arch/arm/plat-omap/include/plat/board.h9
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev_omap.h41
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h5
-rw-r--r--arch/arm/plat-omap/include/plat/common.h35
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h31
-rw-r--r--arch/arm/plat-omap/include/plat/dma.h60
-rw-r--r--arch/arm/plat-omap/include/plat/gpmc.h2
-rw-r--r--arch/arm/plat-omap/include/plat/i2c.h39
-rw-r--r--arch/arm/plat-omap/include/plat/mux.h232
-rw-r--r--arch/arm/plat-omap/include/plat/omap44xx.h6
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h8
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h26
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h17
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h1
-rw-r--r--arch/arm/plat-omap/include/plat/smp.h2
15 files changed, 189 insertions, 325 deletions
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index abb17b604f8..376ce18216f 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -114,15 +114,6 @@ struct omap_pwm_led_platform_data {
114 void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off); 114 void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
115}; 115};
116 116
117/* See arch/arm/plat-omap/include/mach/gpio-switch.h for definitions */
118struct omap_gpio_switch_config {
119 char name[12];
120 u16 gpio;
121 int flags:4;
122 int type:4;
123 int key_code:24; /* Linux key code */
124};
125
126struct omap_uart_config { 117struct omap_uart_config {
127 /* Bit field of UARTs present; bit 0 --> UART1 */ 118 /* Bit field of UARTs present; bit 0 --> UART1 */
128 unsigned int enabled_uarts; 119 unsigned int enabled_uarts;
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
new file mode 100644
index 00000000000..35b36caf5f9
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -0,0 +1,41 @@
1/*
2 * clkdev <-> OMAP integration
3 *
4 * Russell King <linux@arm.linux.org.uk>
5 *
6 */
7
8#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
9#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
10
11#include <asm/clkdev.h>
12
13struct omap_clk {
14 u16 cpu;
15 struct clk_lookup lk;
16};
17
18#define CLK(dev, con, ck, cp) \
19 { \
20 .cpu = cp, \
21 .lk = { \
22 .dev_id = dev, \
23 .con_id = con, \
24 .clk = ck, \
25 }, \
26 }
27
28
29#define CK_310 (1 << 0)
30#define CK_7XX (1 << 1)
31#define CK_1510 (1 << 2)
32#define CK_16XX (1 << 3)
33#define CK_243X (1 << 4)
34#define CK_242X (1 << 5)
35#define CK_343X (1 << 6)
36#define CK_3430ES1 (1 << 7)
37#define CK_3430ES2 (1 << 8)
38#define CK_443X (1 << 9)
39
40#endif
41
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 4b8b0d65cbf..309b6d1dccd 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -13,6 +13,8 @@
13#ifndef __ARCH_ARM_OMAP_CLOCK_H 13#ifndef __ARCH_ARM_OMAP_CLOCK_H
14#define __ARCH_ARM_OMAP_CLOCK_H 14#define __ARCH_ARM_OMAP_CLOCK_H
15 15
16#include <linux/list.h>
17
16struct module; 18struct module;
17struct clk; 19struct clk;
18struct clockdomain; 20struct clockdomain;
@@ -148,6 +150,8 @@ extern const struct clkops clkops_null;
148#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ 150#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
149#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ 151#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
150#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ 152#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
153#define CLOCK_IN_OMAP4430 (1 << 13)
154#define ALWAYS_ENABLED (1 << 14)
151/* bits 13-31 are currently free */ 155/* bits 13-31 are currently free */
152 156
153/* Clksel_rate flags */ 157/* Clksel_rate flags */
@@ -156,6 +160,7 @@ extern const struct clkops clkops_null;
156#define RATE_IN_243X (1 << 2) 160#define RATE_IN_243X (1 << 2)
157#define RATE_IN_343X (1 << 3) /* rates common to all 343X */ 161#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
158#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */ 162#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
163#define RATE_IN_4430 (1 << 5)
159 164
160#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 165#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
161 166
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 064f1730f43..32c22272425 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -27,7 +27,7 @@
27#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H 27#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
28#define __ARCH_ARM_MACH_OMAP_COMMON_H 28#define __ARCH_ARM_MACH_OMAP_COMMON_H
29 29
30#include <linux/i2c.h> 30#include <plat/i2c.h>
31 31
32struct sys_timer; 32struct sys_timer;
33 33
@@ -36,18 +36,6 @@ extern void __iomem *gic_cpu_base_addr;
36 36
37extern void omap_map_common_io(void); 37extern void omap_map_common_io(void);
38extern struct sys_timer omap_timer; 38extern struct sys_timer omap_timer;
39#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
40extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
41 struct i2c_board_info const *info,
42 unsigned len);
43#else
44static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
45 struct i2c_board_info const *info,
46 unsigned len)
47{
48 return 0;
49}
50#endif
51 39
52/* IO bases for various OMAP processors */ 40/* IO bases for various OMAP processors */
53struct omap_globals { 41struct omap_globals {
@@ -58,6 +46,7 @@ struct omap_globals {
58 void __iomem *ctrl; /* System Control Module */ 46 void __iomem *ctrl; /* System Control Module */
59 void __iomem *prm; /* Power and Reset Management */ 47 void __iomem *prm; /* Power and Reset Management */
60 void __iomem *cm; /* Clock Management */ 48 void __iomem *cm; /* Clock Management */
49 void __iomem *cm2;
61}; 50};
62 51
63void omap2_set_globals_242x(void); 52void omap2_set_globals_242x(void);
@@ -71,4 +60,24 @@ void omap2_set_globals_sdrc(struct omap_globals *);
71void omap2_set_globals_control(struct omap_globals *); 60void omap2_set_globals_control(struct omap_globals *);
72void omap2_set_globals_prcm(struct omap_globals *); 61void omap2_set_globals_prcm(struct omap_globals *);
73 62
63/**
64 * omap_test_timeout - busy-loop, testing a condition
65 * @cond: condition to test until it evaluates to true
66 * @timeout: maximum number of microseconds in the timeout
67 * @index: loop index (integer)
68 *
69 * Loop waiting for @cond to become true or until at least @timeout
70 * microseconds have passed. To use, define some integer @index in the
71 * calling code. After running, if @index == @timeout, then the loop has
72 * timed out.
73 */
74#define omap_test_timeout(cond, timeout, index) \
75({ \
76 for (index = 0; index < timeout; index++) { \
77 if (cond) \
78 break; \
79 udelay(1); \
80 } \
81})
82
74#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ 83#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 2e1789001df..9a028bdebb0 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -176,11 +176,13 @@ IS_OMAP_CLASS(15xx, 0x15)
176IS_OMAP_CLASS(16xx, 0x16) 176IS_OMAP_CLASS(16xx, 0x16)
177IS_OMAP_CLASS(24xx, 0x24) 177IS_OMAP_CLASS(24xx, 0x24)
178IS_OMAP_CLASS(34xx, 0x34) 178IS_OMAP_CLASS(34xx, 0x34)
179IS_OMAP_CLASS(44xx, 0x44)
179 180
180IS_OMAP_SUBCLASS(242x, 0x242) 181IS_OMAP_SUBCLASS(242x, 0x242)
181IS_OMAP_SUBCLASS(243x, 0x243) 182IS_OMAP_SUBCLASS(243x, 0x243)
182IS_OMAP_SUBCLASS(343x, 0x343) 183IS_OMAP_SUBCLASS(343x, 0x343)
183IS_OMAP_SUBCLASS(363x, 0x363) 184IS_OMAP_SUBCLASS(363x, 0x363)
185IS_OMAP_SUBCLASS(443x, 0x443)
184 186
185#define cpu_is_omap7xx() 0 187#define cpu_is_omap7xx() 0
186#define cpu_is_omap15xx() 0 188#define cpu_is_omap15xx() 0
@@ -393,11 +395,11 @@ IS_OMAP_TYPE(3517, 0x3517)
393 (!omap3_has_iva()) && \ 395 (!omap3_has_iva()) && \
394 (!omap3_has_sgx())) 396 (!omap3_has_sgx()))
395# define cpu_is_omap3515() (cpu_is_omap3430() && \ 397# define cpu_is_omap3515() (cpu_is_omap3430() && \
396 (omap3_has_iva()) && \ 398 (!omap3_has_iva()) && \
397 (!omap3_has_sgx())) 399 (omap3_has_sgx()))
398# define cpu_is_omap3525() (cpu_is_omap3430() && \ 400# define cpu_is_omap3525() (cpu_is_omap3430() && \
399 (omap3_has_sgx()) && \ 401 (!omap3_has_sgx()) && \
400 (!omap3_has_iva())) 402 (omap3_has_iva()))
401# define cpu_is_omap3530() (cpu_is_omap3430()) 403# define cpu_is_omap3530() (cpu_is_omap3430())
402# define cpu_is_omap3505() is_omap3505() 404# define cpu_is_omap3505() is_omap3505()
403# define cpu_is_omap3517() is_omap3517() 405# define cpu_is_omap3517() is_omap3517()
@@ -408,8 +410,8 @@ IS_OMAP_TYPE(3517, 0x3517)
408# if defined(CONFIG_ARCH_OMAP4) 410# if defined(CONFIG_ARCH_OMAP4)
409# undef cpu_is_omap44xx 411# undef cpu_is_omap44xx
410# undef cpu_is_omap443x 412# undef cpu_is_omap443x
411# define cpu_is_omap44xx() 1 413# define cpu_is_omap44xx() is_omap44xx()
412# define cpu_is_omap443x() 1 414# define cpu_is_omap443x() is_omap443x()
413# endif 415# endif
414 416
415/* Macros to detect if we have OMAP1 or OMAP2 */ 417/* Macros to detect if we have OMAP1 or OMAP2 */
@@ -436,14 +438,15 @@ IS_OMAP_TYPE(3517, 0x3517)
436#define OMAP3630_REV_ES1_0 0x36300034 438#define OMAP3630_REV_ES1_0 0x36300034
437 439
438#define OMAP35XX_CLASS 0x35000034 440#define OMAP35XX_CLASS 0x35000034
439#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 12)) 441#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
440#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 12)) 442#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
441#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 12)) 443#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
442#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 12)) 444#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
443#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 12)) 445#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
444#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 12)) 446#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
445 447
446#define OMAP443X_CLASS 0x44300034 448#define OMAP443X_CLASS 0x44300044
449#define OMAP4430_REV_ES1_0 0x44300044
447 450
448/* 451/*
449 * omap_chip bits 452 * omap_chip bits
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 1c017b29b7e..4ede9e17a0b 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -401,33 +401,6 @@
401 401
402/*----------------------------------------------------------------------------*/ 402/*----------------------------------------------------------------------------*/
403 403
404/* Hardware registers for LCD DMA */
405#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
406#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
407#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
408#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
409#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
410#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
411
412#define OMAP1610_DMA_LCD_BASE (0xfffee300)
413#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
414#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
415#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
416#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
417#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
418#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
419#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
420#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
421#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
422#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
423#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
424#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
425#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
426#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
427#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
428#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
429#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
430
431#define OMAP1_DMA_TOUT_IRQ (1 << 0) 404#define OMAP1_DMA_TOUT_IRQ (1 << 0)
432#define OMAP_DMA_DROP_IRQ (1 << 1) 405#define OMAP_DMA_DROP_IRQ (1 << 1)
433#define OMAP_DMA_HALF_IRQ (1 << 2) 406#define OMAP_DMA_HALF_IRQ (1 << 2)
@@ -441,6 +414,8 @@
441#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10) 414#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
442#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) 415#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
443 416
417#define OMAP_DMA_CCR_EN (1 << 7)
418
444#define OMAP_DMA_DATA_TYPE_S8 0x00 419#define OMAP_DMA_DATA_TYPE_S8 0x00
445#define OMAP_DMA_DATA_TYPE_S16 0x01 420#define OMAP_DMA_DATA_TYPE_S16 0x01
446#define OMAP_DMA_DATA_TYPE_S32 0x02 421#define OMAP_DMA_DATA_TYPE_S32 0x02
@@ -503,14 +478,6 @@
503#define DMA_CH_PRIO_HIGH 0x1 478#define DMA_CH_PRIO_HIGH 0x1
504#define DMA_CH_PRIO_LOW 0x0 /* Def */ 479#define DMA_CH_PRIO_LOW 0x0 /* Def */
505 480
506/* LCD DMA block numbers */
507enum {
508 OMAP_LCD_DMA_B1_TOP,
509 OMAP_LCD_DMA_B1_BOTTOM,
510 OMAP_LCD_DMA_B2_TOP,
511 OMAP_LCD_DMA_B2_BOTTOM
512};
513
514enum omap_dma_burst_mode { 481enum omap_dma_burst_mode {
515 OMAP_DMA_DATA_BURST_DIS = 0, 482 OMAP_DMA_DATA_BURST_DIS = 0,
516 OMAP_DMA_DATA_BURST_4, 483 OMAP_DMA_DATA_BURST_4,
@@ -661,20 +628,13 @@ extern int omap_modify_dma_chain_params(int chain_id,
661extern int omap_dma_chain_status(int chain_id); 628extern int omap_dma_chain_status(int chain_id);
662#endif 629#endif
663 630
664/* LCD DMA functions */ 631#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
665extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), 632#include <mach/lcd_dma.h>
666 void *data); 633#else
667extern void omap_free_lcd_dma(void); 634static inline int omap_lcd_dma_running(void)
668extern void omap_setup_lcd_dma(void); 635{
669extern void omap_enable_lcd_dma(void); 636 return 0;
670extern void omap_stop_lcd_dma(void); 637}
671extern void omap_set_lcd_dma_ext_controller(int external); 638#endif
672extern void omap_set_lcd_dma_single_transfer(int single);
673extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
674 int data_type);
675extern void omap_set_lcd_dma_b1_rotation(int rotate);
676extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
677extern void omap_set_lcd_dma_b1_mirror(int mirror);
678extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
679 639
680#endif /* __ASM_ARCH_DMA_H */ 640#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 696e0ca051b..e081338e0b2 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -45,7 +45,7 @@
45#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) 45#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
46#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) 46#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
47#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) 47#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
48#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1) 48#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2)
49#define GPMC_CONFIG1_MUXADDDATA (1 << 9) 49#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
50#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) 50#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
51#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) 51#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
new file mode 100644
index 00000000000..585d9ca68b9
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -0,0 +1,39 @@
1/*
2 * Helper module for board specific I2C bus registration
3 *
4 * Copyright (C) 2009 Nokia Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/i2c.h>
23
24#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
25extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
26 struct i2c_board_info const *info,
27 unsigned len);
28#else
29static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
30 struct i2c_board_info const *info,
31 unsigned len)
32{
33 return 0;
34}
35#endif
36
37int omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
38 struct i2c_board_info const *info,
39 unsigned len);
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index ba77de60150..8f069cc8035 100644
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -130,58 +130,11 @@
130#define OMAP2_PULL_UP (1 << 4) 130#define OMAP2_PULL_UP (1 << 4)
131#define OMAP2_ALTELECTRICALSEL (1 << 5) 131#define OMAP2_ALTELECTRICALSEL (1 << 5)
132 132
133/* 34xx specific mux bit defines */
134#define OMAP3_INPUT_EN (1 << 8)
135#define OMAP3_OFF_EN (1 << 9)
136#define OMAP3_OFFOUT_EN (1 << 10)
137#define OMAP3_OFFOUT_VAL (1 << 11)
138#define OMAP3_OFF_PULL_EN (1 << 12)
139#define OMAP3_OFF_PULL_UP (1 << 13)
140#define OMAP3_WAKEUP_EN (1 << 14)
141
142/* 34xx mux mode options for each pin. See TRM for options */
143#define OMAP34XX_MUX_MODE0 0
144#define OMAP34XX_MUX_MODE1 1
145#define OMAP34XX_MUX_MODE2 2
146#define OMAP34XX_MUX_MODE3 3
147#define OMAP34XX_MUX_MODE4 4
148#define OMAP34XX_MUX_MODE5 5
149#define OMAP34XX_MUX_MODE6 6
150#define OMAP34XX_MUX_MODE7 7
151
152/* 34xx active pin states */
153#define OMAP34XX_PIN_OUTPUT 0
154#define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
155#define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
156 | OMAP2_PULL_UP)
157#define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
158
159/* 34xx off mode states */
160#define OMAP34XX_PIN_OFF_NONE 0
161#define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
162 | OMAP3_OFFOUT_VAL)
163#define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
164#define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
165 | OMAP3_OFF_PULL_UP)
166#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
167#define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
168
169#define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
170 .name = desc, \
171 .debug = 0, \
172 .mux_reg = reg_offset, \
173 .mux_val = mux_value \
174},
175
176struct pin_config { 133struct pin_config {
177 char *name; 134 char *name;
178 const unsigned int mux_reg; 135 const unsigned int mux_reg;
179 unsigned char debug; 136 unsigned char debug;
180 137
181#if defined(CONFIG_ARCH_OMAP34XX)
182 u16 mux_val; /* Wake-up, off mode, pull, mux mode */
183#endif
184
185#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX) 138#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
186 const unsigned char mask_offset; 139 const unsigned char mask_offset;
187 const unsigned char mask; 140 const unsigned char mask;
@@ -219,11 +172,17 @@ enum omap7xx_index {
219 AA17_7XX_USB_DM, 172 AA17_7XX_USB_DM,
220 W16_7XX_USB_PU_EN, 173 W16_7XX_USB_PU_EN,
221 W17_7XX_USB_VBUSI, 174 W17_7XX_USB_VBUSI,
175 W18_7XX_USB_DMCK_OUT,
176 W19_7XX_USB_DCRST,
222 177
223 /* MMC */ 178 /* MMC */
224 MMC_7XX_CMD, 179 MMC_7XX_CMD,
225 MMC_7XX_CLK, 180 MMC_7XX_CLK,
226 MMC_7XX_DAT0, 181 MMC_7XX_DAT0,
182
183 /* I2C */
184 I2C_7XX_SCL,
185 I2C_7XX_SDA,
227}; 186};
228 187
229enum omap1xxx_index { 188enum omap1xxx_index {
@@ -681,181 +640,6 @@ enum omap24xx_index {
681 640
682}; 641};
683 642
684enum omap34xx_index {
685 /* 34xx I2C */
686 K21_34XX_I2C1_SCL,
687 J21_34XX_I2C1_SDA,
688 AF15_34XX_I2C2_SCL,
689 AE15_34XX_I2C2_SDA,
690 AF14_34XX_I2C3_SCL,
691 AG14_34XX_I2C3_SDA,
692 AD26_34XX_I2C4_SCL,
693 AE26_34XX_I2C4_SDA,
694
695 /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
696 Y8_3430_USB1HS_PHY_CLK,
697 Y9_3430_USB1HS_PHY_STP,
698 AA14_3430_USB1HS_PHY_DIR,
699 AA11_3430_USB1HS_PHY_NXT,
700 W13_3430_USB1HS_PHY_DATA0,
701 W12_3430_USB1HS_PHY_DATA1,
702 W11_3430_USB1HS_PHY_DATA2,
703 Y11_3430_USB1HS_PHY_DATA3,
704 W9_3430_USB1HS_PHY_DATA4,
705 Y12_3430_USB1HS_PHY_DATA5,
706 W8_3430_USB1HS_PHY_DATA6,
707 Y13_3430_USB1HS_PHY_DATA7,
708
709 /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
710 AA8_3430_USB2HS_PHY_CLK,
711 AA10_3430_USB2HS_PHY_STP,
712 AA9_3430_USB2HS_PHY_DIR,
713 AB11_3430_USB2HS_PHY_NXT,
714 AB10_3430_USB2HS_PHY_DATA0,
715 AB9_3430_USB2HS_PHY_DATA1,
716 W3_3430_USB2HS_PHY_DATA2,
717 T4_3430_USB2HS_PHY_DATA3,
718 T3_3430_USB2HS_PHY_DATA4,
719 R3_3430_USB2HS_PHY_DATA5,
720 R4_3430_USB2HS_PHY_DATA6,
721 T2_3430_USB2HS_PHY_DATA7,
722
723
724 /* TLL - HSUSB: 12-pin TLL Port 1*/
725 Y8_3430_USB1HS_TLL_CLK,
726 Y9_3430_USB1HS_TLL_STP,
727 AA14_3430_USB1HS_TLL_DIR,
728 AA11_3430_USB1HS_TLL_NXT,
729 W13_3430_USB1HS_TLL_DATA0,
730 W12_3430_USB1HS_TLL_DATA1,
731 W11_3430_USB1HS_TLL_DATA2,
732 Y11_3430_USB1HS_TLL_DATA3,
733 W9_3430_USB1HS_TLL_DATA4,
734 Y12_3430_USB1HS_TLL_DATA5,
735 W8_3430_USB1HS_TLL_DATA6,
736 Y13_3430_USB1HS_TLL_DATA7,
737
738 /* TLL - HSUSB: 12-pin TLL Port 2*/
739 AA8_3430_USB2HS_TLL_CLK,
740 AA10_3430_USB2HS_TLL_STP,
741 AA9_3430_USB2HS_TLL_DIR,
742 AB11_3430_USB2HS_TLL_NXT,
743 AB10_3430_USB2HS_TLL_DATA0,
744 AB9_3430_USB2HS_TLL_DATA1,
745 W3_3430_USB2HS_TLL_DATA2,
746 T4_3430_USB2HS_TLL_DATA3,
747 T3_3430_USB2HS_TLL_DATA4,
748 R3_3430_USB2HS_TLL_DATA5,
749 R4_3430_USB2HS_TLL_DATA6,
750 T2_3430_USB2HS_TLL_DATA7,
751
752 /* TLL - HSUSB: 12-pin TLL Port 3*/
753 AA6_3430_USB3HS_TLL_CLK,
754 AB3_3430_USB3HS_TLL_STP,
755 AA3_3430_USB3HS_TLL_DIR,
756 Y3_3430_USB3HS_TLL_NXT,
757 AA5_3430_USB3HS_TLL_DATA0,
758 Y4_3430_USB3HS_TLL_DATA1,
759 Y5_3430_USB3HS_TLL_DATA2,
760 W5_3430_USB3HS_TLL_DATA3,
761 AB12_3430_USB3HS_TLL_DATA4,
762 AB13_3430_USB3HS_TLL_DATA5,
763 AA13_3430_USB3HS_TLL_DATA6,
764 AA12_3430_USB3HS_TLL_DATA7,
765
766 /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
767 AF10_3430_USB1FS_PHY_MM1_RXDP,
768 AG9_3430_USB1FS_PHY_MM1_RXDM,
769 W13_3430_USB1FS_PHY_MM1_RXRCV,
770 W12_3430_USB1FS_PHY_MM1_TXSE0,
771 W11_3430_USB1FS_PHY_MM1_TXDAT,
772 Y11_3430_USB1FS_PHY_MM1_TXEN_N,
773
774 /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
775 AF7_3430_USB2FS_PHY_MM2_RXDP,
776 AH7_3430_USB2FS_PHY_MM2_RXDM,
777 AB10_3430_USB2FS_PHY_MM2_RXRCV,
778 AB9_3430_USB2FS_PHY_MM2_TXSE0,
779 W3_3430_USB2FS_PHY_MM2_TXDAT,
780 T4_3430_USB2FS_PHY_MM2_TXEN_N,
781
782 /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
783 AH3_3430_USB3FS_PHY_MM3_RXDP,
784 AE3_3430_USB3FS_PHY_MM3_RXDM,
785 AD1_3430_USB3FS_PHY_MM3_RXRCV,
786 AE1_3430_USB3FS_PHY_MM3_TXSE0,
787 AD2_3430_USB3FS_PHY_MM3_TXDAT,
788 AC1_3430_USB3FS_PHY_MM3_TXEN_N,
789
790 /* 34xx GPIO
791 * - normally these are bidirectional, no internal pullup/pulldown
792 * - "_UP" suffix (GPIO3_UP) if internal pullup is configured
793 * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
794 * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
795 */
796 AF26_34XX_GPIO0,
797 AF22_34XX_GPIO9,
798 AG9_34XX_GPIO23,
799 AH8_34XX_GPIO29,
800 U8_34XX_GPIO54_OUT,
801 U8_34XX_GPIO54_DOWN,
802 L8_34XX_GPIO63,
803 G25_34XX_GPIO86_OUT,
804 AG4_34XX_GPIO134_OUT,
805 AF4_34XX_GPIO135_OUT,
806 AE4_34XX_GPIO136_OUT,
807 AF6_34XX_GPIO140_UP,
808 AE6_34XX_GPIO141,
809 AF5_34XX_GPIO142,
810 AE5_34XX_GPIO143,
811 H19_34XX_GPIO164_OUT,
812 J25_34XX_GPIO170,
813
814 /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
815 H16_34XX_SDRC_CKE0,
816 H17_34XX_SDRC_CKE1,
817
818 /* MMC1 */
819 N28_3430_MMC1_CLK,
820 M27_3430_MMC1_CMD,
821 N27_3430_MMC1_DAT0,
822 N26_3430_MMC1_DAT1,
823 N25_3430_MMC1_DAT2,
824 P28_3430_MMC1_DAT3,
825 P27_3430_MMC1_DAT4,
826 P26_3430_MMC1_DAT5,
827 R27_3430_MMC1_DAT6,
828 R25_3430_MMC1_DAT7,
829
830 /* MMC2 */
831 AE2_3430_MMC2_CLK,
832 AG5_3430_MMC2_CMD,
833 AH5_3430_MMC2_DAT0,
834 AH4_3430_MMC2_DAT1,
835 AG4_3430_MMC2_DAT2,
836 AF4_3430_MMC2_DAT3,
837 AE4_3430_MMC2_DAT4,
838 AH3_3430_MMC2_DAT5,
839 AF3_3430_MMC2_DAT6,
840 AE3_3430_MMC2_DAT7,
841
842 /* MMC3 */
843 AF10_3430_MMC3_CLK,
844 AC3_3430_MMC3_CMD,
845 AE11_3430_MMC3_DAT0,
846 AH9_3430_MMC3_DAT1,
847 AF13_3430_MMC3_DAT2,
848 AF13_3430_MMC3_DAT3,
849
850 /* SYS_NIRQ T2 INT1 */
851 AF26_34XX_SYS_NIRQ,
852
853 /* EHCI GPIO's for OMAP3EVM (Rev >= E) */
854 AH14_34XX_GPIO21,
855 AF9_34XX_GPIO22,
856 U3_34XX_GPIO61,
857};
858
859struct omap_mux_cfg { 643struct omap_mux_cfg {
860 struct pin_config *pins; 644 struct pin_config *pins;
861 unsigned long size; 645 unsigned long size;
@@ -865,14 +649,14 @@ struct omap_mux_cfg {
865#ifdef CONFIG_OMAP_MUX 649#ifdef CONFIG_OMAP_MUX
866/* setup pin muxing in Linux */ 650/* setup pin muxing in Linux */
867extern int omap1_mux_init(void); 651extern int omap1_mux_init(void);
868extern int omap2_mux_init(void);
869extern int omap_mux_register(struct omap_mux_cfg *); 652extern int omap_mux_register(struct omap_mux_cfg *);
870extern int omap_cfg_reg(unsigned long reg_cfg); 653extern int omap_cfg_reg(unsigned long reg_cfg);
871#else 654#else
872/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */ 655/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
873static inline int omap1_mux_init(void) { return 0; } 656static inline int omap1_mux_init(void) { return 0; }
874static inline int omap2_mux_init(void) { return 0; }
875static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; } 657static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
876#endif 658#endif
877 659
660extern int omap2_mux_init(void);
661
878#endif 662#endif
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index e52902a15c1..ef870de43c2 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -26,8 +26,10 @@
26#define OMAP44XX_EMIF2_BASE 0x4d000000 26#define OMAP44XX_EMIF2_BASE 0x4d000000
27#define OMAP44XX_DMM_BASE 0x4e000000 27#define OMAP44XX_DMM_BASE 0x4e000000
28#define OMAP4430_32KSYNCT_BASE 0x4a304000 28#define OMAP4430_32KSYNCT_BASE 0x4a304000
29#define OMAP4430_CM_BASE 0x4a004000 29#define OMAP4430_CM1_BASE 0x4a004000
30#define OMAP4430_PRM_BASE 0x48306000 30#define OMAP4430_CM_BASE OMAP4430_CM1_BASE
31#define OMAP4430_CM2_BASE 0x4a008000
32#define OMAP4430_PRM_BASE 0x4a306000
31#define OMAP44XX_GPMC_BASE 0x50000000 33#define OMAP44XX_GPMC_BASE 0x50000000
32#define OMAP443X_SCM_BASE 0x4a002000 34#define OMAP443X_SCM_BASE 0x4a002000
33#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE 35#define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 11a9773a4e7..dc1fac1d805 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -50,8 +50,8 @@
50 * @pm_lats: ptr to an omap_device_pm_latency table 50 * @pm_lats: ptr to an omap_device_pm_latency table
51 * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats 51 * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
52 * @pm_lat_level: array index of the last odpl entry executed - -1 if never 52 * @pm_lat_level: array index of the last odpl entry executed - -1 if never
53 * @dev_wakeup_lat: dev wakeup latency in microseconds 53 * @dev_wakeup_lat: dev wakeup latency in nanoseconds
54 * @_dev_wakeup_lat_limit: dev wakeup latency limit in usec - set by OMAP PM 54 * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
55 * @_state: one of OMAP_DEVICE_STATE_* (see above) 55 * @_state: one of OMAP_DEVICE_STATE_* (see above)
56 * @flags: device flags 56 * @flags: device flags
57 * 57 *
@@ -137,5 +137,7 @@ struct omap_device_pm_latency {
137}; 137};
138 138
139 139
140#endif 140/* Get omap_device pointer from platform_device pointer */
141#define to_omap_device(x) container_of((x), struct omap_device, pdev)
141 142
143#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index dbdd123eca1..007935a921e 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -50,6 +50,8 @@ struct omap_device;
50#define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) 50#define SYSC_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
51#define SYSC_SOFTRESET_SHIFT 1 51#define SYSC_SOFTRESET_SHIFT 1
52#define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) 52#define SYSC_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
53#define SYSC_AUTOIDLE_SHIFT 0
54#define SYSC_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT)
53 55
54/* OCP SYSSTATUS bit shifts/masks */ 56/* OCP SYSSTATUS bit shifts/masks */
55#define SYSS_RESETDONE_SHIFT 0 57#define SYSS_RESETDONE_SHIFT 0
@@ -62,7 +64,21 @@ struct omap_device;
62 64
63 65
64/** 66/**
65 * struct omap_hwmod_dma_info - MPU address space handled by the hwmod 67 * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
68 * @name: name of the IRQ channel (module local name)
69 * @irq_ch: IRQ channel ID
70 *
71 * @name should be something short, e.g., "tx" or "rx". It is for use
72 * by platform_get_resource_byname(). It is defined locally to the
73 * hwmod.
74 */
75struct omap_hwmod_irq_info {
76 const char *name;
77 u16 irq;
78};
79
80/**
81 * struct omap_hwmod_dma_info - DMA channels used by the hwmod
66 * @name: name of the DMA channel (module local name) 82 * @name: name of the DMA channel (module local name)
67 * @dma_ch: DMA channel ID 83 * @dma_ch: DMA channel ID
68 * 84 *
@@ -294,13 +310,17 @@ struct omap_hwmod_omap4_prcm {
294 * SDRAM controller, etc. 310 * SDRAM controller, etc.
295 * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM 311 * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
296 * controller, etc. 312 * controller, etc.
313 * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
314 * when module is enabled, rather than the default, which is to
315 * enable autoidle
297 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup 316 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
298 */ 317 */
299#define HWMOD_SWSUP_SIDLE (1 << 0) 318#define HWMOD_SWSUP_SIDLE (1 << 0)
300#define HWMOD_SWSUP_MSTANDBY (1 << 1) 319#define HWMOD_SWSUP_MSTANDBY (1 << 1)
301#define HWMOD_INIT_NO_RESET (1 << 2) 320#define HWMOD_INIT_NO_RESET (1 << 2)
302#define HWMOD_INIT_NO_IDLE (1 << 3) 321#define HWMOD_INIT_NO_IDLE (1 << 3)
303#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 4) 322#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
323#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
304 324
305/* 325/*
306 * omap_hwmod._int_flags definitions 326 * omap_hwmod._int_flags definitions
@@ -373,7 +393,7 @@ struct omap_hwmod_omap4_prcm {
373struct omap_hwmod { 393struct omap_hwmod {
374 const char *name; 394 const char *name;
375 struct omap_device *od; 395 struct omap_device *od;
376 u8 *mpu_irqs; 396 struct omap_hwmod_irq_info *mpu_irqs;
377 struct omap_hwmod_dma_info *sdma_chs; 397 struct omap_hwmod_dma_info *sdma_chs;
378 union { 398 union {
379 struct omap_hwmod_omap2_prcm omap2; 399 struct omap_hwmod_omap2_prcm omap2;
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index 3d45ee1d3cf..0b960051eae 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -28,6 +28,8 @@
28#define PWRDM_POWER_INACTIVE 0x2 28#define PWRDM_POWER_INACTIVE 0x2
29#define PWRDM_POWER_ON 0x3 29#define PWRDM_POWER_ON 0x3
30 30
31#define PWRDM_MAX_PWRSTS 4
32
31/* Powerdomain allowable state bitfields */ 33/* Powerdomain allowable state bitfields */
32#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ 34#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
33 (1 << PWRDM_POWER_ON)) 35 (1 << PWRDM_POWER_ON))
@@ -40,7 +42,10 @@
40 42
41/* Powerdomain flags */ 43/* Powerdomain flags */
42#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ 44#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
43 45#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
46 * in MEM bank 1 position. This is
47 * true for OMAP3430
48 */
44 49
45/* 50/*
46 * Number of memory banks that are power-controllable. On OMAP3430, the 51 * Number of memory banks that are power-controllable. On OMAP3430, the
@@ -85,15 +90,15 @@ struct powerdomain {
85 /* Used to represent the OMAP chip types containing this pwrdm */ 90 /* Used to represent the OMAP chip types containing this pwrdm */
86 const struct omap_chip_id omap_chip; 91 const struct omap_chip_id omap_chip;
87 92
88 /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
89 const u8 dep_bit;
90
91 /* Powerdomains that can be told to wake this powerdomain up */ 93 /* Powerdomains that can be told to wake this powerdomain up */
92 struct pwrdm_dep *wkdep_srcs; 94 struct pwrdm_dep *wkdep_srcs;
93 95
94 /* Powerdomains that can be told to keep this pwrdm from inactivity */ 96 /* Powerdomains that can be told to keep this pwrdm from inactivity */
95 struct pwrdm_dep *sleepdep_srcs; 97 struct pwrdm_dep *sleepdep_srcs;
96 98
99 /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
100 const u8 dep_bit;
101
97 /* Possible powerdomain power states */ 102 /* Possible powerdomain power states */
98 const u8 pwrsts; 103 const u8 pwrsts;
99 104
@@ -118,11 +123,11 @@ struct powerdomain {
118 struct list_head node; 123 struct list_head node;
119 124
120 int state; 125 int state;
121 unsigned state_counter[4]; 126 unsigned state_counter[PWRDM_MAX_PWRSTS];
122 127
123#ifdef CONFIG_PM_DEBUG 128#ifdef CONFIG_PM_DEBUG
124 s64 timer; 129 s64 timer;
125 s64 state_timer[4]; 130 s64 state_timer[PWRDM_MAX_PWRSTS];
126#endif 131#endif
127}; 132};
128 133
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 9951345a25d..f5a4a92393e 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -53,6 +53,7 @@
53#ifndef __ASSEMBLER__ 53#ifndef __ASSEMBLER__
54extern void __init omap_serial_early_init(void); 54extern void __init omap_serial_early_init(void);
55extern void omap_serial_init(void); 55extern void omap_serial_init(void);
56extern void omap_serial_init_port(int port);
56extern int omap_uart_can_sleep(void); 57extern int omap_uart_can_sleep(void);
57extern void omap_uart_check_wakeup(void); 58extern void omap_uart_check_wakeup(void);
58extern void omap_uart_prepare_suspend(void); 59extern void omap_uart_prepare_suspend(void);
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index dcaa8fde706..8983d54c4fd 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -28,6 +28,8 @@
28 28
29/* Needed for secondary core boot */ 29/* Needed for secondary core boot */
30extern void omap_secondary_startup(void); 30extern void omap_secondary_startup(void);
31extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
32extern void omap_auxcoreboot_addr(u32 cpu_addr);
31 33
32/* 34/*
33 * We use Soft IRQ1 as the IPI 35 * We use Soft IRQ1 as the IPI
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 04:49:55 -0500