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Diffstat (limited to 'arch/arm/plat-omap/include/mach/irqs.h')
-rw-r--r--arch/arm/plat-omap/include/mach/irqs.h59
1 files changed, 59 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index 62aa7dfb946..a2929ac8c68 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -125,6 +125,7 @@
125#define INT_UART2 (15 + IH2_BASE) 125#define INT_UART2 (15 + IH2_BASE)
126#define INT_BT_MCSI1TX (16 + IH2_BASE) 126#define INT_BT_MCSI1TX (16 + IH2_BASE)
127#define INT_BT_MCSI1RX (17 + IH2_BASE) 127#define INT_BT_MCSI1RX (17 + IH2_BASE)
128#define INT_SOSSI_MATCH (19 + IH2_BASE)
128#define INT_USB_W2FC (20 + IH2_BASE) 129#define INT_USB_W2FC (20 + IH2_BASE)
129#define INT_1WIRE (21 + IH2_BASE) 130#define INT_1WIRE (21 + IH2_BASE)
130#define INT_OS_TIMER (22 + IH2_BASE) 131#define INT_OS_TIMER (22 + IH2_BASE)
@@ -176,6 +177,7 @@
176#define INT_1610_DMA_CH14 (61 + IH2_BASE) 177#define INT_1610_DMA_CH14 (61 + IH2_BASE)
177#define INT_1610_DMA_CH15 (62 + IH2_BASE) 178#define INT_1610_DMA_CH15 (62 + IH2_BASE)
178#define INT_1610_NAND (63 + IH2_BASE) 179#define INT_1610_NAND (63 + IH2_BASE)
180#define INT_1610_SHA1MD5 (91 + IH2_BASE)
179 181
180/* 182/*
181 * OMAP-730 specific IRQ numbers for interrupt handler 2 183 * OMAP-730 specific IRQ numbers for interrupt handler 2
@@ -263,12 +265,18 @@
263#define INT_24XX_GPTIMER10 46 265#define INT_24XX_GPTIMER10 46
264#define INT_24XX_GPTIMER11 47 266#define INT_24XX_GPTIMER11 47
265#define INT_24XX_GPTIMER12 48 267#define INT_24XX_GPTIMER12 48
268#define INT_24XX_SHA1MD5 51
269#define INT_24XX_MCBSP4_IRQ_TX 54
270#define INT_24XX_MCBSP4_IRQ_RX 55
266#define INT_24XX_I2C1_IRQ 56 271#define INT_24XX_I2C1_IRQ 56
267#define INT_24XX_I2C2_IRQ 57 272#define INT_24XX_I2C2_IRQ 57
273#define INT_24XX_HDQ_IRQ 58
268#define INT_24XX_MCBSP1_IRQ_TX 59 274#define INT_24XX_MCBSP1_IRQ_TX 59
269#define INT_24XX_MCBSP1_IRQ_RX 60 275#define INT_24XX_MCBSP1_IRQ_RX 60
270#define INT_24XX_MCBSP2_IRQ_TX 62 276#define INT_24XX_MCBSP2_IRQ_TX 62
271#define INT_24XX_MCBSP2_IRQ_RX 63 277#define INT_24XX_MCBSP2_IRQ_RX 63
278#define INT_24XX_SPI1_IRQ 65
279#define INT_24XX_SPI2_IRQ 66
272#define INT_24XX_UART1_IRQ 72 280#define INT_24XX_UART1_IRQ 72
273#define INT_24XX_UART2_IRQ 73 281#define INT_24XX_UART2_IRQ 73
274#define INT_24XX_UART3_IRQ 74 282#define INT_24XX_UART3_IRQ 74
@@ -278,7 +286,58 @@
278#define INT_24XX_USB_IRQ_HGEN 78 286#define INT_24XX_USB_IRQ_HGEN 78
279#define INT_24XX_USB_IRQ_HSOF 79 287#define INT_24XX_USB_IRQ_HSOF 79
280#define INT_24XX_USB_IRQ_OTG 80 288#define INT_24XX_USB_IRQ_OTG 80
289#define INT_24XX_MCBSP5_IRQ_TX 81
290#define INT_24XX_MCBSP5_IRQ_RX 82
281#define INT_24XX_MMC_IRQ 83 291#define INT_24XX_MMC_IRQ 83
292#define INT_24XX_MMC2_IRQ 86
293#define INT_24XX_MCBSP3_IRQ_TX 89
294#define INT_24XX_MCBSP3_IRQ_RX 90
295#define INT_24XX_SPI3_IRQ 91
296
297#define INT_243X_MCBSP2_IRQ 16
298#define INT_243X_MCBSP3_IRQ 17
299#define INT_243X_MCBSP4_IRQ 18
300#define INT_243X_MCBSP5_IRQ 19
301#define INT_243X_MCBSP1_IRQ 64
302#define INT_243X_HS_USB_MC 92
303#define INT_243X_HS_USB_DMA 93
304#define INT_243X_CARKIT_IRQ 94
305
306#define INT_34XX_BENCH_MPU_EMUL 3
307#define INT_34XX_ST_MCBSP2_IRQ 4
308#define INT_34XX_ST_MCBSP3_IRQ 5
309#define INT_34XX_SSM_ABORT_IRQ 6
310#define INT_34XX_SYS_NIRQ 7
311#define INT_34XX_D2D_FW_IRQ 8
312#define INT_34XX_PRCM_MPU_IRQ 11
313#define INT_34XX_MCBSP1_IRQ 16
314#define INT_34XX_MCBSP2_IRQ 17
315#define INT_34XX_MCBSP3_IRQ 22
316#define INT_34XX_MCBSP4_IRQ 23
317#define INT_34XX_CAM_IRQ 24
318#define INT_34XX_MCBSP5_IRQ 27
319#define INT_34XX_GPIO_BANK1 29
320#define INT_34XX_GPIO_BANK2 30
321#define INT_34XX_GPIO_BANK3 31
322#define INT_34XX_GPIO_BANK4 32
323#define INT_34XX_GPIO_BANK5 33
324#define INT_34XX_GPIO_BANK6 34
325#define INT_34XX_USIM_IRQ 35
326#define INT_34XX_WDT3_IRQ 36
327#define INT_34XX_SPI4_IRQ 48
328#define INT_34XX_SHA1MD52_IRQ 49
329#define INT_34XX_FPKA_READY_IRQ 50
330#define INT_34XX_SHA1MD51_IRQ 51
331#define INT_34XX_RNG_IRQ 52
332#define INT_34XX_I2C3_IRQ 61
333#define INT_34XX_FPKA_ERROR_IRQ 64
334#define INT_34XX_PBIAS_IRQ 75
335#define INT_34XX_OHCI_IRQ 76
336#define INT_34XX_EHCI_IRQ 77
337#define INT_34XX_TLL_IRQ 78
338#define INT_34XX_PARTHASH_IRQ 79
339#define INT_34XX_MMC3_IRQ 94
340#define INT_34XX_GPT12_IRQ 95
282 341
283#define INT_34XX_BENCH_MPU_EMUL 3 342#define INT_34XX_BENCH_MPU_EMUL 3
284 343