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-rw-r--r--arch/arm/mm/Kconfig5
-rw-r--r--arch/arm/mm/cache-v6.S20
-rw-r--r--arch/arm/mm/cache-v7.S19
-rw-r--r--arch/arm/mm/context.c5
-rw-r--r--arch/arm/mm/dma-mapping.c4
-rw-r--r--arch/arm/mm/fault-armv.c9
-rw-r--r--arch/arm/mm/fault.c5
-rw-r--r--arch/arm/mm/flush.c31
-rw-r--r--arch/arm/mm/highmem.c2
-rw-r--r--arch/arm/mm/init.c22
-rw-r--r--arch/arm/mm/mmu.c7
-rw-r--r--arch/arm/mm/proc-v6.S7
-rw-r--r--arch/arm/mm/proc-v7.S14
13 files changed, 94 insertions, 56 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e993140edd8..9264d814cd7 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -122,10 +122,7 @@ config CPU_ARM920T
122 select CPU_TLB_V4WBI if MMU 122 select CPU_TLB_V4WBI if MMU
123 help 123 help
124 The ARM920T is licensed to be produced by numerous vendors, 124 The ARM920T is licensed to be produced by numerous vendors,
125 and is used in the Maverick EP9312 and the Samsung S3C2410. 125 and is used in the Cirrus EP93xx and the Samsung S3C2410.
126
127 More information on the Maverick EP9312 at
128 <http://linuxdevices.com/products/PD2382866068.html>.
129 126
130 Say Y if you want support for the ARM920T processor. 127 Say Y if you want support for the ARM920T processor.
131 Otherwise, say N. 128 Otherwise, say N.
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 8f5c13f4c93..295e25dd638 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -12,6 +12,7 @@
12#include <linux/linkage.h> 12#include <linux/linkage.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <asm/assembler.h> 14#include <asm/assembler.h>
15#include <asm/unwind.h>
15 16
16#include "proc-macros.S" 17#include "proc-macros.S"
17 18
@@ -121,11 +122,13 @@ ENTRY(v6_coherent_kern_range)
121 * - the Icache does not read data from the write buffer 122 * - the Icache does not read data from the write buffer
122 */ 123 */
123ENTRY(v6_coherent_user_range) 124ENTRY(v6_coherent_user_range)
124 125 UNWIND(.fnstart )
125#ifdef HARVARD_CACHE 126#ifdef HARVARD_CACHE
126 bic r0, r0, #CACHE_LINE_SIZE - 1 127 bic r0, r0, #CACHE_LINE_SIZE - 1
1271: mcr p15, 0, r0, c7, c10, 1 @ clean D line 1281:
129 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
128 add r0, r0, #CACHE_LINE_SIZE 130 add r0, r0, #CACHE_LINE_SIZE
1312:
129 cmp r0, r1 132 cmp r0, r1
130 blo 1b 133 blo 1b
131#endif 134#endif
@@ -143,6 +146,19 @@ ENTRY(v6_coherent_user_range)
143 mov pc, lr 146 mov pc, lr
144 147
145/* 148/*
149 * Fault handling for the cache operation above. If the virtual address in r0
150 * isn't mapped, just try the next page.
151 */
1529001:
153 mov r0, r0, lsr #12
154 mov r0, r0, lsl #12
155 add r0, r0, #4096
156 b 2b
157 UNWIND(.fnend )
158ENDPROC(v6_coherent_user_range)
159ENDPROC(v6_coherent_kern_range)
160
161/*
146 * v6_flush_kern_dcache_page(kaddr) 162 * v6_flush_kern_dcache_page(kaddr)
147 * 163 *
148 * Ensure that the data held in the page kaddr is written back 164 * Ensure that the data held in the page kaddr is written back
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index bda0ec31a4e..e1bd9759617 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -13,6 +13,7 @@
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <asm/assembler.h> 15#include <asm/assembler.h>
16#include <asm/unwind.h>
16 17
17#include "proc-macros.S" 18#include "proc-macros.S"
18 19
@@ -153,13 +154,16 @@ ENTRY(v7_coherent_kern_range)
153 * - the Icache does not read data from the write buffer 154 * - the Icache does not read data from the write buffer
154 */ 155 */
155ENTRY(v7_coherent_user_range) 156ENTRY(v7_coherent_user_range)
157 UNWIND(.fnstart )
156 dcache_line_size r2, r3 158 dcache_line_size r2, r3
157 sub r3, r2, #1 159 sub r3, r2, #1
158 bic r0, r0, r3 160 bic r0, r0, r3
1591: mcr p15, 0, r0, c7, c11, 1 @ clean D line to the point of unification 1611:
162 USER( mcr p15, 0, r0, c7, c11, 1 ) @ clean D line to the point of unification
160 dsb 163 dsb
161 mcr p15, 0, r0, c7, c5, 1 @ invalidate I line 164 USER( mcr p15, 0, r0, c7, c5, 1 ) @ invalidate I line
162 add r0, r0, r2 165 add r0, r0, r2
1662:
163 cmp r0, r1 167 cmp r0, r1
164 blo 1b 168 blo 1b
165 mov r0, #0 169 mov r0, #0
@@ -167,6 +171,17 @@ ENTRY(v7_coherent_user_range)
167 dsb 171 dsb
168 isb 172 isb
169 mov pc, lr 173 mov pc, lr
174
175/*
176 * Fault handling for the cache operation above. If the virtual address in r0
177 * isn't mapped, just try the next page.
178 */
1799001:
180 mov r0, r0, lsr #12
181 mov r0, r0, lsl #12
182 add r0, r0, #4096
183 b 2b
184 UNWIND(.fnend )
170ENDPROC(v7_coherent_kern_range) 185ENDPROC(v7_coherent_kern_range)
171ENDPROC(v7_coherent_user_range) 186ENDPROC(v7_coherent_user_range)
172 187
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 6bda76a4319..a9e22e31eaa 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -50,10 +50,7 @@ void __new_context(struct mm_struct *mm)
50 isb(); 50 isb();
51 flush_tlb_all(); 51 flush_tlb_all();
52 if (icache_is_vivt_asid_tagged()) { 52 if (icache_is_vivt_asid_tagged()) {
53 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" 53 __flush_icache_all();
54 "mcr p15, 0, %0, c7, c5, 6 @ flush BTAC/BTB\n"
55 :
56 : "r" (0));
57 dsb(); 54 dsb();
58 } 55 }
59 } 56 }
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index b30925fcbcd..b9590a7085c 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -205,7 +205,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
205 205
206 order = get_order(size); 206 order = get_order(size);
207 207
208 if (mask != 0xffffffff) 208 if (mask < 0xffffffffULL)
209 gfp |= GFP_DMA; 209 gfp |= GFP_DMA;
210 210
211 page = alloc_pages(gfp, order); 211 page = alloc_pages(gfp, order);
@@ -289,7 +289,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
289 if (!mask) 289 if (!mask)
290 goto error; 290 goto error;
291 291
292 if (mask != 0xffffffff) 292 if (mask < 0xffffffffULL)
293 gfp |= GFP_DMA; 293 gfp |= GFP_DMA;
294 virt = kmalloc(size, gfp); 294 virt = kmalloc(size, gfp);
295 if (!virt) 295 if (!virt)
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index bc0099d5ae8..d0d17b6a370 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -153,14 +153,11 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
153 153
154 page = pfn_to_page(pfn); 154 page = pfn_to_page(pfn);
155 mapping = page_mapping(page); 155 mapping = page_mapping(page);
156 if (mapping) {
157#ifndef CONFIG_SMP 156#ifndef CONFIG_SMP
158 int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags); 157 if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
159 158 __flush_dcache_page(mapping, page);
160 if (dirty)
161 __flush_dcache_page(mapping, page);
162#endif 159#endif
163 160 if (mapping) {
164 if (cache_is_vivt()) 161 if (cache_is_vivt())
165 make_coherent(mapping, vma, addr, pfn); 162 make_coherent(mapping, vma, addr, pfn);
166 else if (vma->vm_flags & VM_EXEC) 163 else if (vma->vm_flags & VM_EXEC)
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index ae0e25f5a70..10e06801afb 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -292,6 +292,11 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
292 * down_read() 292 * down_read()
293 */ 293 */
294 might_sleep(); 294 might_sleep();
295#ifdef CONFIG_DEBUG_VM
296 if (!user_mode(regs) &&
297 !search_exception_tables(regs->ARM_pc))
298 goto no_context;
299#endif
295 } 300 }
296 301
297 fault = __do_page_fault(mm, addr, fsr, tsk); 302 fault = __do_page_fault(mm, addr, fsr, tsk);
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index b27942909b2..7f294f307c8 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -18,10 +18,6 @@
18 18
19#include "mm.h" 19#include "mm.h"
20 20
21#ifdef CONFIG_ARM_ERRATA_411920
22extern void v6_icache_inval_all(void);
23#endif
24
25#ifdef CONFIG_CPU_CACHE_VIPT 21#ifdef CONFIG_CPU_CACHE_VIPT
26 22
27#define ALIAS_FLUSH_START 0xffff4000 23#define ALIAS_FLUSH_START 0xffff4000
@@ -35,16 +31,11 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
35 flush_tlb_kernel_page(to); 31 flush_tlb_kernel_page(to);
36 32
37 asm( "mcrr p15, 0, %1, %0, c14\n" 33 asm( "mcrr p15, 0, %1, %0, c14\n"
38 " mcr p15, 0, %2, c7, c10, 4\n" 34 " mcr p15, 0, %2, c7, c10, 4"
39#ifndef CONFIG_ARM_ERRATA_411920
40 " mcr p15, 0, %2, c7, c5, 0\n"
41#endif
42 : 35 :
43 : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) 36 : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
44 : "cc"); 37 : "cc");
45#ifdef CONFIG_ARM_ERRATA_411920 38 __flush_icache_all();
46 v6_icache_inval_all();
47#endif
48} 39}
49 40
50void flush_cache_mm(struct mm_struct *mm) 41void flush_cache_mm(struct mm_struct *mm)
@@ -57,16 +48,11 @@ void flush_cache_mm(struct mm_struct *mm)
57 48
58 if (cache_is_vipt_aliasing()) { 49 if (cache_is_vipt_aliasing()) {
59 asm( "mcr p15, 0, %0, c7, c14, 0\n" 50 asm( "mcr p15, 0, %0, c7, c14, 0\n"
60 " mcr p15, 0, %0, c7, c10, 4\n" 51 " mcr p15, 0, %0, c7, c10, 4"
61#ifndef CONFIG_ARM_ERRATA_411920
62 " mcr p15, 0, %0, c7, c5, 0\n"
63#endif
64 : 52 :
65 : "r" (0) 53 : "r" (0)
66 : "cc"); 54 : "cc");
67#ifdef CONFIG_ARM_ERRATA_411920 55 __flush_icache_all();
68 v6_icache_inval_all();
69#endif
70 } 56 }
71} 57}
72 58
@@ -81,16 +67,11 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned
81 67
82 if (cache_is_vipt_aliasing()) { 68 if (cache_is_vipt_aliasing()) {
83 asm( "mcr p15, 0, %0, c7, c14, 0\n" 69 asm( "mcr p15, 0, %0, c7, c14, 0\n"
84 " mcr p15, 0, %0, c7, c10, 4\n" 70 " mcr p15, 0, %0, c7, c10, 4"
85#ifndef CONFIG_ARM_ERRATA_411920
86 " mcr p15, 0, %0, c7, c5, 0\n"
87#endif
88 : 71 :
89 : "r" (0) 72 : "r" (0)
90 : "cc"); 73 : "cc");
91#ifdef CONFIG_ARM_ERRATA_411920 74 __flush_icache_all();
92 v6_icache_inval_all();
93#endif
94 } 75 }
95} 76}
96 77
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 73cae57fa70..30f82fb5918 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -46,6 +46,8 @@ void *kmap_atomic(struct page *page, enum km_type type)
46 if (!PageHighMem(page)) 46 if (!PageHighMem(page))
47 return page_address(page); 47 return page_address(page);
48 48
49 debug_kmap_atomic(type);
50
49 kmap = kmap_high_get(page); 51 kmap = kmap_high_get(page);
50 if (kmap) 52 if (kmap)
51 return kmap; 53 return kmap;
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 877c492f8e1..52c40d15567 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -273,7 +273,6 @@ static void __init bootmem_init_node(int node, struct meminfo *mi,
273 struct membank *bank = &mi->bank[i]; 273 struct membank *bank = &mi->bank[i];
274 if (!bank->highmem) 274 if (!bank->highmem)
275 free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank)); 275 free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
276 memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank));
277 } 276 }
278 277
279 /* 278 /*
@@ -370,6 +369,19 @@ int pfn_valid(unsigned long pfn)
370 return 0; 369 return 0;
371} 370}
372EXPORT_SYMBOL(pfn_valid); 371EXPORT_SYMBOL(pfn_valid);
372
373static void arm_memory_present(struct meminfo *mi, int node)
374{
375}
376#else
377static void arm_memory_present(struct meminfo *mi, int node)
378{
379 int i;
380 for_each_nodebank(i, mi, node) {
381 struct membank *bank = &mi->bank[i];
382 memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank));
383 }
384}
373#endif 385#endif
374 386
375static int __init meminfo_cmp(const void *_a, const void *_b) 387static int __init meminfo_cmp(const void *_a, const void *_b)
@@ -427,6 +439,12 @@ void __init bootmem_init(void)
427 */ 439 */
428 if (node == initrd_node) 440 if (node == initrd_node)
429 bootmem_reserve_initrd(node); 441 bootmem_reserve_initrd(node);
442
443 /*
444 * Sparsemem tries to allocate bootmem in memory_present(),
445 * so must be done after the fixed reservations
446 */
447 arm_memory_present(mi, node);
430 } 448 }
431 449
432 /* 450 /*
@@ -483,7 +501,7 @@ free_memmap(int node, unsigned long start_pfn, unsigned long end_pfn)
483 /* 501 /*
484 * Convert start_pfn/end_pfn to a struct page pointer. 502 * Convert start_pfn/end_pfn to a struct page pointer.
485 */ 503 */
486 start_pg = pfn_to_page(start_pfn); 504 start_pg = pfn_to_page(start_pfn - 1) + 1;
487 end_pg = pfn_to_page(end_pfn); 505 end_pg = pfn_to_page(end_pfn);
488 506
489 /* 507 /*
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 02243eeccf5..ea67be0223a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -117,6 +117,13 @@ static void __init early_cachepolicy(char **p)
117 } 117 }
118 if (i == ARRAY_SIZE(cache_policies)) 118 if (i == ARRAY_SIZE(cache_policies))
119 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); 119 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
120 /*
121 * This restriction is partly to do with the way we boot; it is
122 * unpredictable to have memory mapped using two different sets of
123 * memory attributes (shared, type, and cache attribs). We can not
124 * change these attributes once the initial assembly has setup the
125 * page tables.
126 */
120 if (cpu_architecture() >= CPU_ARCH_ARMv6) { 127 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
121 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); 128 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
122 cachepolicy = CPOLICY_WRITEBACK; 129 cachepolicy = CPOLICY_WRITEBACK;
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 194737d60a2..70f75d2e3ea 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -32,8 +32,10 @@
32 32
33#ifndef CONFIG_SMP 33#ifndef CONFIG_SMP
34#define TTB_FLAGS TTB_RGN_WBWA 34#define TTB_FLAGS TTB_RGN_WBWA
35#define PMD_FLAGS PMD_SECT_WB
35#else 36#else
36#define TTB_FLAGS TTB_RGN_WBWA|TTB_S 37#define TTB_FLAGS TTB_RGN_WBWA|TTB_S
38#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
37#endif 39#endif
38 40
39ENTRY(cpu_v6_proc_init) 41ENTRY(cpu_v6_proc_init)
@@ -222,10 +224,9 @@ __v6_proc_info:
222 .long 0x0007b000 224 .long 0x0007b000
223 .long 0x0007f000 225 .long 0x0007f000
224 .long PMD_TYPE_SECT | \ 226 .long PMD_TYPE_SECT | \
225 PMD_SECT_BUFFERABLE | \
226 PMD_SECT_CACHEABLE | \
227 PMD_SECT_AP_WRITE | \ 227 PMD_SECT_AP_WRITE | \
228 PMD_SECT_AP_READ 228 PMD_SECT_AP_READ | \
229 PMD_FLAGS
229 .long PMD_TYPE_SECT | \ 230 .long PMD_TYPE_SECT | \
230 PMD_SECT_XN | \ 231 PMD_SECT_XN | \
231 PMD_SECT_AP_WRITE | \ 232 PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 23ebcf6eab9..3a285218fd1 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -33,9 +33,11 @@
33#ifndef CONFIG_SMP 33#ifndef CONFIG_SMP
34/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 34/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB 35#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
36#define PMD_FLAGS PMD_SECT_WB
36#else 37#else
37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 38/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
38#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 39#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
40#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
39#endif 41#endif
40 42
41ENTRY(cpu_v7_proc_init) 43ENTRY(cpu_v7_proc_init)
@@ -184,9 +186,10 @@ cpu_v7_name:
184 */ 186 */
185__v7_setup: 187__v7_setup:
186#ifdef CONFIG_SMP 188#ifdef CONFIG_SMP
187 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode and 189 mrc p15, 0, r0, c1, c0, 1
188 orr r0, r0, #(1 << 6) | (1 << 0) @ TLB ops broadcasting 190 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
189 mcr p15, 0, r0, c1, c0, 1 191 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
192 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
190#endif 193#endif
191 adr r12, __v7_setup_stack @ the local stack 194 adr r12, __v7_setup_stack @ the local stack
192 stmia r12, {r0-r5, r7, r9, r11, lr} 195 stmia r12, {r0-r5, r7, r9, r11, lr}
@@ -326,10 +329,9 @@ __v7_proc_info:
326 .long 0x000f0000 @ Required ID value 329 .long 0x000f0000 @ Required ID value
327 .long 0x000f0000 @ Mask for ID 330 .long 0x000f0000 @ Mask for ID
328 .long PMD_TYPE_SECT | \ 331 .long PMD_TYPE_SECT | \
329 PMD_SECT_BUFFERABLE | \
330 PMD_SECT_CACHEABLE | \
331 PMD_SECT_AP_WRITE | \ 332 PMD_SECT_AP_WRITE | \
332 PMD_SECT_AP_READ 333 PMD_SECT_AP_READ | \
334 PMD_FLAGS
333 .long PMD_TYPE_SECT | \ 335 .long PMD_TYPE_SECT | \
334 PMD_SECT_XN | \ 336 PMD_SECT_XN | \
335 PMD_SECT_AP_WRITE | \ 337 PMD_SECT_AP_WRITE | \
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-06 10:00:22 -0500