1 files changed, 20 insertions, 16 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S
index 336adccea54..0cd0fc9635b 100644
--- a/arch/arm/mach-sa1100/include/mach/debug-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S
@@ -12,33 +12,37 @@
 */
 #include <mach/hardware.h>
-                .macro  addruart, rx, tmp
+                .macro  addruart, rp, rv
-                mrc     p15, 0, \rx, c1, c0
+                mrc     p15, 0, \rp, c1, c0
-                tst     \rx, #1                 @ MMU enabled?
+                tst     \rp, #1                 @ MMU enabled?
-                moveq   \rx, #0x80000000        @ physical base address
+                moveq   \rp, #0x80000000        @ physical base address
-                movne   \rx, #0xf8000000        @ virtual address
+                movne   \rp, #0xf8000000        @ virtual address
                @ We probe for the active serial port here, coherently with
                @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
                @ We assume r1 can be clobbered.
                @ see if Ser3 is active
-                add     \rx, \rx, #0x00050000
+                add     \rp, \rp, #0x00050000
-                ldr     r1, [\rx, #UTCR3]
+                ldr     \rv, [\rp, #UTCR3]
-                tst     r1, #UTCR3_TXE
+                tst     \rv, #UTCR3_TXE
                @ if Ser3 is inactive, then try Ser1
-                addeq   \rx, \rx, #(0x00010000 - 0x00050000)
+                addeq   \rp, \rp, #(0x00010000 - 0x00050000)
-                ldreq   r1, [\rx, #UTCR3]
+                ldreq   \rv, [\rp, #UTCR3]
-                tsteq   r1, #UTCR3_TXE
+                tsteq   \rv, #UTCR3_TXE
                @ if Ser1 is inactive, then try Ser2
-                addeq   \rx, \rx, #(0x00030000 - 0x00010000)
+                addeq   \rp, \rp, #(0x00030000 - 0x00010000)
-                ldreq   r1, [\rx, #UTCR3]
+                ldreq   \rv, [\rp, #UTCR3]
-                tsteq   r1, #UTCR3_TXE
+                tsteq   \rv, #UTCR3_TXE
+                @ clear top bits, and generate both phys and virt addresses
+                lsl     \rp, \rp, #8
+                lsr     \rp, \rp, #8
+                orr     \rv, \rp, #0xf8000000   @ virtual
+                orr     \rp, \rp, #0x80000000   @ physical
-                @ if all ports are inactive, then there is nothing we can do
-                moveq   pc, lr
                .endm
                .macro  senduart,rd,rx

diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S index 336adccea54..0cd0fc9635b 100644 --- a/arch/arm/mach-sa1100/include/mach/debug-macro.S +++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S
@@ -12,33 +12,37 @@
12	*/	12	*/
13	#include <mach/hardware.h>	13	#include <mach/hardware.h>
14		14
15	.macro addruart, rx, tmp	15	.macro addruart, rp, rv
16	mrc p15, 0, \rx, c1, c0	16	mrc p15, 0, \rp, c1, c0
17	tst \rx, #1 @ MMU enabled?	17	tst \rp, #1 @ MMU enabled?
18	moveq \rx, #0x80000000 @ physical base address	18	moveq \rp, #0x80000000 @ physical base address
19	movne \rx, #0xf8000000 @ virtual address	19	movne \rp, #0xf8000000 @ virtual address
20		20
21	@ We probe for the active serial port here, coherently with	21	@ We probe for the active serial port here, coherently with
22	@ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.	22	@ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
23	@ We assume r1 can be clobbered.	23	@ We assume r1 can be clobbered.
24		24
25	@ see if Ser3 is active	25	@ see if Ser3 is active
26	add \rx, \rx, #0x00050000	26	add \rp, \rp, #0x00050000
27	ldr r1, [\rx, #UTCR3]	27	ldr \rv, [\rp, #UTCR3]
28	tst r1, #UTCR3_TXE	28	tst \rv, #UTCR3_TXE
29		29
30	@ if Ser3 is inactive, then try Ser1	30	@ if Ser3 is inactive, then try Ser1
31	addeq \rx, \rx, #(0x00010000 - 0x00050000)	31	addeq \rp, \rp, #(0x00010000 - 0x00050000)
32	ldreq r1, [\rx, #UTCR3]	32	ldreq \rv, [\rp, #UTCR3]
33	tsteq r1, #UTCR3_TXE	33	tsteq \rv, #UTCR3_TXE
34		34
35	@ if Ser1 is inactive, then try Ser2	35	@ if Ser1 is inactive, then try Ser2
36	addeq \rx, \rx, #(0x00030000 - 0x00010000)	36	addeq \rp, \rp, #(0x00030000 - 0x00010000)
37	ldreq r1, [\rx, #UTCR3]	37	ldreq \rv, [\rp, #UTCR3]
38	tsteq r1, #UTCR3_TXE	38	tsteq \rv, #UTCR3_TXE
		39
		40	@ clear top bits, and generate both phys and virt addresses
		41	lsl \rp, \rp, #8
		42	lsr \rp, \rp, #8
		43	orr \rv, \rp, #0xf8000000 @ virtual
		44	orr \rp, \rp, #0x80000000 @ physical
39		45
40	@ if all ports are inactive, then there is nothing we can do
41	moveq pc, lr
42	.endm	46	.endm
43		47
44	.macro senduart,rd,rx	48	.macro senduart,rd,rx