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-rw-r--r--arch/arm/mach-s5pv310/Kconfig95
-rw-r--r--arch/arm/mach-s5pv310/Makefile10
-rw-r--r--arch/arm/mach-s5pv310/clock.c635
-rw-r--r--arch/arm/mach-s5pv310/cpu.c47
-rw-r--r--arch/arm/mach-s5pv310/gpiolib.c304
-rw-r--r--arch/arm/mach-s5pv310/hotplug.c144
-rw-r--r--arch/arm/mach-s5pv310/include/mach/irqs.h44
-rw-r--r--arch/arm/mach-s5pv310/include/mach/map.h19
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-clock.h32
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-gpio.h42
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-srom.h50
-rw-r--r--arch/arm/mach-s5pv310/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-s5pv310/irq-combiner.c6
-rw-r--r--arch/arm/mach-s5pv310/irq-eint.c228
-rw-r--r--arch/arm/mach-s5pv310/mach-smdkc210.c202
-rw-r--r--arch/arm/mach-s5pv310/mach-smdkv310.c121
-rw-r--r--arch/arm/mach-s5pv310/mach-universal_c210.c81
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c0.c6
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c1.c6
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c2.c6
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c3.c23
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c4.c23
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c5.c23
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c6.c23
-rw-r--r--arch/arm/mach-s5pv310/setup-i2c7.c23
-rw-r--r--arch/arm/mach-s5pv310/setup-sdhci-gpio.c152
-rw-r--r--arch/arm/mach-s5pv310/setup-sdhci.c69
27 files changed, 2306 insertions, 110 deletions
diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
index 331b5bd97ab..1150b360f38 100644
--- a/arch/arm/mach-s5pv310/Kconfig
+++ b/arch/arm/mach-s5pv310/Kconfig
@@ -11,7 +11,6 @@ if ARCH_S5PV310
11 11
12config CPU_S5PV310 12config CPU_S5PV310
13 bool 13 bool
14 select PLAT_S5P
15 help 14 help
16 Enable S5PV310 CPU support 15 Enable S5PV310 CPU support
17 16
@@ -25,21 +24,105 @@ config S5PV310_SETUP_I2C2
25 help 24 help
26 Common setup code for i2c bus 2. 25 Common setup code for i2c bus 2.
27 26
27config S5PV310_SETUP_I2C3
28 bool
29 help
30 Common setup code for i2c bus 3.
31
32config S5PV310_SETUP_I2C4
33 bool
34 help
35 Common setup code for i2c bus 4.
36
37config S5PV310_SETUP_I2C5
38 bool
39 help
40 Common setup code for i2c bus 5.
41
42config S5PV310_SETUP_I2C6
43 bool
44 help
45 Common setup code for i2c bus 6.
46
47config S5PV310_SETUP_I2C7
48 bool
49 help
50 Common setup code for i2c bus 7.
51
52config S5PV310_SETUP_SDHCI
53 bool
54 select S5PV310_SETUP_SDHCI_GPIO
55 help
56 Internal helper functions for S5PV310 based SDHCI systems.
57
58config S5PV310_SETUP_SDHCI_GPIO
59 bool
60 help
61 Common setup code for SDHCI gpio.
62
28# machine support 63# machine support
29 64
30config MACH_SMDKV310 65menu "S5PC210 Machines"
31 bool "SMDKV310" 66
67config MACH_SMDKC210
68 bool "SMDKC210"
32 select CPU_S5PV310 69 select CPU_S5PV310
33 select ARCH_SPARSEMEM_ENABLE 70 select S3C_DEV_RTC
71 select S3C_DEV_WDT
72 select S3C_DEV_HSMMC
73 select S3C_DEV_HSMMC1
74 select S3C_DEV_HSMMC2
75 select S3C_DEV_HSMMC3
76 select S5PV310_SETUP_SDHCI
34 help 77 help
35 Machine support for Samsung SMDKV310 78 Machine support for Samsung SMDKC210
79 S5PC210(MCP) is one of package option of S5PV310
36 80
37config MACH_UNIVERSAL_C210 81config MACH_UNIVERSAL_C210
38 bool "Mobile UNIVERSAL_C210 Board" 82 bool "Mobile UNIVERSAL_C210 Board"
39 select CPU_S5PV310 83 select CPU_S5PV310
40 select ARCH_SPARSEMEM_ENABLE 84 select S5P_DEV_ONENAND
85 select S3C_DEV_I2C1
86 select S5PV310_SETUP_I2C1
41 help 87 help
42 Machine support for Samsung Mobile Universal S5PC210 Reference 88 Machine support for Samsung Mobile Universal S5PC210 Reference
43 Board. S5PC210(MCP) is one of package option of S5PV310 89 Board. S5PC210(MCP) is one of package option of S5PV310
44 90
91endmenu
92
93menu "S5PV310 Machines"
94
95config MACH_SMDKV310
96 bool "SMDKV310"
97 select CPU_S5PV310
98 select S3C_DEV_RTC
99 select S3C_DEV_WDT
100 select S3C_DEV_HSMMC
101 select S3C_DEV_HSMMC1
102 select S3C_DEV_HSMMC2
103 select S3C_DEV_HSMMC3
104 select S5PV310_SETUP_SDHCI
105 help
106 Machine support for Samsung SMDKV310
107
108endmenu
109
110comment "Configuration for HSMMC bus width"
111
112menu "Use 8-bit bus width"
113
114config S5PV310_SDHCI_CH0_8BIT
115 bool "Channel 0 with 8-bit bus"
116 help
117 Support HSMMC Channel 0 8-bit bus.
118 If selected, Channel 1 is disabled.
119
120config S5PV310_SDHCI_CH2_8BIT
121 bool "Channel 2 with 8-bit bus"
122 help
123 Support HSMMC Channel 2 8-bit bus.
124 If selected, Channel 3 is disabled.
125
126endmenu
127
45endif 128endif
diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
index d5b51c72340..84afc64e7c0 100644
--- a/arch/arm/mach-s5pv310/Makefile
+++ b/arch/arm/mach-s5pv310/Makefile
@@ -13,7 +13,7 @@ obj- :=
13# Core support for S5PV310 system 13# Core support for S5PV310 system
14 14
15obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o 15obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o 16obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o
17 17
18obj-$(CONFIG_SMP) += platsmp.o headsmp.o 18obj-$(CONFIG_SMP) += platsmp.o headsmp.o
19obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o 19obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
@@ -21,6 +21,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
21 21
22# machine support 22# machine support
23 23
24obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
24obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o 25obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
25obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o 26obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
26 27
@@ -28,3 +29,10 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
28 29
29obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o 30obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o
30obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o 31obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o
32obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o
33obj-$(CONFIG_S5PV310_SETUP_I2C4) += setup-i2c4.o
34obj-$(CONFIG_S5PV310_SETUP_I2C5) += setup-i2c5.o
35obj-$(CONFIG_S5PV310_SETUP_I2C6) += setup-i2c6.o
36obj-$(CONFIG_S5PV310_SETUP_I2C7) += setup-i2c7.o
37obj-$(CONFIG_S5PV310_SETUP_SDHCI) += setup-sdhci.o
38obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 26a0f03df8e..58c9d33f36f 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -30,16 +30,92 @@ static struct clk clk_sclk_hdmi27m = {
30 .rate = 27000000, 30 .rate = 27000000,
31}; 31};
32 32
33static struct clk clk_sclk_hdmiphy = {
34 .name = "sclk_hdmiphy",
35 .id = -1,
36};
37
38static struct clk clk_sclk_usbphy0 = {
39 .name = "sclk_usbphy0",
40 .id = -1,
41 .rate = 27000000,
42};
43
44static struct clk clk_sclk_usbphy1 = {
45 .name = "sclk_usbphy1",
46 .id = -1,
47};
48
49static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
50{
51 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
52}
53
54static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
55{
56 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
57}
58
59static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
60{
61 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
62}
63
64static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
65{
66 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
67}
68
69static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
70{
71 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
72}
73
33static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) 74static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
34{ 75{
35 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); 76 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
36} 77}
37 78
79static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
80{
81 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
82}
83
84static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
85{
86 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
87}
88
89static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
90{
91 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
92}
93
94static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
95{
96 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
97}
98
99static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
100{
101 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
102}
103
104static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
105{
106 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
107}
108
38static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable) 109static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
39{ 110{
40 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); 111 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
41} 112}
42 113
114static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable)
115{
116 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
117}
118
43/* Core list of CMU_CPU side */ 119/* Core list of CMU_CPU side */
44 120
45static struct clksrc_clk clk_mout_apll = { 121static struct clksrc_clk clk_mout_apll = {
@@ -79,7 +155,7 @@ static struct clksrc_clk clk_mout_mpll = {
79}; 155};
80 156
81static struct clk *clkset_moutcore_list[] = { 157static struct clk *clkset_moutcore_list[] = {
82 [0] = &clk_sclk_apll.clk, 158 [0] = &clk_mout_apll.clk,
83 [1] = &clk_mout_mpll.clk, 159 [1] = &clk_mout_mpll.clk,
84}; 160};
85 161
@@ -150,24 +226,6 @@ static struct clksrc_clk clk_periphclk = {
150 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, 226 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
151}; 227};
152 228
153static struct clksrc_clk clk_atclk = {
154 .clk = {
155 .name = "atclk",
156 .id = -1,
157 .parent = &clk_moutcore.clk,
158 },
159 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
160};
161
162static struct clksrc_clk clk_pclk_dbg = {
163 .clk = {
164 .name = "pclk_dbg",
165 .id = -1,
166 .parent = &clk_atclk.clk,
167 },
168 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
169};
170
171/* Core list of CMU_CORE side */ 229/* Core list of CMU_CORE side */
172 230
173static struct clk *clkset_corebus_list[] = { 231static struct clk *clkset_corebus_list[] = {
@@ -241,7 +299,7 @@ static struct clk *clkset_aclk_top_list[] = {
241 [1] = &clk_sclk_apll.clk, 299 [1] = &clk_sclk_apll.clk,
242}; 300};
243 301
244static struct clksrc_sources clkset_aclk_200 = { 302static struct clksrc_sources clkset_aclk = {
245 .sources = clkset_aclk_top_list, 303 .sources = clkset_aclk_top_list,
246 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), 304 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
247}; 305};
@@ -251,52 +309,37 @@ static struct clksrc_clk clk_aclk_200 = {
251 .name = "aclk_200", 309 .name = "aclk_200",
252 .id = -1, 310 .id = -1,
253 }, 311 },
254 .sources = &clkset_aclk_200, 312 .sources = &clkset_aclk,
255 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, 313 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
256 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 }, 314 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
257}; 315};
258 316
259static struct clksrc_sources clkset_aclk_100 = {
260 .sources = clkset_aclk_top_list,
261 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
262};
263
264static struct clksrc_clk clk_aclk_100 = { 317static struct clksrc_clk clk_aclk_100 = {
265 .clk = { 318 .clk = {
266 .name = "aclk_100", 319 .name = "aclk_100",
267 .id = -1, 320 .id = -1,
268 }, 321 },
269 .sources = &clkset_aclk_100, 322 .sources = &clkset_aclk,
270 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, 323 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
271 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 }, 324 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
272}; 325};
273 326
274static struct clksrc_sources clkset_aclk_160 = {
275 .sources = clkset_aclk_top_list,
276 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
277};
278
279static struct clksrc_clk clk_aclk_160 = { 327static struct clksrc_clk clk_aclk_160 = {
280 .clk = { 328 .clk = {
281 .name = "aclk_160", 329 .name = "aclk_160",
282 .id = -1, 330 .id = -1,
283 }, 331 },
284 .sources = &clkset_aclk_160, 332 .sources = &clkset_aclk,
285 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, 333 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
286 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 }, 334 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
287}; 335};
288 336
289static struct clksrc_sources clkset_aclk_133 = {
290 .sources = clkset_aclk_top_list,
291 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
292};
293
294static struct clksrc_clk clk_aclk_133 = { 337static struct clksrc_clk clk_aclk_133 = {
295 .clk = { 338 .clk = {
296 .name = "aclk_133", 339 .name = "aclk_133",
297 .id = -1, 340 .id = -1,
298 }, 341 },
299 .sources = &clkset_aclk_133, 342 .sources = &clkset_aclk,
300 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, 343 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
301 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 }, 344 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
302}; 345};
@@ -315,6 +358,8 @@ static struct clksrc_clk clk_vpllsrc = {
315 .clk = { 358 .clk = {
316 .name = "vpll_src", 359 .name = "vpll_src",
317 .id = -1, 360 .id = -1,
361 .enable = s5pv310_clksrc_mask_top_ctrl,
362 .ctrlbit = (1 << 0),
318 }, 363 },
319 .sources = &clkset_vpllsrc, 364 .sources = &clkset_vpllsrc,
320 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 }, 365 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
@@ -346,7 +391,175 @@ static struct clk init_clocks_disable[] = {
346 .parent = &clk_aclk_100.clk, 391 .parent = &clk_aclk_100.clk,
347 .enable = s5pv310_clk_ip_peril_ctrl, 392 .enable = s5pv310_clk_ip_peril_ctrl,
348 .ctrlbit = (1<<24), 393 .ctrlbit = (1<<24),
349 } 394 }, {
395 .name = "csis",
396 .id = 0,
397 .enable = s5pv310_clk_ip_cam_ctrl,
398 .ctrlbit = (1 << 4),
399 }, {
400 .name = "csis",
401 .id = 1,
402 .enable = s5pv310_clk_ip_cam_ctrl,
403 .ctrlbit = (1 << 5),
404 }, {
405 .name = "fimc",
406 .id = 0,
407 .enable = s5pv310_clk_ip_cam_ctrl,
408 .ctrlbit = (1 << 0),
409 }, {
410 .name = "fimc",
411 .id = 1,
412 .enable = s5pv310_clk_ip_cam_ctrl,
413 .ctrlbit = (1 << 1),
414 }, {
415 .name = "fimc",
416 .id = 2,
417 .enable = s5pv310_clk_ip_cam_ctrl,
418 .ctrlbit = (1 << 2),
419 }, {
420 .name = "fimc",
421 .id = 3,
422 .enable = s5pv310_clk_ip_cam_ctrl,
423 .ctrlbit = (1 << 3),
424 }, {
425 .name = "fimd",
426 .id = 0,
427 .enable = s5pv310_clk_ip_lcd0_ctrl,
428 .ctrlbit = (1 << 0),
429 }, {
430 .name = "fimd",
431 .id = 1,
432 .enable = s5pv310_clk_ip_lcd1_ctrl,
433 .ctrlbit = (1 << 0),
434 }, {
435 .name = "hsmmc",
436 .id = 0,
437 .parent = &clk_aclk_133.clk,
438 .enable = s5pv310_clk_ip_fsys_ctrl,
439 .ctrlbit = (1 << 5),
440 }, {
441 .name = "hsmmc",
442 .id = 1,
443 .parent = &clk_aclk_133.clk,
444 .enable = s5pv310_clk_ip_fsys_ctrl,
445 .ctrlbit = (1 << 6),
446 }, {
447 .name = "hsmmc",
448 .id = 2,
449 .parent = &clk_aclk_133.clk,
450 .enable = s5pv310_clk_ip_fsys_ctrl,
451 .ctrlbit = (1 << 7),
452 }, {
453 .name = "hsmmc",
454 .id = 3,
455 .parent = &clk_aclk_133.clk,
456 .enable = s5pv310_clk_ip_fsys_ctrl,
457 .ctrlbit = (1 << 8),
458 }, {
459 .name = "hsmmc",
460 .id = 4,
461 .parent = &clk_aclk_133.clk,
462 .enable = s5pv310_clk_ip_fsys_ctrl,
463 .ctrlbit = (1 << 9),
464 }, {
465 .name = "sata",
466 .id = -1,
467 .enable = s5pv310_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 10),
469 }, {
470 .name = "adc",
471 .id = -1,
472 .enable = s5pv310_clk_ip_peril_ctrl,
473 .ctrlbit = (1 << 15),
474 }, {
475 .name = "rtc",
476 .id = -1,
477 .enable = s5pv310_clk_ip_perir_ctrl,
478 .ctrlbit = (1 << 15),
479 }, {
480 .name = "watchdog",
481 .id = -1,
482 .enable = s5pv310_clk_ip_perir_ctrl,
483 .ctrlbit = (1 << 14),
484 }, {
485 .name = "usbhost",
486 .id = -1,
487 .enable = s5pv310_clk_ip_fsys_ctrl ,
488 .ctrlbit = (1 << 12),
489 }, {
490 .name = "otg",
491 .id = -1,
492 .enable = s5pv310_clk_ip_fsys_ctrl,
493 .ctrlbit = (1 << 13),
494 }, {
495 .name = "spi",
496 .id = 0,
497 .enable = s5pv310_clk_ip_peril_ctrl,
498 .ctrlbit = (1 << 16),
499 }, {
500 .name = "spi",
501 .id = 1,
502 .enable = s5pv310_clk_ip_peril_ctrl,
503 .ctrlbit = (1 << 17),
504 }, {
505 .name = "spi",
506 .id = 2,
507 .enable = s5pv310_clk_ip_peril_ctrl,
508 .ctrlbit = (1 << 18),
509 }, {
510 .name = "fimg2d",
511 .id = -1,
512 .enable = s5pv310_clk_ip_image_ctrl,
513 .ctrlbit = (1 << 0),
514 }, {
515 .name = "i2c",
516 .id = 0,
517 .parent = &clk_aclk_100.clk,
518 .enable = s5pv310_clk_ip_peril_ctrl,
519 .ctrlbit = (1 << 6),
520 }, {
521 .name = "i2c",
522 .id = 1,
523 .parent = &clk_aclk_100.clk,
524 .enable = s5pv310_clk_ip_peril_ctrl,
525 .ctrlbit = (1 << 7),
526 }, {
527 .name = "i2c",
528 .id = 2,
529 .parent = &clk_aclk_100.clk,
530 .enable = s5pv310_clk_ip_peril_ctrl,
531 .ctrlbit = (1 << 8),
532 }, {
533 .name = "i2c",
534 .id = 3,
535 .parent = &clk_aclk_100.clk,
536 .enable = s5pv310_clk_ip_peril_ctrl,
537 .ctrlbit = (1 << 9),
538 }, {
539 .name = "i2c",
540 .id = 4,
541 .parent = &clk_aclk_100.clk,
542 .enable = s5pv310_clk_ip_peril_ctrl,
543 .ctrlbit = (1 << 10),
544 }, {
545 .name = "i2c",
546 .id = 5,
547 .parent = &clk_aclk_100.clk,
548 .enable = s5pv310_clk_ip_peril_ctrl,
549 .ctrlbit = (1 << 11),
550 }, {
551 .name = "i2c",
552 .id = 6,
553 .parent = &clk_aclk_100.clk,
554 .enable = s5pv310_clk_ip_peril_ctrl,
555 .ctrlbit = (1 << 12),
556 }, {
557 .name = "i2c",
558 .id = 7,
559 .parent = &clk_aclk_100.clk,
560 .enable = s5pv310_clk_ip_peril_ctrl,
561 .ctrlbit = (1 << 13),
562 },
350}; 563};
351 564
352static struct clk init_clocks[] = { 565static struct clk init_clocks[] = {
@@ -387,6 +600,9 @@ static struct clk *clkset_group_list[] = {
387 [0] = &clk_ext_xtal_mux, 600 [0] = &clk_ext_xtal_mux,
388 [1] = &clk_xusbxti, 601 [1] = &clk_xusbxti,
389 [2] = &clk_sclk_hdmi27m, 602 [2] = &clk_sclk_hdmi27m,
603 [3] = &clk_sclk_usbphy0,
604 [4] = &clk_sclk_usbphy1,
605 [5] = &clk_sclk_hdmiphy,
390 [6] = &clk_mout_mpll.clk, 606 [6] = &clk_mout_mpll.clk,
391 [7] = &clk_mout_epll.clk, 607 [7] = &clk_mout_epll.clk,
392 [8] = &clk_sclk_vpll.clk, 608 [8] = &clk_sclk_vpll.clk,
@@ -397,6 +613,104 @@ static struct clksrc_sources clkset_group = {
397 .nr_sources = ARRAY_SIZE(clkset_group_list), 613 .nr_sources = ARRAY_SIZE(clkset_group_list),
398}; 614};
399 615
616static struct clk *clkset_mout_g2d0_list[] = {
617 [0] = &clk_mout_mpll.clk,
618 [1] = &clk_sclk_apll.clk,
619};
620
621static struct clksrc_sources clkset_mout_g2d0 = {
622 .sources = clkset_mout_g2d0_list,
623 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
624};
625
626static struct clksrc_clk clk_mout_g2d0 = {
627 .clk = {
628 .name = "mout_g2d0",
629 .id = -1,
630 },
631 .sources = &clkset_mout_g2d0,
632 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
633};
634
635static struct clk *clkset_mout_g2d1_list[] = {
636 [0] = &clk_mout_epll.clk,
637 [1] = &clk_sclk_vpll.clk,
638};
639
640static struct clksrc_sources clkset_mout_g2d1 = {
641 .sources = clkset_mout_g2d1_list,
642 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
643};
644
645static struct clksrc_clk clk_mout_g2d1 = {
646 .clk = {
647 .name = "mout_g2d1",
648 .id = -1,
649 },
650 .sources = &clkset_mout_g2d1,
651 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
652};
653
654static struct clk *clkset_mout_g2d_list[] = {
655 [0] = &clk_mout_g2d0.clk,
656 [1] = &clk_mout_g2d1.clk,
657};
658
659static struct clksrc_sources clkset_mout_g2d = {
660 .sources = clkset_mout_g2d_list,
661 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
662};
663
664static struct clksrc_clk clk_dout_mmc0 = {
665 .clk = {
666 .name = "dout_mmc0",
667 .id = -1,
668 },
669 .sources = &clkset_group,
670 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
671 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
672};
673
674static struct clksrc_clk clk_dout_mmc1 = {
675 .clk = {
676 .name = "dout_mmc1",
677 .id = -1,
678 },
679 .sources = &clkset_group,
680 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
681 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
682};
683
684static struct clksrc_clk clk_dout_mmc2 = {
685 .clk = {
686 .name = "dout_mmc2",
687 .id = -1,
688 },
689 .sources = &clkset_group,
690 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
691 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
692};
693
694static struct clksrc_clk clk_dout_mmc3 = {
695 .clk = {
696 .name = "dout_mmc3",
697 .id = -1,
698 },
699 .sources = &clkset_group,
700 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
701 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
702};
703
704static struct clksrc_clk clk_dout_mmc4 = {
705 .clk = {
706 .name = "dout_mmc4",
707 .id = -1,
708 },
709 .sources = &clkset_group,
710 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
711 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
712};
713
400static struct clksrc_clk clksrcs[] = { 714static struct clksrc_clk clksrcs[] = {
401 { 715 {
402 .clk = { 716 .clk = {
@@ -448,7 +762,200 @@ static struct clksrc_clk clksrcs[] = {
448 .sources = &clkset_group, 762 .sources = &clkset_group,
449 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 }, 763 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
450 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 }, 764 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
451 }, 765 }, {
766 .clk = {
767 .name = "sclk_csis",
768 .id = 0,
769 .enable = s5pv310_clksrc_mask_cam_ctrl,
770 .ctrlbit = (1 << 24),
771 },
772 .sources = &clkset_group,
773 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
774 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
775 }, {
776 .clk = {
777 .name = "sclk_csis",
778 .id = 1,
779 .enable = s5pv310_clksrc_mask_cam_ctrl,
780 .ctrlbit = (1 << 28),
781 },
782 .sources = &clkset_group,
783 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
784 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
785 }, {
786 .clk = {
787 .name = "sclk_cam",
788 .id = 0,
789 .enable = s5pv310_clksrc_mask_cam_ctrl,
790 .ctrlbit = (1 << 16),
791 },
792 .sources = &clkset_group,
793 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
794 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
795 }, {
796 .clk = {
797 .name = "sclk_cam",
798 .id = 1,
799 .enable = s5pv310_clksrc_mask_cam_ctrl,
800 .ctrlbit = (1 << 20),
801 },
802 .sources = &clkset_group,
803 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
804 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
805 }, {
806 .clk = {
807 .name = "sclk_fimc",
808 .id = 0,
809 .enable = s5pv310_clksrc_mask_cam_ctrl,
810 .ctrlbit = (1 << 0),
811 },
812 .sources = &clkset_group,
813 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
814 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
815 }, {
816 .clk = {
817 .name = "sclk_fimc",
818 .id = 1,
819 .enable = s5pv310_clksrc_mask_cam_ctrl,
820 .ctrlbit = (1 << 4),
821 },
822 .sources = &clkset_group,
823 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
824 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
825 }, {
826 .clk = {
827 .name = "sclk_fimc",
828 .id = 2,
829 .enable = s5pv310_clksrc_mask_cam_ctrl,
830 .ctrlbit = (1 << 8),
831 },
832 .sources = &clkset_group,
833 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
834 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
835 }, {
836 .clk = {
837 .name = "sclk_fimc",
838 .id = 3,
839 .enable = s5pv310_clksrc_mask_cam_ctrl,
840 .ctrlbit = (1 << 12),
841 },
842 .sources = &clkset_group,
843 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
844 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
845 }, {
846 .clk = {
847 .name = "sclk_fimd",
848 .id = 0,
849 .enable = s5pv310_clksrc_mask_lcd0_ctrl,
850 .ctrlbit = (1 << 0),
851 },
852 .sources = &clkset_group,
853 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
854 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
855 }, {
856 .clk = {
857 .name = "sclk_fimd",
858 .id = 1,
859 .enable = s5pv310_clksrc_mask_lcd1_ctrl,
860 .ctrlbit = (1 << 0),
861 },
862 .sources = &clkset_group,
863 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
864 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
865 }, {
866 .clk = {
867 .name = "sclk_sata",
868 .id = -1,
869 .enable = s5pv310_clksrc_mask_fsys_ctrl,
870 .ctrlbit = (1 << 24),
871 },
872 .sources = &clkset_mout_corebus,
873 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
874 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
875 }, {
876 .clk = {
877 .name = "sclk_spi",
878 .id = 0,
879 .enable = s5pv310_clksrc_mask_peril1_ctrl,
880 .ctrlbit = (1 << 16),
881 },
882 .sources = &clkset_group,
883 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
884 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
885 }, {
886 .clk = {
887 .name = "sclk_spi",
888 .id = 1,
889 .enable = s5pv310_clksrc_mask_peril1_ctrl,
890 .ctrlbit = (1 << 20),
891 },
892 .sources = &clkset_group,
893 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
894 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
895 }, {
896 .clk = {
897 .name = "sclk_spi",
898 .id = 2,
899 .enable = s5pv310_clksrc_mask_peril1_ctrl,
900 .ctrlbit = (1 << 24),
901 },
902 .sources = &clkset_group,
903 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
904 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
905 }, {
906 .clk = {
907 .name = "sclk_fimg2d",
908 .id = -1,
909 },
910 .sources = &clkset_mout_g2d,
911 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
912 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
913 }, {
914 .clk = {
915 .name = "sclk_mmc",
916 .id = 0,
917 .parent = &clk_dout_mmc0.clk,
918 .enable = s5pv310_clksrc_mask_fsys_ctrl,
919 .ctrlbit = (1 << 0),
920 },
921 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
922 }, {
923 .clk = {
924 .name = "sclk_mmc",
925 .id = 1,
926 .parent = &clk_dout_mmc1.clk,
927 .enable = s5pv310_clksrc_mask_fsys_ctrl,
928 .ctrlbit = (1 << 4),
929 },
930 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
931 }, {
932 .clk = {
933 .name = "sclk_mmc",
934 .id = 2,
935 .parent = &clk_dout_mmc2.clk,
936 .enable = s5pv310_clksrc_mask_fsys_ctrl,
937 .ctrlbit = (1 << 8),
938 },
939 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
940 }, {
941 .clk = {
942 .name = "sclk_mmc",
943 .id = 3,
944 .parent = &clk_dout_mmc3.clk,
945 .enable = s5pv310_clksrc_mask_fsys_ctrl,
946 .ctrlbit = (1 << 12),
947 },
948 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
949 }, {
950 .clk = {
951 .name = "sclk_mmc",
952 .id = 4,
953 .parent = &clk_dout_mmc4.clk,
954 .enable = s5pv310_clksrc_mask_fsys_ctrl,
955 .ctrlbit = (1 << 16),
956 },
957 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
958 }
452}; 959};
453 960
454/* Clock initialization code */ 961/* Clock initialization code */
@@ -464,8 +971,6 @@ static struct clksrc_clk *sysclks[] = {
464 &clk_aclk_cores, 971 &clk_aclk_cores,
465 &clk_aclk_corem1, 972 &clk_aclk_corem1,
466 &clk_periphclk, 973 &clk_periphclk,
467 &clk_atclk,
468 &clk_pclk_dbg,
469 &clk_mout_corebus, 974 &clk_mout_corebus,
470 &clk_sclk_dmc, 975 &clk_sclk_dmc,
471 &clk_aclk_cored, 976 &clk_aclk_cored,
@@ -478,6 +983,11 @@ static struct clksrc_clk *sysclks[] = {
478 &clk_aclk_100, 983 &clk_aclk_100,
479 &clk_aclk_160, 984 &clk_aclk_160,
480 &clk_aclk_133, 985 &clk_aclk_133,
986 &clk_dout_mmc0,
987 &clk_dout_mmc1,
988 &clk_dout_mmc2,
989 &clk_dout_mmc3,
990 &clk_dout_mmc4,
481}; 991};
482 992
483void __init_or_cpufreq s5pv310_setup_clocks(void) 993void __init_or_cpufreq s5pv310_setup_clocks(void)
@@ -490,15 +1000,11 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
490 unsigned long vpllsrc; 1000 unsigned long vpllsrc;
491 unsigned long xtal; 1001 unsigned long xtal;
492 unsigned long armclk; 1002 unsigned long armclk;
493 unsigned long aclk_corem0;
494 unsigned long aclk_cores;
495 unsigned long aclk_corem1;
496 unsigned long periphclk;
497 unsigned long sclk_dmc; 1003 unsigned long sclk_dmc;
498 unsigned long aclk_cored; 1004 unsigned long aclk_200;
499 unsigned long aclk_corep; 1005 unsigned long aclk_100;
500 unsigned long aclk_acp; 1006 unsigned long aclk_160;
501 unsigned long pclk_acp; 1007 unsigned long aclk_133;
502 unsigned int ptr; 1008 unsigned int ptr;
503 1009
504 printk(KERN_DEBUG "%s: registering clocks\n", __func__); 1010 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
@@ -529,26 +1035,21 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
529 apll, mpll, epll, vpll); 1035 apll, mpll, epll, vpll);
530 1036
531 armclk = clk_get_rate(&clk_armclk.clk); 1037 armclk = clk_get_rate(&clk_armclk.clk);
532 aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
533 aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
534 aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
535 periphclk = clk_get_rate(&clk_periphclk.clk);
536 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk); 1038 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
537 aclk_cored = clk_get_rate(&clk_aclk_cored.clk); 1039
538 aclk_corep = clk_get_rate(&clk_aclk_corep.clk); 1040 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
539 aclk_acp = clk_get_rate(&clk_aclk_acp.clk); 1041 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
540 pclk_acp = clk_get_rate(&clk_pclk_acp.clk); 1042 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
541 1043 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
542 printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n" 1044
543 "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n" 1045 printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
544 "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld", 1046 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
545 armclk, aclk_corem0, aclk_cores, aclk_corem1, 1047 armclk, sclk_dmc, aclk_200,
546 periphclk, sclk_dmc, aclk_cored, aclk_corep, 1048 aclk_100, aclk_160, aclk_133);
547 aclk_acp, pclk_acp);
548 1049
549 clk_f.rate = armclk; 1050 clk_f.rate = armclk;
550 clk_h.rate = sclk_dmc; 1051 clk_h.rate = sclk_dmc;
551 clk_p.rate = periphclk; 1052 clk_p.rate = aclk_100;
552 1053
553 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) 1054 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
554 s3c_set_clksrc(&clksrcs[ptr], true); 1055 s3c_set_clksrc(&clksrcs[ptr], true);
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index 4add39853ff..82ce4aa6d61 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -15,10 +15,12 @@
15#include <asm/mach/irq.h> 15#include <asm/mach/irq.h>
16 16
17#include <asm/proc-fns.h> 17#include <asm/proc-fns.h>
18#include <asm/hardware/cache-l2x0.h>
18 19
19#include <plat/cpu.h> 20#include <plat/cpu.h>
20#include <plat/clock.h> 21#include <plat/clock.h>
21#include <plat/s5pv310.h> 22#include <plat/s5pv310.h>
23#include <plat/sdhci.h>
22 24
23#include <mach/regs-irq.h> 25#include <mach/regs-irq.h>
24 26
@@ -56,15 +58,30 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
56 .length = SZ_4K, 58 .length = SZ_4K,
57 .type = MT_DEVICE, 59 .type = MT_DEVICE,
58 }, { 60 }, {
59 .virtual = (unsigned long)S5P_VA_GPIO, 61 .virtual = (unsigned long)S5P_VA_GPIO1,
60 .pfn = __phys_to_pfn(S5PV310_PA_GPIO1), 62 .pfn = __phys_to_pfn(S5PV310_PA_GPIO1),
61 .length = SZ_4K, 63 .length = SZ_4K,
62 .type = MT_DEVICE, 64 .type = MT_DEVICE,
63 }, { 65 }, {
66 .virtual = (unsigned long)S5P_VA_GPIO2,
67 .pfn = __phys_to_pfn(S5PV310_PA_GPIO2),
68 .length = SZ_4K,
69 .type = MT_DEVICE,
70 }, {
71 .virtual = (unsigned long)S5P_VA_GPIO3,
72 .pfn = __phys_to_pfn(S5PV310_PA_GPIO3),
73 .length = SZ_256,
74 .type = MT_DEVICE,
75 }, {
64 .virtual = (unsigned long)S3C_VA_UART, 76 .virtual = (unsigned long)S3C_VA_UART,
65 .pfn = __phys_to_pfn(S3C_PA_UART), 77 .pfn = __phys_to_pfn(S3C_PA_UART),
66 .length = SZ_512K, 78 .length = SZ_512K,
67 .type = MT_DEVICE, 79 .type = MT_DEVICE,
80 }, {
81 .virtual = (unsigned long)S5P_VA_SROMC,
82 .pfn = __phys_to_pfn(S5PV310_PA_SROMC),
83 .length = SZ_4K,
84 .type = MT_DEVICE,
68 }, 85 },
69}; 86};
70 87
@@ -83,6 +100,12 @@ static void s5pv310_idle(void)
83void __init s5pv310_map_io(void) 100void __init s5pv310_map_io(void)
84{ 101{
85 iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc)); 102 iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
103
104 /* initialize device information early */
105 s5pv310_default_sdhci0();
106 s5pv310_default_sdhci1();
107 s5pv310_default_sdhci2();
108 s5pv310_default_sdhci3();
86} 109}
87 110
88void __init s5pv310_init_clocks(int xtal) 111void __init s5pv310_init_clocks(int xtal)
@@ -131,6 +154,28 @@ static int __init s5pv310_core_init(void)
131 154
132core_initcall(s5pv310_core_init); 155core_initcall(s5pv310_core_init);
133 156
157#ifdef CONFIG_CACHE_L2X0
158static int __init s5pv310_l2x0_cache_init(void)
159{
160 /* TAG, Data Latency Control: 2cycle */
161 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
162 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
163
164 /* L2X0 Prefetch Control */
165 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
166
167 /* L2X0 Power Control */
168 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
169 S5P_VA_L2CC + L2X0_POWER_CTRL);
170
171 l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
172
173 return 0;
174}
175
176early_initcall(s5pv310_l2x0_cache_init);
177#endif
178
134int __init s5pv310_init(void) 179int __init s5pv310_init(void)
135{ 180{
136 printk(KERN_INFO "S5PV310: Initializing architecture\n"); 181 printk(KERN_INFO "S5PV310: Initializing architecture\n");
diff --git a/arch/arm/mach-s5pv310/gpiolib.c b/arch/arm/mach-s5pv310/gpiolib.c
new file mode 100644
index 00000000000..55217b8923e
--- /dev/null
+++ b/arch/arm/mach-s5pv310/gpiolib.c
@@ -0,0 +1,304 @@
1/* linux/arch/arm/mach-s5pv310/gpiolib.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19
20#include <plat/gpio-core.h>
21#include <plat/gpio-cfg.h>
22#include <plat/gpio-cfg-helpers.h>
23
24static struct s3c_gpio_cfg gpio_cfg = {
25 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
26 .set_pull = s3c_gpio_setpull_updown,
27 .get_pull = s3c_gpio_getpull_updown,
28};
29
30static struct s3c_gpio_cfg gpio_cfg_noint = {
31 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
32 .set_pull = s3c_gpio_setpull_updown,
33 .get_pull = s3c_gpio_getpull_updown,
34};
35
36/*
37 * Following are the gpio banks in v310.
38 *
39 * The 'config' member when left to NULL, is initialized to the default
40 * structure gpio_cfg in the init function below.
41 *
42 * The 'base' member is also initialized in the init function below.
43 * Note: The initialization of 'base' member of s3c_gpio_chip structure
44 * uses the above macro and depends on the banks being listed in order here.
45 */
46static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = {
47 {
48 .chip = {
49 .base = S5PV310_GPA0(0),
50 .ngpio = S5PV310_GPIO_A0_NR,
51 .label = "GPA0",
52 },
53 }, {
54 .chip = {
55 .base = S5PV310_GPA1(0),
56 .ngpio = S5PV310_GPIO_A1_NR,
57 .label = "GPA1",
58 },
59 }, {
60 .chip = {
61 .base = S5PV310_GPB(0),
62 .ngpio = S5PV310_GPIO_B_NR,
63 .label = "GPB",
64 },
65 }, {
66 .chip = {
67 .base = S5PV310_GPC0(0),
68 .ngpio = S5PV310_GPIO_C0_NR,
69 .label = "GPC0",
70 },
71 }, {
72 .chip = {
73 .base = S5PV310_GPC1(0),
74 .ngpio = S5PV310_GPIO_C1_NR,
75 .label = "GPC1",
76 },
77 }, {
78 .chip = {
79 .base = S5PV310_GPD0(0),
80 .ngpio = S5PV310_GPIO_D0_NR,
81 .label = "GPD0",
82 },
83 }, {
84 .chip = {
85 .base = S5PV310_GPD1(0),
86 .ngpio = S5PV310_GPIO_D1_NR,
87 .label = "GPD1",
88 },
89 }, {
90 .chip = {
91 .base = S5PV310_GPE0(0),
92 .ngpio = S5PV310_GPIO_E0_NR,
93 .label = "GPE0",
94 },
95 }, {
96 .chip = {
97 .base = S5PV310_GPE1(0),
98 .ngpio = S5PV310_GPIO_E1_NR,
99 .label = "GPE1",
100 },
101 }, {
102 .chip = {
103 .base = S5PV310_GPE2(0),
104 .ngpio = S5PV310_GPIO_E2_NR,
105 .label = "GPE2",
106 },
107 }, {
108 .chip = {
109 .base = S5PV310_GPE3(0),
110 .ngpio = S5PV310_GPIO_E3_NR,
111 .label = "GPE3",
112 },
113 }, {
114 .chip = {
115 .base = S5PV310_GPE4(0),
116 .ngpio = S5PV310_GPIO_E4_NR,
117 .label = "GPE4",
118 },
119 }, {
120 .chip = {
121 .base = S5PV310_GPF0(0),
122 .ngpio = S5PV310_GPIO_F0_NR,
123 .label = "GPF0",
124 },
125 }, {
126 .chip = {
127 .base = S5PV310_GPF1(0),
128 .ngpio = S5PV310_GPIO_F1_NR,
129 .label = "GPF1",
130 },
131 }, {
132 .chip = {
133 .base = S5PV310_GPF2(0),
134 .ngpio = S5PV310_GPIO_F2_NR,
135 .label = "GPF2",
136 },
137 }, {
138 .chip = {
139 .base = S5PV310_GPF3(0),
140 .ngpio = S5PV310_GPIO_F3_NR,
141 .label = "GPF3",
142 },
143 },
144};
145
146static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
147 {
148 .chip = {
149 .base = S5PV310_GPJ0(0),
150 .ngpio = S5PV310_GPIO_J0_NR,
151 .label = "GPJ0",
152 },
153 }, {
154 .chip = {
155 .base = S5PV310_GPJ1(0),
156 .ngpio = S5PV310_GPIO_J1_NR,
157 .label = "GPJ1",
158 },
159 }, {
160 .chip = {
161 .base = S5PV310_GPK0(0),
162 .ngpio = S5PV310_GPIO_K0_NR,
163 .label = "GPK0",
164 },
165 }, {
166 .chip = {
167 .base = S5PV310_GPK1(0),
168 .ngpio = S5PV310_GPIO_K1_NR,
169 .label = "GPK1",
170 },
171 }, {
172 .chip = {
173 .base = S5PV310_GPK2(0),
174 .ngpio = S5PV310_GPIO_K2_NR,
175 .label = "GPK2",
176 },
177 }, {
178 .chip = {
179 .base = S5PV310_GPK3(0),
180 .ngpio = S5PV310_GPIO_K3_NR,
181 .label = "GPK3",
182 },
183 }, {
184 .chip = {
185 .base = S5PV310_GPL0(0),
186 .ngpio = S5PV310_GPIO_L0_NR,
187 .label = "GPL0",
188 },
189 }, {
190 .chip = {
191 .base = S5PV310_GPL1(0),
192 .ngpio = S5PV310_GPIO_L1_NR,
193 .label = "GPL1",
194 },
195 }, {
196 .chip = {
197 .base = S5PV310_GPL2(0),
198 .ngpio = S5PV310_GPIO_L2_NR,
199 .label = "GPL2",
200 },
201 }, {
202 .base = (S5P_VA_GPIO2 + 0xC00),
203 .config = &gpio_cfg_noint,
204 .irq_base = IRQ_EINT(0),
205 .chip = {
206 .base = S5PV310_GPX0(0),
207 .ngpio = S5PV310_GPIO_X0_NR,
208 .label = "GPX0",
209 .to_irq = samsung_gpiolib_to_irq,
210 },
211 }, {
212 .base = (S5P_VA_GPIO2 + 0xC20),
213 .config = &gpio_cfg_noint,
214 .irq_base = IRQ_EINT(8),
215 .chip = {
216 .base = S5PV310_GPX1(0),
217 .ngpio = S5PV310_GPIO_X1_NR,
218 .label = "GPX1",
219 .to_irq = samsung_gpiolib_to_irq,
220 },
221 }, {
222 .base = (S5P_VA_GPIO2 + 0xC40),
223 .config = &gpio_cfg_noint,
224 .irq_base = IRQ_EINT(16),
225 .chip = {
226 .base = S5PV310_GPX2(0),
227 .ngpio = S5PV310_GPIO_X2_NR,
228 .label = "GPX2",
229 .to_irq = samsung_gpiolib_to_irq,
230 },
231 }, {
232 .base = (S5P_VA_GPIO2 + 0xC60),
233 .config = &gpio_cfg_noint,
234 .irq_base = IRQ_EINT(24),
235 .chip = {
236 .base = S5PV310_GPX3(0),
237 .ngpio = S5PV310_GPIO_X3_NR,
238 .label = "GPX3",
239 .to_irq = samsung_gpiolib_to_irq,
240 },
241 },
242};
243
244static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = {
245 {
246 .chip = {
247 .base = S5PV310_GPZ(0),
248 .ngpio = S5PV310_GPIO_Z_NR,
249 .label = "GPZ",
250 },
251 },
252};
253
254static __init int s5pv310_gpiolib_init(void)
255{
256 struct s3c_gpio_chip *chip;
257 int i;
258 int nr_chips;
259
260 /* GPIO part 1 */
261
262 chip = s5pv310_gpio_part1_4bit;
263 nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit);
264
265 for (i = 0; i < nr_chips; i++, chip++) {
266 if (chip->config == NULL)
267 chip->config = &gpio_cfg;
268 if (chip->base == NULL)
269 chip->base = S5P_VA_GPIO1 + (i) * 0x20;
270 }
271
272 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips);
273
274 /* GPIO part 2 */
275
276 chip = s5pv310_gpio_part2_4bit;
277 nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit);
278
279 for (i = 0; i < nr_chips; i++, chip++) {
280 if (chip->config == NULL)
281 chip->config = &gpio_cfg;
282 if (chip->base == NULL)
283 chip->base = S5P_VA_GPIO2 + (i) * 0x20;
284 }
285
286 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips);
287
288 /* GPIO part 3 */
289
290 chip = s5pv310_gpio_part3_4bit;
291 nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit);
292
293 for (i = 0; i < nr_chips; i++, chip++) {
294 if (chip->config == NULL)
295 chip->config = &gpio_cfg;
296 if (chip->base == NULL)
297 chip->base = S5P_VA_GPIO3 + (i) * 0x20;
298 }
299
300 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips);
301
302 return 0;
303}
304core_initcall(s5pv310_gpiolib_init);
diff --git a/arch/arm/mach-s5pv310/hotplug.c b/arch/arm/mach-s5pv310/hotplug.c
new file mode 100644
index 00000000000..03652c3605f
--- /dev/null
+++ b/arch/arm/mach-s5pv310/hotplug.c
@@ -0,0 +1,144 @@
1/* linux arch/arm/mach-s5pv310/hotplug.c
2 *
3 * Cloned from linux/arch/arm/mach-realview/hotplug.c
4 *
5 * Copyright (C) 2002 ARM Ltd.
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/smp.h>
16#include <linux/completion.h>
17
18#include <asm/cacheflush.h>
19
20extern volatile int pen_release;
21
22static DECLARE_COMPLETION(cpu_killed);
23
24static inline void cpu_enter_lowpower(void)
25{
26 unsigned int v;
27
28 flush_cache_all();
29 asm volatile(
30 " mcr p15, 0, %1, c7, c5, 0\n"
31 " mcr p15, 0, %1, c7, c10, 4\n"
32 /*
33 * Turn off coherency
34 */
35 " mrc p15, 0, %0, c1, c0, 1\n"
36 " bic %0, %0, #0x20\n"
37 " mcr p15, 0, %0, c1, c0, 1\n"
38 " mrc p15, 0, %0, c1, c0, 0\n"
39 " bic %0, %0, #0x04\n"
40 " mcr p15, 0, %0, c1, c0, 0\n"
41 : "=&r" (v)
42 : "r" (0)
43 : "cc");
44}
45
46static inline void cpu_leave_lowpower(void)
47{
48 unsigned int v;
49
50 asm volatile(
51 "mrc p15, 0, %0, c1, c0, 0\n"
52 " orr %0, %0, #0x04\n"
53 " mcr p15, 0, %0, c1, c0, 0\n"
54 " mrc p15, 0, %0, c1, c0, 1\n"
55 " orr %0, %0, #0x20\n"
56 " mcr p15, 0, %0, c1, c0, 1\n"
57 : "=&r" (v)
58 :
59 : "cc");
60}
61
62static inline void platform_do_lowpower(unsigned int cpu)
63{
64 /*
65 * there is no power-control hardware on this platform, so all
66 * we can do is put the core into WFI; this is safe as the calling
67 * code will have already disabled interrupts
68 */
69 for (;;) {
70 /*
71 * here's the WFI
72 */
73 asm(".word 0xe320f003\n"
74 :
75 :
76 : "memory", "cc");
77
78 if (pen_release == cpu) {
79 /*
80 * OK, proper wakeup, we're done
81 */
82 break;
83 }
84
85 /*
86 * getting here, means that we have come out of WFI without
87 * having been woken up - this shouldn't happen
88 *
89 * The trouble is, letting people know about this is not really
90 * possible, since we are currently running incoherently, and
91 * therefore cannot safely call printk() or anything else
92 */
93#ifdef DEBUG
94 printk(KERN_WARN "CPU%u: spurious wakeup call\n", cpu);
95#endif
96 }
97}
98
99int platform_cpu_kill(unsigned int cpu)
100{
101 return wait_for_completion_timeout(&cpu_killed, 5000);
102}
103
104/*
105 * platform-specific code to shutdown a CPU
106 *
107 * Called with IRQs disabled
108 */
109void platform_cpu_die(unsigned int cpu)
110{
111#ifdef DEBUG
112 unsigned int this_cpu = hard_smp_processor_id();
113
114 if (cpu != this_cpu) {
115 printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
116 this_cpu, cpu);
117 BUG();
118 }
119#endif
120
121 printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
122 complete(&cpu_killed);
123
124 /*
125 * we're ready for shutdown now, so do it
126 */
127 cpu_enter_lowpower();
128 platform_do_lowpower(cpu);
129
130 /*
131 * bring this CPU back into the world of cache
132 * coherency, and then restore interrupts
133 */
134 cpu_leave_lowpower();
135}
136
137int platform_cpu_disable(unsigned int cpu)
138{
139 /*
140 * we don't allow CPU 0 to be shutdown (it is still too special
141 * e.g. clock tick interrupts)
142 */
143 return cpu == 0 ? -EPERM : 0;
144}
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
index 471fc3bb199..99e7dad8a85 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -3,7 +3,7 @@
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com/
5 * 5 *
6 * S5PV210 - IRQ definitions 6 * S5PV310 - IRQ definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -60,6 +60,9 @@
60#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3) 60#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3)
61#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4) 61#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4)
62 62
63#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
64#define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
65
63#define IRQ_UART0 COMBINER_IRQ(26, 0) 66#define IRQ_UART0 COMBINER_IRQ(26, 0)
64#define IRQ_UART1 COMBINER_IRQ(26, 1) 67#define IRQ_UART1 COMBINER_IRQ(26, 1)
65#define IRQ_UART2 COMBINER_IRQ(26, 2) 68#define IRQ_UART2 COMBINER_IRQ(26, 2)
@@ -67,13 +70,46 @@
67#define IRQ_UART4 COMBINER_IRQ(26, 4) 70#define IRQ_UART4 COMBINER_IRQ(26, 4)
68 71
69#define IRQ_IIC COMBINER_IRQ(27, 0) 72#define IRQ_IIC COMBINER_IRQ(27, 0)
73#define IRQ_IIC1 COMBINER_IRQ(27, 1)
74#define IRQ_IIC2 COMBINER_IRQ(27, 2)
75#define IRQ_IIC3 COMBINER_IRQ(27, 3)
76#define IRQ_IIC4 COMBINER_IRQ(27, 4)
77#define IRQ_IIC5 COMBINER_IRQ(27, 5)
78#define IRQ_IIC6 COMBINER_IRQ(27, 6)
79#define IRQ_IIC7 COMBINER_IRQ(27, 7)
80
81#define IRQ_HSMMC0 COMBINER_IRQ(29, 0)
82#define IRQ_HSMMC1 COMBINER_IRQ(29, 1)
83#define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
84#define IRQ_HSMMC3 COMBINER_IRQ(29, 3)
70 85
71#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) 86#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
72 87
73/* Set the default NR_IRQS */ 88#define IRQ_EINT4 COMBINER_IRQ(37, 0)
89#define IRQ_EINT5 COMBINER_IRQ(37, 1)
90#define IRQ_EINT6 COMBINER_IRQ(37, 2)
91#define IRQ_EINT7 COMBINER_IRQ(37, 3)
92#define IRQ_EINT8 COMBINER_IRQ(38, 0)
93
94#define IRQ_EINT9 COMBINER_IRQ(38, 1)
95#define IRQ_EINT10 COMBINER_IRQ(38, 2)
96#define IRQ_EINT11 COMBINER_IRQ(38, 3)
97#define IRQ_EINT12 COMBINER_IRQ(38, 4)
98#define IRQ_EINT13 COMBINER_IRQ(38, 5)
99#define IRQ_EINT14 COMBINER_IRQ(38, 6)
100#define IRQ_EINT15 COMBINER_IRQ(38, 7)
101
102#define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
74 103
75#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0) 104#define MAX_COMBINER_NR 40
105
106#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
107
108#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0)
109#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16)
110
111/* Set the default NR_IRQS */
76 112
77#define MAX_COMBINER_NR 39 113#define NR_IRQS (S5P_IRQ_EINT_BASE + 32)
78 114
79#endif /* __ASM_ARCH_IRQS_H */ 115#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index aff6d23624b..7acf4e77e92 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -25,6 +25,8 @@
25 25
26#define S5PV310_PA_SYSRAM (0x02025000) 26#define S5PV310_PA_SYSRAM (0x02025000)
27 27
28#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
29
28#define S5PC210_PA_ONENAND (0x0C000000) 30#define S5PC210_PA_ONENAND (0x0C000000)
29#define S5P_PA_ONENAND S5PC210_PA_ONENAND 31#define S5P_PA_ONENAND S5PC210_PA_ONENAND
30 32
@@ -34,12 +36,13 @@
34#define S5PV310_PA_CHIPID (0x10000000) 36#define S5PV310_PA_CHIPID (0x10000000)
35#define S5P_PA_CHIPID S5PV310_PA_CHIPID 37#define S5P_PA_CHIPID S5PV310_PA_CHIPID
36 38
37#define S5PV310_PA_SYSCON (0x10020000) 39#define S5PV310_PA_SYSCON (0x10010000)
38#define S5P_PA_SYSCON S5PV310_PA_SYSCON 40#define S5P_PA_SYSCON S5PV310_PA_SYSCON
39 41
40#define S5PV310_PA_CMU (0x10030000) 42#define S5PV310_PA_CMU (0x10030000)
41 43
42#define S5PV310_PA_WATCHDOG (0x10060000) 44#define S5PV310_PA_WATCHDOG (0x10060000)
45#define S5PV310_PA_RTC (0x10070000)
43 46
44#define S5PV310_PA_COMBINER (0x10448000) 47#define S5PV310_PA_COMBINER (0x10448000)
45 48
@@ -55,6 +58,8 @@
55 58
56#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 59#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
57 60
61#define S5PV310_PA_SROMC (0x12570000)
62
58#define S5PV310_PA_UART (0x13800000) 63#define S5PV310_PA_UART (0x13800000)
59 64
60#define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET)) 65#define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET))
@@ -66,7 +71,7 @@
66 71
67#define S5P_SZ_UART SZ_256 72#define S5P_SZ_UART SZ_256
68 73
69#define S5PV310_PA_IIC0 (0x13860000) 74#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
70 75
71#define S5PV310_PA_TIMER (0x139D0000) 76#define S5PV310_PA_TIMER (0x139D0000)
72#define S5P_PA_TIMER S5PV310_PA_TIMER 77#define S5P_PA_TIMER S5PV310_PA_TIMER
@@ -80,7 +85,15 @@
80#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1) 85#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
81#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2) 86#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
82#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3) 87#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
83#define S3C_PA_IIC S5PV310_PA_IIC0 88#define S3C_PA_IIC S5PV310_PA_IIC(0)
89#define S3C_PA_IIC1 S5PV310_PA_IIC(1)
90#define S3C_PA_IIC2 S5PV310_PA_IIC(2)
91#define S3C_PA_IIC3 S5PV310_PA_IIC(3)
92#define S3C_PA_IIC4 S5PV310_PA_IIC(4)
93#define S3C_PA_IIC5 S5PV310_PA_IIC(5)
94#define S3C_PA_IIC6 S5PV310_PA_IIC(6)
95#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
96#define S3C_PA_RTC S5PV310_PA_RTC
84#define S3C_PA_WDT S5PV310_PA_WATCHDOG 97#define S3C_PA_WDT S5PV310_PA_WATCHDOG
85 98
86#endif /* __ASM_ARCH_MAP_H */ 99#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
index 4013553cd9b..f1028cad978 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -26,11 +26,23 @@
26 26
27#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) 27#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
28#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) 28#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
29 29#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
30#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
31#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
32#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
33#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
30#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) 34#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
35#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
31 36
32#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) 37#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
33 38#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
39#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
40#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
41#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
42#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
43#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
44#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
45#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C)
34#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550) 46#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
35#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554) 47#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
36#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558) 48#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
@@ -38,9 +50,21 @@
38#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) 50#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
39#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) 51#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
40 52
53#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
54#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
55#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
56#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
57#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
41#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) 58#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
59#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
42 60
61#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
62#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
63#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
64#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
65#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
43#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) 66#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
67#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
44 68
45#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200) 69#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
46#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500) 70#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500)
@@ -60,4 +84,8 @@
60 84
61#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) 85#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
62 86
87/* Compatibility defines */
88
89#define S5P_EPLL_CON S5P_EPLL_CON0
90
63#endif /* __ASM_ARCH_REGS_CLOCK_H */ 91#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
new file mode 100644
index 00000000000..82e9e0c9d45
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
@@ -0,0 +1,42 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17#include <mach/irqs.h>
18
19#define S5PV310_EINT40CON (S5P_VA_GPIO2 + 0xE00)
20#define S5P_EINT_CON(x) (S5PV310_EINT40CON + ((x) * 0x4))
21
22#define S5PV310_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
23#define S5P_EINT_FLTCON(x) (S5PV310_EINT40FLTCON0 + ((x) * 0x4))
24
25#define S5PV310_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
26#define S5P_EINT_MASK(x) (S5PV310_EINT40MASK + ((x) * 0x4))
27
28#define S5PV310_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
29#define S5P_EINT_PEND(x) (S5PV310_EINT40PEND + ((x) * 0x4))
30
31#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
32
33#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
34
35#define EINT_MODE S3C_GPIO_SFN(0xf)
36
37#define EINT_GPIO_0(x) S5PV310_GPX0(x)
38#define EINT_GPIO_1(x) S5PV310_GPX1(x)
39#define EINT_GPIO_2(x) S5PV310_GPX2(x)
40#define EINT_GPIO_3(x) S5PV310_GPX3(x)
41
42#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-srom.h b/arch/arm/mach-s5pv310/include/mach/regs-srom.h
new file mode 100644
index 00000000000..1898b3e1055
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-srom.h
@@ -0,0 +1,50 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-srom.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - SROMC register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_SROM_H
14#define __ASM_ARCH_REGS_SROM_H __FILE__
15
16#include <mach/map.h>
17
18#define S5PV310_SROMREG(x) (S5P_VA_SROMC + (x))
19
20#define S5PV310_SROM_BW S5PV310_SROMREG(0x0)
21#define S5PV310_SROM_BC0 S5PV310_SROMREG(0x4)
22#define S5PV310_SROM_BC1 S5PV310_SROMREG(0x8)
23#define S5PV310_SROM_BC2 S5PV310_SROMREG(0xc)
24#define S5PV310_SROM_BC3 S5PV310_SROMREG(0x10)
25
26/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
27
28#define S5PV310_SROM_BW__DATAWIDTH__SHIFT 0
29#define S5PV310_SROM_BW__ADDRMODE__SHIFT 1
30#define S5PV310_SROM_BW__WAITENABLE__SHIFT 2
31#define S5PV310_SROM_BW__BYTEENABLE__SHIFT 3
32
33#define S5PV310_SROM_BW__CS_MASK 0xf
34
35#define S5PV310_SROM_BW__NCS0__SHIFT 0
36#define S5PV310_SROM_BW__NCS1__SHIFT 4
37#define S5PV310_SROM_BW__NCS2__SHIFT 8
38#define S5PV310_SROM_BW__NCS3__SHIFT 12
39
40/* applies to same to BCS0 - BCS3 */
41
42#define S5PV310_SROM_BCX__PMC__SHIFT 0
43#define S5PV310_SROM_BCX__TACP__SHIFT 4
44#define S5PV310_SROM_BCX__TCAH__SHIFT 8
45#define S5PV310_SROM_BCX__TCOH__SHIFT 12
46#define S5PV310_SROM_BCX__TACC__SHIFT 16
47#define S5PV310_SROM_BCX__TCOS__SHIFT 24
48#define S5PV310_SROM_BCX__TACS__SHIFT 28
49
50#endif /* __ASM_ARCH_REGS_SROM_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
index 256f221edf3..65759fb9758 100644
--- a/arch/arm/mach-s5pv310/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
@@ -17,6 +17,6 @@
17#ifndef __ASM_ARCH_VMALLOC_H 17#ifndef __ASM_ARCH_VMALLOC_H
18#define __ASM_ARCH_VMALLOC_H __FILE__ 18#define __ASM_ARCH_VMALLOC_H __FILE__
19 19
20#define VMALLOC_END (0xF0000000UL) 20#define VMALLOC_END 0xF6000000UL
21 21
22#endif /* __ASM_ARCH_VMALLOC_H */ 22#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c
index 0f7052164f2..c3f88c3faf6 100644
--- a/arch/arm/mach-s5pv310/irq-combiner.c
+++ b/arch/arm/mach-s5pv310/irq-combiner.c
@@ -66,11 +66,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
66 if (status == 0) 66 if (status == 0)
67 goto out; 67 goto out;
68 68
69 for (combiner_irq = 0; combiner_irq < 32; combiner_irq++) { 69 combiner_irq = __ffs(status);
70 if (status & 0x1)
71 break;
72 status >>= 1;
73 }
74 70
75 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31); 71 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
76 if (unlikely(cascade_irq >= NR_IRQS)) 72 if (unlikely(cascade_irq >= NR_IRQS))
diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-s5pv310/irq-eint.c
new file mode 100644
index 00000000000..5877503e92c
--- /dev/null
+++ b/arch/arm/mach-s5pv310/irq-eint.c
@@ -0,0 +1,228 @@
1/* linux/arch/arm/mach-s5pv310/irq-eint.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - IRQ EINT support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/sysdev.h>
18#include <linux/gpio.h>
19
20#include <plat/pm.h>
21#include <plat/cpu.h>
22#include <plat/gpio-cfg.h>
23
24#include <mach/regs-gpio.h>
25
26static DEFINE_SPINLOCK(eint_lock);
27
28static unsigned int eint0_15_data[16];
29
30static unsigned int s5pv310_get_irq_nr(unsigned int number)
31{
32 u32 ret = 0;
33
34 switch (number) {
35 case 0 ... 3:
36 ret = (number + IRQ_EINT0);
37 break;
38 case 4 ... 7:
39 ret = (number + (IRQ_EINT4 - 4));
40 break;
41 case 8 ... 15:
42 ret = (number + (IRQ_EINT8 - 8));
43 break;
44 default:
45 printk(KERN_ERR "number available : %d\n", number);
46 }
47
48 return ret;
49}
50
51static inline void s5pv310_irq_eint_mask(unsigned int irq)
52{
53 u32 mask;
54
55 spin_lock(&eint_lock);
56 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
57 mask |= eint_irq_to_bit(irq);
58 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
59 spin_unlock(&eint_lock);
60}
61
62static void s5pv310_irq_eint_unmask(unsigned int irq)
63{
64 u32 mask;
65
66 spin_lock(&eint_lock);
67 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
68 mask &= ~(eint_irq_to_bit(irq));
69 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
70 spin_unlock(&eint_lock);
71}
72
73static inline void s5pv310_irq_eint_ack(unsigned int irq)
74{
75 __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
76}
77
78static void s5pv310_irq_eint_maskack(unsigned int irq)
79{
80 s5pv310_irq_eint_mask(irq);
81 s5pv310_irq_eint_ack(irq);
82}
83
84static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
85{
86 int offs = EINT_OFFSET(irq);
87 int shift;
88 u32 ctrl, mask;
89 u32 newvalue = 0;
90
91 switch (type) {
92 case IRQ_TYPE_EDGE_RISING:
93 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
94 break;
95
96 case IRQ_TYPE_EDGE_FALLING:
97 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
98 break;
99
100 case IRQ_TYPE_EDGE_BOTH:
101 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
102 break;
103
104 case IRQ_TYPE_LEVEL_LOW:
105 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
106 break;
107
108 case IRQ_TYPE_LEVEL_HIGH:
109 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
110 break;
111
112 default:
113 printk(KERN_ERR "No such irq type %d", type);
114 return -EINVAL;
115 }
116
117 shift = (offs & 0x7) * 4;
118 mask = 0x7 << shift;
119
120 spin_lock(&eint_lock);
121 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
122 ctrl &= ~mask;
123 ctrl |= newvalue << shift;
124 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
125 spin_unlock(&eint_lock);
126
127 switch (offs) {
128 case 0 ... 7:
129 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
130 break;
131 case 8 ... 15:
132 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
133 break;
134 case 16 ... 23:
135 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
136 break;
137 case 24 ... 31:
138 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
139 break;
140 default:
141 printk(KERN_ERR "No such irq number %d", offs);
142 }
143
144 return 0;
145}
146
147static struct irq_chip s5pv310_irq_eint = {
148 .name = "s5pv310-eint",
149 .mask = s5pv310_irq_eint_mask,
150 .unmask = s5pv310_irq_eint_unmask,
151 .mask_ack = s5pv310_irq_eint_maskack,
152 .ack = s5pv310_irq_eint_ack,
153 .set_type = s5pv310_irq_eint_set_type,
154#ifdef CONFIG_PM
155 .set_wake = s3c_irqext_wake,
156#endif
157};
158
159/* s5pv310_irq_demux_eint
160 *
161 * This function demuxes the IRQ from from EINTs 16 to 31.
162 * It is designed to be inlined into the specific handler
163 * s5p_irq_demux_eintX_Y.
164 *
165 * Each EINT pend/mask registers handle eight of them.
166 */
167static inline void s5pv310_irq_demux_eint(unsigned int start)
168{
169 unsigned int irq;
170
171 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
172 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
173
174 status &= ~mask;
175 status &= 0xff;
176
177 while (status) {
178 irq = fls(status) - 1;
179 generic_handle_irq(irq + start);
180 status &= ~(1 << irq);
181 }
182}
183
184static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
185{
186 s5pv310_irq_demux_eint(IRQ_EINT(16));
187 s5pv310_irq_demux_eint(IRQ_EINT(24));
188}
189
190static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
191{
192 u32 *irq_data = get_irq_data(irq);
193 struct irq_chip *chip = get_irq_chip(irq);
194
195 chip->mask(irq);
196
197 if (chip->ack)
198 chip->ack(irq);
199
200 generic_handle_irq(*irq_data);
201
202 chip->unmask(irq);
203}
204
205int __init s5pv310_init_irq_eint(void)
206{
207 int irq;
208
209 for (irq = 0 ; irq <= 31 ; irq++) {
210 set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint);
211 set_irq_handler(IRQ_EINT(irq), handle_level_irq);
212 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
213 }
214
215 set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31);
216
217 for (irq = 0 ; irq <= 15 ; irq++) {
218 eint0_15_data[irq] = IRQ_EINT(irq);
219
220 set_irq_data(s5pv310_get_irq_nr(irq), &eint0_15_data[irq]);
221 set_irq_chained_handler(s5pv310_get_irq_nr(irq),
222 s5pv310_irq_eint0_15);
223 }
224
225 return 0;
226}
227
228arch_initcall(s5pv310_init_irq_eint);
diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c
new file mode 100644
index 00000000000..2b8d4fc52d7
--- /dev/null
+++ b/arch/arm/mach-s5pv310/mach-smdkc210.c
@@ -0,0 +1,202 @@
1/* linux/arch/arm/mach-s5pv310/mach-smdkc210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12#include <linux/gpio.h>
13#include <linux/mmc/host.h>
14#include <linux/platform_device.h>
15#include <linux/smsc911x.h>
16#include <linux/io.h>
17
18#include <asm/mach/arch.h>
19#include <asm/mach-types.h>
20
21#include <plat/regs-serial.h>
22#include <plat/s5pv310.h>
23#include <plat/cpu.h>
24#include <plat/devs.h>
25#include <plat/sdhci.h>
26
27#include <mach/map.h>
28#include <mach/regs-srom.h>
29
30/* Following are default values for UCON, ULCON and UFCON UART registers */
31#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
32 S3C2410_UCON_RXILEVEL | \
33 S3C2410_UCON_TXIRQMODE | \
34 S3C2410_UCON_RXIRQMODE | \
35 S3C2410_UCON_RXFIFO_TOI | \
36 S3C2443_UCON_RXERR_IRQEN)
37
38#define SMDKC210_ULCON_DEFAULT S3C2410_LCON_CS8
39
40#define SMDKC210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
41 S5PV210_UFCON_TXTRIG4 | \
42 S5PV210_UFCON_RXTRIG4)
43
44static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
45 [0] = {
46 .hwport = 0,
47 .flags = 0,
48 .ucon = SMDKC210_UCON_DEFAULT,
49 .ulcon = SMDKC210_ULCON_DEFAULT,
50 .ufcon = SMDKC210_UFCON_DEFAULT,
51 },
52 [1] = {
53 .hwport = 1,
54 .flags = 0,
55 .ucon = SMDKC210_UCON_DEFAULT,
56 .ulcon = SMDKC210_ULCON_DEFAULT,
57 .ufcon = SMDKC210_UFCON_DEFAULT,
58 },
59 [2] = {
60 .hwport = 2,
61 .flags = 0,
62 .ucon = SMDKC210_UCON_DEFAULT,
63 .ulcon = SMDKC210_ULCON_DEFAULT,
64 .ufcon = SMDKC210_UFCON_DEFAULT,
65 },
66 [3] = {
67 .hwport = 3,
68 .flags = 0,
69 .ucon = SMDKC210_UCON_DEFAULT,
70 .ulcon = SMDKC210_ULCON_DEFAULT,
71 .ufcon = SMDKC210_UFCON_DEFAULT,
72 },
73};
74
75static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
76 .cd_type = S3C_SDHCI_CD_GPIO,
77 .ext_cd_gpio = S5PV310_GPK0(2),
78 .ext_cd_gpio_invert = 1,
79 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
80#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
81 .max_width = 8,
82 .host_caps = MMC_CAP_8_BIT_DATA,
83#endif
84};
85
86static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
87 .cd_type = S3C_SDHCI_CD_GPIO,
88 .ext_cd_gpio = S5PV310_GPK0(2),
89 .ext_cd_gpio_invert = 1,
90 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
91};
92
93static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
94 .cd_type = S3C_SDHCI_CD_GPIO,
95 .ext_cd_gpio = S5PV310_GPK2(2),
96 .ext_cd_gpio_invert = 1,
97 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
98#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
99 .max_width = 8,
100 .host_caps = MMC_CAP_8_BIT_DATA,
101#endif
102};
103
104static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
105 .cd_type = S3C_SDHCI_CD_GPIO,
106 .ext_cd_gpio = S5PV310_GPK2(2),
107 .ext_cd_gpio_invert = 1,
108 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
109};
110
111static struct resource smdkc210_smsc911x_resources[] = {
112 [0] = {
113 .start = S5PV310_PA_SROM_BANK(1),
114 .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
115 .flags = IORESOURCE_MEM,
116 },
117 [1] = {
118 .start = IRQ_EINT(5),
119 .end = IRQ_EINT(5),
120 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
121 },
122};
123
124static struct smsc911x_platform_config smsc9215_config = {
125 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
126 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
127 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
128 .phy_interface = PHY_INTERFACE_MODE_MII,
129 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
130};
131
132static struct platform_device smdkc210_smsc911x = {
133 .name = "smsc911x",
134 .id = -1,
135 .num_resources = ARRAY_SIZE(smdkc210_smsc911x_resources),
136 .resource = smdkc210_smsc911x_resources,
137 .dev = {
138 .platform_data = &smsc9215_config,
139 },
140};
141
142static struct platform_device *smdkc210_devices[] __initdata = {
143 &s3c_device_hsmmc0,
144 &s3c_device_hsmmc1,
145 &s3c_device_hsmmc2,
146 &s3c_device_hsmmc3,
147 &s3c_device_rtc,
148 &s3c_device_wdt,
149 &smdkc210_smsc911x,
150};
151
152static void __init smdkc210_smsc911x_init(void)
153{
154 u32 cs1;
155
156 /* configure nCS1 width to 16 bits */
157 cs1 = __raw_readl(S5PV310_SROM_BW) &
158 ~(S5PV310_SROM_BW__CS_MASK <<
159 S5PV310_SROM_BW__NCS1__SHIFT);
160 cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
161 (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
162 (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
163 S5PV310_SROM_BW__NCS1__SHIFT;
164 __raw_writel(cs1, S5PV310_SROM_BW);
165
166 /* set timing for nCS1 suitable for ethernet chip */
167 __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
168 (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
169 (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
170 (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
171 (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
172 (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
173 (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
174}
175
176static void __init smdkc210_map_io(void)
177{
178 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
179 s3c24xx_init_clocks(24000000);
180 s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
181}
182
183static void __init smdkc210_machine_init(void)
184{
185 smdkc210_smsc911x_init();
186
187 s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
188 s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
189 s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
190 s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
191
192 platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
193}
194
195MACHINE_START(SMDKC210, "SMDKC210")
196 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
197 .boot_params = S5P_PA_SDRAM + 0x100,
198 .init_irq = s5pv310_init_irq,
199 .map_io = smdkc210_map_io,
200 .init_machine = smdkc210_machine_init,
201 .timer = &s5pv310_timer,
202MACHINE_END
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c
index 46215a14b3b..35826d66632 100644
--- a/arch/arm/mach-s5pv310/mach-smdkv310.c
+++ b/arch/arm/mach-s5pv310/mach-smdkv310.c
@@ -9,16 +9,23 @@
9*/ 9*/
10 10
11#include <linux/serial_core.h> 11#include <linux/serial_core.h>
12#include <linux/gpio.h>
13#include <linux/mmc/host.h>
14#include <linux/platform_device.h>
15#include <linux/smsc911x.h>
16#include <linux/io.h>
12 17
13#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
14#include <asm/mach-types.h> 19#include <asm/mach-types.h>
15#include <asm/hardware/cache-l2x0.h>
16 20
17#include <plat/regs-serial.h> 21#include <plat/regs-serial.h>
18#include <plat/s5pv310.h> 22#include <plat/s5pv310.h>
19#include <plat/cpu.h> 23#include <plat/cpu.h>
24#include <plat/devs.h>
25#include <plat/sdhci.h>
20 26
21#include <mach/map.h> 27#include <mach/map.h>
28#include <mach/regs-srom.h>
22 29
23/* Following are default values for UCON, ULCON and UFCON UART registers */ 30/* Following are default values for UCON, ULCON and UFCON UART registers */
24#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 31#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -65,6 +72,107 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
65 }, 72 },
66}; 73};
67 74
75static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
76 .cd_type = S3C_SDHCI_CD_GPIO,
77 .ext_cd_gpio = S5PV310_GPK0(2),
78 .ext_cd_gpio_invert = 1,
79 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
80#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
81 .max_width = 8,
82 .host_caps = MMC_CAP_8_BIT_DATA,
83#endif
84};
85
86static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
87 .cd_type = S3C_SDHCI_CD_GPIO,
88 .ext_cd_gpio = S5PV310_GPK0(2),
89 .ext_cd_gpio_invert = 1,
90 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
91};
92
93static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
94 .cd_type = S3C_SDHCI_CD_GPIO,
95 .ext_cd_gpio = S5PV310_GPK2(2),
96 .ext_cd_gpio_invert = 1,
97 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
98#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
99 .max_width = 8,
100 .host_caps = MMC_CAP_8_BIT_DATA,
101#endif
102};
103
104static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
105 .cd_type = S3C_SDHCI_CD_GPIO,
106 .ext_cd_gpio = S5PV310_GPK2(2),
107 .ext_cd_gpio_invert = 1,
108 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
109};
110
111static struct resource smdkv310_smsc911x_resources[] = {
112 [0] = {
113 .start = S5PV310_PA_SROM_BANK(1),
114 .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
115 .flags = IORESOURCE_MEM,
116 },
117 [1] = {
118 .start = IRQ_EINT(5),
119 .end = IRQ_EINT(5),
120 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
121 },
122};
123
124static struct smsc911x_platform_config smsc9215_config = {
125 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
126 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
127 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
128 .phy_interface = PHY_INTERFACE_MODE_MII,
129 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
130};
131
132static struct platform_device smdkv310_smsc911x = {
133 .name = "smsc911x",
134 .id = -1,
135 .num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources),
136 .resource = smdkv310_smsc911x_resources,
137 .dev = {
138 .platform_data = &smsc9215_config,
139 },
140};
141
142static struct platform_device *smdkv310_devices[] __initdata = {
143 &s3c_device_hsmmc0,
144 &s3c_device_hsmmc1,
145 &s3c_device_hsmmc2,
146 &s3c_device_hsmmc3,
147 &s3c_device_rtc,
148 &s3c_device_wdt,
149 &smdkv310_smsc911x,
150};
151
152static void __init smdkv310_smsc911x_init(void)
153{
154 u32 cs1;
155
156 /* configure nCS1 width to 16 bits */
157 cs1 = __raw_readl(S5PV310_SROM_BW) &
158 ~(S5PV310_SROM_BW__CS_MASK <<
159 S5PV310_SROM_BW__NCS1__SHIFT);
160 cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
161 (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
162 (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
163 S5PV310_SROM_BW__NCS1__SHIFT;
164 __raw_writel(cs1, S5PV310_SROM_BW);
165
166 /* set timing for nCS1 suitable for ethernet chip */
167 __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
168 (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
169 (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
170 (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
171 (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
172 (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
173 (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
174}
175
68static void __init smdkv310_map_io(void) 176static void __init smdkv310_map_io(void)
69{ 177{
70 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 178 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -74,9 +182,14 @@ static void __init smdkv310_map_io(void)
74 182
75static void __init smdkv310_machine_init(void) 183static void __init smdkv310_machine_init(void)
76{ 184{
77#ifdef CONFIG_CACHE_L2X0 185 smdkv310_smsc911x_init();
78 l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); 186
79#endif 187 s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
188 s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
189 s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
190 s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
191
192 platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
80} 193}
81 194
82MACHINE_START(SMDKV310, "SMDKV310") 195MACHINE_START(SMDKV310, "SMDKV310")
diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c
index d7c2ec770f8..16d8fc00caf 100644
--- a/arch/arm/mach-s5pv310/mach-universal_c210.c
+++ b/arch/arm/mach-s5pv310/mach-universal_c210.c
@@ -7,15 +7,20 @@
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
8*/ 8*/
9 9
10#include <linux/platform_device.h>
10#include <linux/serial_core.h> 11#include <linux/serial_core.h>
12#include <linux/input.h>
13#include <linux/i2c.h>
14#include <linux/gpio_keys.h>
15#include <linux/gpio.h>
11 16
12#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
13#include <asm/mach-types.h> 18#include <asm/mach-types.h>
14#include <asm/hardware/cache-l2x0.h>
15 19
16#include <plat/regs-serial.h> 20#include <plat/regs-serial.h>
17#include <plat/s5pv310.h> 21#include <plat/s5pv310.h>
18#include <plat/cpu.h> 22#include <plat/cpu.h>
23#include <plat/devs.h>
19 24
20#include <mach/map.h> 25#include <mach/map.h>
21 26
@@ -60,6 +65,72 @@ static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
60 }, 65 },
61}; 66};
62 67
68static struct gpio_keys_button universal_gpio_keys_tables[] = {
69 {
70 .code = KEY_VOLUMEUP,
71 .gpio = S5PV310_GPX2(0), /* XEINT16 */
72 .desc = "gpio-keys: KEY_VOLUMEUP",
73 .type = EV_KEY,
74 .active_low = 1,
75 .debounce_interval = 1,
76 }, {
77 .code = KEY_VOLUMEDOWN,
78 .gpio = S5PV310_GPX2(1), /* XEINT17 */
79 .desc = "gpio-keys: KEY_VOLUMEDOWN",
80 .type = EV_KEY,
81 .active_low = 1,
82 .debounce_interval = 1,
83 }, {
84 .code = KEY_CONFIG,
85 .gpio = S5PV310_GPX2(2), /* XEINT18 */
86 .desc = "gpio-keys: KEY_CONFIG",
87 .type = EV_KEY,
88 .active_low = 1,
89 .debounce_interval = 1,
90 }, {
91 .code = KEY_CAMERA,
92 .gpio = S5PV310_GPX2(3), /* XEINT19 */
93 .desc = "gpio-keys: KEY_CAMERA",
94 .type = EV_KEY,
95 .active_low = 1,
96 .debounce_interval = 1,
97 }, {
98 .code = KEY_OK,
99 .gpio = S5PV310_GPX3(5), /* XEINT29 */
100 .desc = "gpio-keys: KEY_OK",
101 .type = EV_KEY,
102 .active_low = 1,
103 .debounce_interval = 1,
104 },
105};
106
107static struct gpio_keys_platform_data universal_gpio_keys_data = {
108 .buttons = universal_gpio_keys_tables,
109 .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
110};
111
112static struct platform_device universal_gpio_keys = {
113 .name = "gpio-keys",
114 .dev = {
115 .platform_data = &universal_gpio_keys_data,
116 },
117};
118
119/* I2C0 */
120static struct i2c_board_info i2c0_devs[] __initdata = {
121 /* Camera, To be updated */
122};
123
124/* I2C1 */
125static struct i2c_board_info i2c1_devs[] __initdata = {
126 /* Gyro, To be updated */
127};
128
129static struct platform_device *universal_devices[] __initdata = {
130 &universal_gpio_keys,
131 &s5p_device_onenand,
132};
133
63static void __init universal_map_io(void) 134static void __init universal_map_io(void)
64{ 135{
65 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 136 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -69,9 +140,11 @@ static void __init universal_map_io(void)
69 140
70static void __init universal_machine_init(void) 141static void __init universal_machine_init(void)
71{ 142{
72#ifdef CONFIG_CACHE_L2X0 143 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
73 l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff); 144 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
74#endif 145
146 /* Last */
147 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
75} 148}
76 149
77MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") 150MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
diff --git a/arch/arm/mach-s5pv310/setup-i2c0.c b/arch/arm/mach-s5pv310/setup-i2c0.c
index 43671280738..f47f8f3152e 100644
--- a/arch/arm/mach-s5pv310/setup-i2c0.c
+++ b/arch/arm/mach-s5pv310/setup-i2c0.c
@@ -21,8 +21,6 @@ struct platform_device; /* don't need the contents */
21 21
22void s3c_i2c0_cfg_gpio(struct platform_device *dev) 22void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{ 23{
24 s3c_gpio_cfgpin(S5PV310_GPD1(0), S3C_GPIO_SFN(2)); 24 s3c_gpio_cfgall_range(S5PV310_GPD1(0), 2,
25 s3c_gpio_setpull(S5PV310_GPD1(0), S3C_GPIO_PULL_UP); 25 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
26 s3c_gpio_cfgpin(S5PV310_GPD1(1), S3C_GPIO_SFN(2));
27 s3c_gpio_setpull(S5PV310_GPD1(1), S3C_GPIO_PULL_UP);
28} 26}
diff --git a/arch/arm/mach-s5pv310/setup-i2c1.c b/arch/arm/mach-s5pv310/setup-i2c1.c
index 1ecd5bc35b5..9d07e4e2f14 100644
--- a/arch/arm/mach-s5pv310/setup-i2c1.c
+++ b/arch/arm/mach-s5pv310/setup-i2c1.c
@@ -18,8 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c1_cfg_gpio(struct platform_device *dev) 19void s3c_i2c1_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgpin(S5PV310_GPD1(2), S3C_GPIO_SFN(2)); 21 s3c_gpio_cfgall_range(S5PV310_GPD1(2), 2,
22 s3c_gpio_setpull(S5PV310_GPD1(2), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
23 s3c_gpio_cfgpin(S5PV310_GPD1(3), S3C_GPIO_SFN(2));
24 s3c_gpio_setpull(S5PV310_GPD1(3), S3C_GPIO_PULL_UP);
25} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c2.c b/arch/arm/mach-s5pv310/setup-i2c2.c
index 4c0d8def660..4163b1233da 100644
--- a/arch/arm/mach-s5pv310/setup-i2c2.c
+++ b/arch/arm/mach-s5pv310/setup-i2c2.c
@@ -18,8 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c2_cfg_gpio(struct platform_device *dev) 19void s3c_i2c2_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgpin(S5PV310_GPA0(6), S3C_GPIO_SFN(3)); 21 s3c_gpio_cfgall_range(S5PV310_GPA0(6), 2,
22 s3c_gpio_setpull(S5PV310_GPA0(6), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23 s3c_gpio_cfgpin(S5PV310_GPA0(7), S3C_GPIO_SFN(3));
24 s3c_gpio_setpull(S5PV310_GPA0(7), S3C_GPIO_PULL_UP);
25} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c3.c b/arch/arm/mach-s5pv310/setup-i2c3.c
new file mode 100644
index 00000000000..180f153d2a2
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-i2c3.c
@@ -0,0 +1,23 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c3.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C3 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c3_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(S5PV310_GPA1(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c4.c b/arch/arm/mach-s5pv310/setup-i2c4.c
new file mode 100644
index 00000000000..909e8dfc531
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-i2c4.c
@@ -0,0 +1,23 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c4.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C4 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c4_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(S5PV310_GPB(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c5.c b/arch/arm/mach-s5pv310/setup-i2c5.c
new file mode 100644
index 00000000000..5d0fa4ac028
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-i2c5.c
@@ -0,0 +1,23 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c5.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C5 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c5_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(S5PV310_GPB(6), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c6.c b/arch/arm/mach-s5pv310/setup-i2c6.c
new file mode 100644
index 00000000000..34aafab92ac
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-i2c6.c
@@ -0,0 +1,23 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c6.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C6 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c6_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(S5PV310_GPC1(3), 2,
22 S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c7.c b/arch/arm/mach-s5pv310/setup-i2c7.c
new file mode 100644
index 00000000000..9b25b8d1892
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-i2c7.c
@@ -0,0 +1,23 @@
1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c7.c
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 *
6 * I2C7 GPIO configuration.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct platform_device; /* don't need the contents */
14
15#include <linux/gpio.h>
16#include <plat/iic.h>
17#include <plat/gpio-cfg.h>
18
19void s3c_i2c7_cfg_gpio(struct platform_device *dev)
20{
21 s3c_gpio_cfgall_range(S5PV310_GPD0(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23}
diff --git a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
new file mode 100644
index 00000000000..86d38cc4913
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
@@ -0,0 +1,152 @@
1/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19#include <linux/mmc/host.h>
20#include <linux/mmc/card.h>
21
22#include <plat/gpio-cfg.h>
23#include <plat/regs-sdhci.h>
24#include <plat/sdhci.h>
25
26void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
27{
28 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
29 unsigned int gpio;
30
31 /* Set all the necessary GPK0[0:1] pins to special-function 2 */
32 for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) {
33 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
34 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
35 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
36 }
37
38 switch (width) {
39 case 8:
40 for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
41 /* Data pin GPK1[3:6] to special-funtion 3 */
42 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
43 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
44 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
45 }
46 case 4:
47 for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) {
48 /* Data pin GPK0[3:6] to special-funtion 2 */
49 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
50 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
51 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
52 }
53 default:
54 break;
55 }
56
57 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
58 s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2));
59 s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP);
60 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
61 }
62}
63
64void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
65{
66 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
67 unsigned int gpio;
68
69 /* Set all the necessary GPK1[0:1] pins to special-function 2 */
70 for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) {
71 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
72 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
73 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
74 }
75
76 for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
77 /* Data pin GPK1[3:6] to special-function 2 */
78 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
79 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
80 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
81 }
82
83 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
84 s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2));
85 s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP);
86 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
87 }
88}
89
90void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
91{
92 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
93 unsigned int gpio;
94
95 /* Set all the necessary GPK2[0:1] pins to special-function 2 */
96 for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) {
97 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
98 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
99 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
100 }
101
102 switch (width) {
103 case 8:
104 for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
105 /* Data pin GPK3[3:6] to special-function 3 */
106 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
107 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
108 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
109 }
110 case 4:
111 for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) {
112 /* Data pin GPK2[3:6] to special-function 2 */
113 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
114 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
115 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
116 }
117 default:
118 break;
119 }
120
121 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
122 s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2));
123 s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP);
124 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
125 }
126}
127
128void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
129{
130 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
131 unsigned int gpio;
132
133 /* Set all the necessary GPK3[0:1] pins to special-function 2 */
134 for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) {
135 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
136 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
137 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
138 }
139
140 for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
141 /* Data pin GPK3[3:6] to special-function 2 */
142 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
143 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
144 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
145 }
146
147 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
148 s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2));
149 s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP);
150 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
151 }
152}
diff --git a/arch/arm/mach-s5pv310/setup-sdhci.c b/arch/arm/mach-s5pv310/setup-sdhci.c
new file mode 100644
index 00000000000..db8358fc466
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-sdhci.c
@@ -0,0 +1,69 @@
1/* linux/arch/arm/mach-s5pv310/setup-sdhci.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <linux/mmc/card.h>
20#include <linux/mmc/host.h>
21
22#include <plat/regs-sdhci.h>
23
24/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
25
26char *s5pv310_hsmmc_clksrcs[4] = {
27 [0] = NULL,
28 [1] = NULL,
29 [2] = "sclk_mmc", /* mmc_bus */
30 [3] = NULL,
31};
32
33void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
34 struct mmc_ios *ios, struct mmc_card *card)
35{
36 u32 ctrl2, ctrl3;
37
38 /* don't need to alter anything acording to card-type */
39
40 ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
41
42 /* select base clock source to HCLK */
43
44 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
45
46 /*
47 * clear async mode, enable conflict mask, rx feedback ctrl, SD
48 * clk hold and no use debounce count
49 */
50
51 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
52 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
53 S3C_SDHCI_CTRL2_ENFBCLKRX |
54 S3C_SDHCI_CTRL2_DFCNT_NONE |
55 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
56
57 /* Tx and Rx feedback clock delay control */
58
59 if (ios->clock < 25 * 1000000)
60 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
61 S3C_SDHCI_CTRL3_FCSEL2 |
62 S3C_SDHCI_CTRL3_FCSEL1 |
63 S3C_SDHCI_CTRL3_FCSEL0);
64 else
65 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
66
67 writel(ctrl2, r + S3C_SDHCI_CONTROL2);
68 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
69}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 06:21:02 -0500