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Diffstat (limited to 'arch/arm/mach-s5pv310/clock.c')
-rw-r--r--arch/arm/mach-s5pv310/clock.c28
1 files changed, 21 insertions, 7 deletions
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 6d22c43c6ee..753fa446587 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -244,7 +244,7 @@ static struct clksrc_clk clk_mout_corebus = {
244 .id = -1, 244 .id = -1,
245 }, 245 },
246 .sources = &clkset_mout_corebus, 246 .sources = &clkset_mout_corebus,
247 .reg_src = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 }, 247 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
248}; 248};
249 249
250static struct clksrc_clk clk_sclk_dmc = { 250static struct clksrc_clk clk_sclk_dmc = {
@@ -253,7 +253,7 @@ static struct clksrc_clk clk_sclk_dmc = {
253 .id = -1, 253 .id = -1,
254 .parent = &clk_mout_corebus.clk, 254 .parent = &clk_mout_corebus.clk,
255 }, 255 },
256 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 }, 256 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
257}; 257};
258 258
259static struct clksrc_clk clk_aclk_cored = { 259static struct clksrc_clk clk_aclk_cored = {
@@ -262,7 +262,7 @@ static struct clksrc_clk clk_aclk_cored = {
262 .id = -1, 262 .id = -1,
263 .parent = &clk_sclk_dmc.clk, 263 .parent = &clk_sclk_dmc.clk,
264 }, 264 },
265 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 }, 265 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
266}; 266};
267 267
268static struct clksrc_clk clk_aclk_corep = { 268static struct clksrc_clk clk_aclk_corep = {
@@ -271,7 +271,7 @@ static struct clksrc_clk clk_aclk_corep = {
271 .id = -1, 271 .id = -1,
272 .parent = &clk_aclk_cored.clk, 272 .parent = &clk_aclk_cored.clk,
273 }, 273 },
274 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 }, 274 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
275}; 275};
276 276
277static struct clksrc_clk clk_aclk_acp = { 277static struct clksrc_clk clk_aclk_acp = {
@@ -280,7 +280,7 @@ static struct clksrc_clk clk_aclk_acp = {
280 .id = -1, 280 .id = -1,
281 .parent = &clk_mout_corebus.clk, 281 .parent = &clk_mout_corebus.clk,
282 }, 282 },
283 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 }, 283 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
284}; 284};
285 285
286static struct clksrc_clk clk_pclk_acp = { 286static struct clksrc_clk clk_pclk_acp = {
@@ -289,7 +289,7 @@ static struct clksrc_clk clk_pclk_acp = {
289 .id = -1, 289 .id = -1,
290 .parent = &clk_aclk_acp.clk, 290 .parent = &clk_aclk_acp.clk,
291 }, 291 },
292 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 }, 292 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
293}; 293};
294 294
295/* Core list of CMU_TOP side */ 295/* Core list of CMU_TOP side */
@@ -1020,6 +1020,17 @@ static struct clksrc_clk *sysclks[] = {
1020 &clk_dout_mmc4, 1020 &clk_dout_mmc4,
1021}; 1021};
1022 1022
1023static int xtal_rate;
1024
1025static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk)
1026{
1027 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1028}
1029
1030static struct clk_ops s5pv310_fout_apll_ops = {
1031 .get_rate = s5pv310_fout_apll_get_rate,
1032};
1033
1023void __init_or_cpufreq s5pv310_setup_clocks(void) 1034void __init_or_cpufreq s5pv310_setup_clocks(void)
1024{ 1035{
1025 struct clk *xtal_clk; 1036 struct clk *xtal_clk;
@@ -1043,6 +1054,9 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
1043 BUG_ON(IS_ERR(xtal_clk)); 1054 BUG_ON(IS_ERR(xtal_clk));
1044 1055
1045 xtal = clk_get_rate(xtal_clk); 1056 xtal = clk_get_rate(xtal_clk);
1057
1058 xtal_rate = xtal;
1059
1046 clk_put(xtal_clk); 1060 clk_put(xtal_clk);
1047 1061
1048 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); 1062 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
@@ -1056,7 +1070,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
1056 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 1070 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1057 __raw_readl(S5P_VPLL_CON1), pll_4650); 1071 __raw_readl(S5P_VPLL_CON1), pll_4650);
1058 1072
1059 clk_fout_apll.rate = apll; 1073 clk_fout_apll.ops = &s5pv310_fout_apll_ops;
1060 clk_fout_mpll.rate = mpll; 1074 clk_fout_mpll.rate = mpll;
1061 clk_fout_epll.rate = epll; 1075 clk_fout_epll.rate = epll;
1062 clk_fout_vpll.rate = vpll; 1076 clk_fout_vpll.rate = vpll;