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-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c519
1 files changed, 515 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 12d939e456c..8ecfbcde13b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -16,11 +16,14 @@
16#include <plat/cpu.h> 16#include <plat/cpu.h>
17#include <plat/dma.h> 17#include <plat/dma.h>
18#include <plat/serial.h> 18#include <plat/serial.h>
19#include <plat/i2c.h>
20#include <plat/gpio.h>
19 21
20#include "omap_hwmod_common_data.h" 22#include "omap_hwmod_common_data.h"
21 23
22#include "prm-regbits-24xx.h" 24#include "prm-regbits-24xx.h"
23#include "cm-regbits-24xx.h" 25#include "cm-regbits-24xx.h"
26#include "wd_timer.h"
24 27
25/* 28/*
26 * OMAP2430 hardware module integration data 29 * OMAP2430 hardware module integration data
@@ -36,6 +39,12 @@ static struct omap_hwmod omap2430_iva_hwmod;
36static struct omap_hwmod omap2430_l3_main_hwmod; 39static struct omap_hwmod omap2430_l3_main_hwmod;
37static struct omap_hwmod omap2430_l4_core_hwmod; 40static struct omap_hwmod omap2430_l4_core_hwmod;
38static struct omap_hwmod omap2430_wd_timer2_hwmod; 41static struct omap_hwmod omap2430_wd_timer2_hwmod;
42static struct omap_hwmod omap2430_gpio1_hwmod;
43static struct omap_hwmod omap2430_gpio2_hwmod;
44static struct omap_hwmod omap2430_gpio3_hwmod;
45static struct omap_hwmod omap2430_gpio4_hwmod;
46static struct omap_hwmod omap2430_gpio5_hwmod;
47static struct omap_hwmod omap2430_dma_system_hwmod;
39 48
40/* L3 -> L4_CORE interface */ 49/* L3 -> L4_CORE interface */
41static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { 50static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -77,6 +86,47 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod;
77static struct omap_hwmod omap2430_uart1_hwmod; 86static struct omap_hwmod omap2430_uart1_hwmod;
78static struct omap_hwmod omap2430_uart2_hwmod; 87static struct omap_hwmod omap2430_uart2_hwmod;
79static struct omap_hwmod omap2430_uart3_hwmod; 88static struct omap_hwmod omap2430_uart3_hwmod;
89static struct omap_hwmod omap2430_i2c1_hwmod;
90static struct omap_hwmod omap2430_i2c2_hwmod;
91
92/* I2C IP block address space length (in bytes) */
93#define OMAP2_I2C_AS_LEN 128
94
95/* L4 CORE -> I2C1 interface */
96static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
97 {
98 .pa_start = 0x48070000,
99 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
100 .flags = ADDR_TYPE_RT,
101 },
102};
103
104static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
105 .master = &omap2430_l4_core_hwmod,
106 .slave = &omap2430_i2c1_hwmod,
107 .clk = "i2c1_ick",
108 .addr = omap2430_i2c1_addr_space,
109 .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space),
110 .user = OCP_USER_MPU | OCP_USER_SDMA,
111};
112
113/* L4 CORE -> I2C2 interface */
114static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
115 {
116 .pa_start = 0x48072000,
117 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
118 .flags = ADDR_TYPE_RT,
119 },
120};
121
122static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
123 .master = &omap2430_l4_core_hwmod,
124 .slave = &omap2430_i2c2_hwmod,
125 .clk = "i2c2_ick",
126 .addr = omap2430_i2c2_addr_space,
127 .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space),
128 .user = OCP_USER_MPU | OCP_USER_SDMA,
129};
80 130
81/* L4_CORE -> L4_WKUP interface */ 131/* L4_CORE -> L4_WKUP interface */
82static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { 132static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
@@ -262,8 +312,9 @@ static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
262}; 312};
263 313
264static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { 314static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
265 .name = "wd_timer", 315 .name = "wd_timer",
266 .sysc = &omap2430_wd_timer_sysc, 316 .sysc = &omap2430_wd_timer_sysc,
317 .pre_shutdown = &omap2_wd_timer_disable
267}; 318};
268 319
269/* wd_timer2 */ 320/* wd_timer2 */
@@ -418,6 +469,456 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
418 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 469 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
419}; 470};
420 471
472/* I2C common */
473static struct omap_hwmod_class_sysconfig i2c_sysc = {
474 .rev_offs = 0x00,
475 .sysc_offs = 0x20,
476 .syss_offs = 0x10,
477 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
478 .sysc_fields = &omap_hwmod_sysc_type1,
479};
480
481static struct omap_hwmod_class i2c_class = {
482 .name = "i2c",
483 .sysc = &i2c_sysc,
484};
485
486static struct omap_i2c_dev_attr i2c_dev_attr = {
487 .fifo_depth = 8, /* bytes */
488};
489
490/* I2C1 */
491
492static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
493 { .irq = INT_24XX_I2C1_IRQ, },
494};
495
496static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
497 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
498 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
499};
500
501static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
502 &omap2430_l4_core__i2c1,
503};
504
505static struct omap_hwmod omap2430_i2c1_hwmod = {
506 .name = "i2c1",
507 .mpu_irqs = i2c1_mpu_irqs,
508 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
509 .sdma_reqs = i2c1_sdma_reqs,
510 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
511 .main_clk = "i2chs1_fck",
512 .prcm = {
513 .omap2 = {
514 /*
515 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
516 * I2CHS IP's do not follow the usual pattern.
517 * prcm_reg_id alone cannot be used to program
518 * the iclk and fclk. Needs to be handled using
519 * additonal flags when clk handling is moved
520 * to hwmod framework.
521 */
522 .module_offs = CORE_MOD,
523 .prcm_reg_id = 1,
524 .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
525 .idlest_reg_id = 1,
526 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
527 },
528 },
529 .slaves = omap2430_i2c1_slaves,
530 .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves),
531 .class = &i2c_class,
532 .dev_attr = &i2c_dev_attr,
533 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
534};
535
536/* I2C2 */
537
538static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
539 { .irq = INT_24XX_I2C2_IRQ, },
540};
541
542static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
543 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
544 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
545};
546
547static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
548 &omap2430_l4_core__i2c2,
549};
550
551static struct omap_hwmod omap2430_i2c2_hwmod = {
552 .name = "i2c2",
553 .mpu_irqs = i2c2_mpu_irqs,
554 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
555 .sdma_reqs = i2c2_sdma_reqs,
556 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
557 .main_clk = "i2chs2_fck",
558 .prcm = {
559 .omap2 = {
560 .module_offs = CORE_MOD,
561 .prcm_reg_id = 1,
562 .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
563 .idlest_reg_id = 1,
564 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
565 },
566 },
567 .slaves = omap2430_i2c2_slaves,
568 .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves),
569 .class = &i2c_class,
570 .dev_attr = &i2c_dev_attr,
571 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
572};
573
574/* l4_wkup -> gpio1 */
575static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
576 {
577 .pa_start = 0x4900C000,
578 .pa_end = 0x4900C1ff,
579 .flags = ADDR_TYPE_RT
580 },
581};
582
583static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
584 .master = &omap2430_l4_wkup_hwmod,
585 .slave = &omap2430_gpio1_hwmod,
586 .clk = "gpios_ick",
587 .addr = omap2430_gpio1_addr_space,
588 .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space),
589 .user = OCP_USER_MPU | OCP_USER_SDMA,
590};
591
592/* l4_wkup -> gpio2 */
593static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
594 {
595 .pa_start = 0x4900E000,
596 .pa_end = 0x4900E1ff,
597 .flags = ADDR_TYPE_RT
598 },
599};
600
601static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
602 .master = &omap2430_l4_wkup_hwmod,
603 .slave = &omap2430_gpio2_hwmod,
604 .clk = "gpios_ick",
605 .addr = omap2430_gpio2_addr_space,
606 .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space),
607 .user = OCP_USER_MPU | OCP_USER_SDMA,
608};
609
610/* l4_wkup -> gpio3 */
611static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
612 {
613 .pa_start = 0x49010000,
614 .pa_end = 0x490101ff,
615 .flags = ADDR_TYPE_RT
616 },
617};
618
619static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
620 .master = &omap2430_l4_wkup_hwmod,
621 .slave = &omap2430_gpio3_hwmod,
622 .clk = "gpios_ick",
623 .addr = omap2430_gpio3_addr_space,
624 .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space),
625 .user = OCP_USER_MPU | OCP_USER_SDMA,
626};
627
628/* l4_wkup -> gpio4 */
629static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
630 {
631 .pa_start = 0x49012000,
632 .pa_end = 0x490121ff,
633 .flags = ADDR_TYPE_RT
634 },
635};
636
637static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
638 .master = &omap2430_l4_wkup_hwmod,
639 .slave = &omap2430_gpio4_hwmod,
640 .clk = "gpios_ick",
641 .addr = omap2430_gpio4_addr_space,
642 .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space),
643 .user = OCP_USER_MPU | OCP_USER_SDMA,
644};
645
646/* l4_core -> gpio5 */
647static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
648 {
649 .pa_start = 0x480B6000,
650 .pa_end = 0x480B61ff,
651 .flags = ADDR_TYPE_RT
652 },
653};
654
655static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
656 .master = &omap2430_l4_core_hwmod,
657 .slave = &omap2430_gpio5_hwmod,
658 .clk = "gpio5_ick",
659 .addr = omap2430_gpio5_addr_space,
660 .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space),
661 .user = OCP_USER_MPU | OCP_USER_SDMA,
662};
663
664/* gpio dev_attr */
665static struct omap_gpio_dev_attr gpio_dev_attr = {
666 .bank_width = 32,
667 .dbck_flag = false,
668};
669
670static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
671 .rev_offs = 0x0000,
672 .sysc_offs = 0x0010,
673 .syss_offs = 0x0014,
674 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
675 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
676 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
677 .sysc_fields = &omap_hwmod_sysc_type1,
678};
679
680/*
681 * 'gpio' class
682 * general purpose io module
683 */
684static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
685 .name = "gpio",
686 .sysc = &omap243x_gpio_sysc,
687 .rev = 0,
688};
689
690/* gpio1 */
691static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
692 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
693};
694
695static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
696 &omap2430_l4_wkup__gpio1,
697};
698
699static struct omap_hwmod omap2430_gpio1_hwmod = {
700 .name = "gpio1",
701 .mpu_irqs = omap243x_gpio1_irqs,
702 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
703 .main_clk = "gpios_fck",
704 .prcm = {
705 .omap2 = {
706 .prcm_reg_id = 1,
707 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
708 .module_offs = WKUP_MOD,
709 .idlest_reg_id = 1,
710 .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
711 },
712 },
713 .slaves = omap2430_gpio1_slaves,
714 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
715 .class = &omap243x_gpio_hwmod_class,
716 .dev_attr = &gpio_dev_attr,
717 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
718};
719
720/* gpio2 */
721static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
722 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
723};
724
725static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
726 &omap2430_l4_wkup__gpio2,
727};
728
729static struct omap_hwmod omap2430_gpio2_hwmod = {
730 .name = "gpio2",
731 .mpu_irqs = omap243x_gpio2_irqs,
732 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
733 .main_clk = "gpios_fck",
734 .prcm = {
735 .omap2 = {
736 .prcm_reg_id = 1,
737 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
738 .module_offs = WKUP_MOD,
739 .idlest_reg_id = 1,
740 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
741 },
742 },
743 .slaves = omap2430_gpio2_slaves,
744 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
745 .class = &omap243x_gpio_hwmod_class,
746 .dev_attr = &gpio_dev_attr,
747 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
748};
749
750/* gpio3 */
751static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
752 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
753};
754
755static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
756 &omap2430_l4_wkup__gpio3,
757};
758
759static struct omap_hwmod omap2430_gpio3_hwmod = {
760 .name = "gpio3",
761 .mpu_irqs = omap243x_gpio3_irqs,
762 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
763 .main_clk = "gpios_fck",
764 .prcm = {
765 .omap2 = {
766 .prcm_reg_id = 1,
767 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
768 .module_offs = WKUP_MOD,
769 .idlest_reg_id = 1,
770 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
771 },
772 },
773 .slaves = omap2430_gpio3_slaves,
774 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
775 .class = &omap243x_gpio_hwmod_class,
776 .dev_attr = &gpio_dev_attr,
777 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
778};
779
780/* gpio4 */
781static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
782 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
783};
784
785static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
786 &omap2430_l4_wkup__gpio4,
787};
788
789static struct omap_hwmod omap2430_gpio4_hwmod = {
790 .name = "gpio4",
791 .mpu_irqs = omap243x_gpio4_irqs,
792 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
793 .main_clk = "gpios_fck",
794 .prcm = {
795 .omap2 = {
796 .prcm_reg_id = 1,
797 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
798 .module_offs = WKUP_MOD,
799 .idlest_reg_id = 1,
800 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
801 },
802 },
803 .slaves = omap2430_gpio4_slaves,
804 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
805 .class = &omap243x_gpio_hwmod_class,
806 .dev_attr = &gpio_dev_attr,
807 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
808};
809
810/* gpio5 */
811static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
812 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
813};
814
815static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
816 &omap2430_l4_core__gpio5,
817};
818
819static struct omap_hwmod omap2430_gpio5_hwmod = {
820 .name = "gpio5",
821 .mpu_irqs = omap243x_gpio5_irqs,
822 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
823 .main_clk = "gpio5_fck",
824 .prcm = {
825 .omap2 = {
826 .prcm_reg_id = 2,
827 .module_bit = OMAP2430_EN_GPIO5_SHIFT,
828 .module_offs = CORE_MOD,
829 .idlest_reg_id = 2,
830 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
831 },
832 },
833 .slaves = omap2430_gpio5_slaves,
834 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
835 .class = &omap243x_gpio_hwmod_class,
836 .dev_attr = &gpio_dev_attr,
837 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
838};
839
840/* dma_system */
841static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
842 .rev_offs = 0x0000,
843 .sysc_offs = 0x002c,
844 .syss_offs = 0x0028,
845 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
846 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
847 SYSC_HAS_AUTOIDLE),
848 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
849 .sysc_fields = &omap_hwmod_sysc_type1,
850};
851
852static struct omap_hwmod_class omap2430_dma_hwmod_class = {
853 .name = "dma",
854 .sysc = &omap2430_dma_sysc,
855};
856
857/* dma attributes */
858static struct omap_dma_dev_attr dma_dev_attr = {
859 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
860 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
861 .lch_count = 32,
862};
863
864static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
865 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
866 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
867 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
868 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
869};
870
871static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
872 {
873 .pa_start = 0x48056000,
874 .pa_end = 0x4a0560ff,
875 .flags = ADDR_TYPE_RT
876 },
877};
878
879/* dma_system -> L3 */
880static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
881 .master = &omap2430_dma_system_hwmod,
882 .slave = &omap2430_l3_main_hwmod,
883 .clk = "core_l3_ck",
884 .user = OCP_USER_MPU | OCP_USER_SDMA,
885};
886
887/* dma_system master ports */
888static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
889 &omap2430_dma_system__l3,
890};
891
892/* l4_core -> dma_system */
893static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
894 .master = &omap2430_l4_core_hwmod,
895 .slave = &omap2430_dma_system_hwmod,
896 .clk = "sdma_ick",
897 .addr = omap2430_dma_system_addrs,
898 .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs),
899 .user = OCP_USER_MPU | OCP_USER_SDMA,
900};
901
902/* dma_system slave ports */
903static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
904 &omap2430_l4_core__dma_system,
905};
906
907static struct omap_hwmod omap2430_dma_system_hwmod = {
908 .name = "dma",
909 .class = &omap2430_dma_hwmod_class,
910 .mpu_irqs = omap2430_dma_system_irqs,
911 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs),
912 .main_clk = "core_l3_ck",
913 .slaves = omap2430_dma_system_slaves,
914 .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
915 .masters = omap2430_dma_system_masters,
916 .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters),
917 .dev_attr = &dma_dev_attr,
918 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
919 .flags = HWMOD_NO_IDLEST,
920};
921
421static __initdata struct omap_hwmod *omap2430_hwmods[] = { 922static __initdata struct omap_hwmod *omap2430_hwmods[] = {
422 &omap2430_l3_main_hwmod, 923 &omap2430_l3_main_hwmod,
423 &omap2430_l4_core_hwmod, 924 &omap2430_l4_core_hwmod,
@@ -428,6 +929,18 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
428 &omap2430_uart1_hwmod, 929 &omap2430_uart1_hwmod,
429 &omap2430_uart2_hwmod, 930 &omap2430_uart2_hwmod,
430 &omap2430_uart3_hwmod, 931 &omap2430_uart3_hwmod,
932 &omap2430_i2c1_hwmod,
933 &omap2430_i2c2_hwmod,
934
935 /* gpio class */
936 &omap2430_gpio1_hwmod,
937 &omap2430_gpio2_hwmod,
938 &omap2430_gpio3_hwmod,
939 &omap2430_gpio4_hwmod,
940 &omap2430_gpio5_hwmod,
941
942 /* dma_system class*/
943 &omap2430_dma_system_hwmod,
431 NULL, 944 NULL,
432}; 945};
433 946
@@ -435,5 +948,3 @@ int __init omap2430_hwmod_init(void)
435{ 948{
436 return omap_hwmod_init(omap2430_hwmods); 949 return omap_hwmod_init(omap2430_hwmods);
437} 950}
438
439
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 09:50:23 -0400